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From: Jani Nikula <jani.nikula@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, Nischal Varide <nischal.varide@intel.com>
Subject: [Intel-gfx] [PATCH 5/9] drm/i915/reg: add stream splitter configuration definitions
Date: Mon, 25 Jan 2021 17:52:29 +0200	[thread overview]
Message-ID: <c0605ffe6177a313f85ce2d6ad0ba05a90288854.1611589818.git.jani.nikula@intel.com> (raw)
In-Reply-To: <cover.1611589818.git.jani.nikula@intel.com>

The splitter configuration is required for eDP MSO.

Bspec: 50174
Cc: Nischal Varide <nischal.varide@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b9bbc6bacb1..d279ff03827f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11402,6 +11402,9 @@ enum skl_power_gate {
 #define  BIG_JOINER_ENABLE			(1 << 29)
 #define  MASTER_BIG_JOINER_ENABLE		(1 << 28)
 #define  VGA_CENTERING_ENABLE			(1 << 27)
+#define  SPLITTER_CONFIGURATION_MASK		REG_GENMASK(26, 25)
+#define  SPLITTER_CONFIGURATION_2_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
+#define  SPLITTER_CONFIGURATION_4_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
 
 #define _ICL_PIPE_DSS_CTL2_PB			0x78204
 #define _ICL_PIPE_DSS_CTL2_PC			0x78404
-- 
2.20.1

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  parent reply	other threads:[~2021-01-25 15:53 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-25 15:52 [Intel-gfx] [PATCH 0/9] drm/i915/edp: enable MSO... maybe Jani Nikula
2021-01-25 15:52 ` [PATCH 1/9] drm/dp: add MSO related DPCD registers Jani Nikula
2021-01-25 15:52   ` [Intel-gfx] " Jani Nikula
2021-01-25 15:52 ` [Intel-gfx] [PATCH 2/9] drm/i915/edp: reject modes with dimensions other than fixed mode Jani Nikula
2021-01-25 16:40   ` Ville Syrjälä
2021-01-25 15:52 ` [Intel-gfx] [PATCH 3/9] drm/i915/edp: always add fixed mode to probed modes in ->get_modes() Jani Nikula
2021-01-25 15:52 ` [Intel-gfx] [PATCH 4/9] drm/i915/edp: read sink MSO configuration for eDP 1.4+ Jani Nikula
2021-01-25 15:52 ` Jani Nikula [this message]
2021-01-25 15:52 ` [Intel-gfx] [PATCH 6/9] drm/i915/mso: add state readout for platforms that support it Jani Nikula
2021-01-25 16:43   ` Ville Syrjälä
2021-01-25 15:52 ` [Intel-gfx] [PATCH 7/9] drm/i915/mso: add state check Jani Nikula
2021-01-25 15:52 ` [Intel-gfx] [PATCH 8/9] drm/i915/edp: modify fixed and downclock modes for MSO Jani Nikula
2021-01-25 15:52 ` [Intel-gfx] [PATCH 9/9] drm/i915/edp: enable eDP MSO during link training Jani Nikula
2021-01-25 18:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/edp: enable MSO... maybe Patchwork
2021-01-25 19:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-26  0:49 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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