From: Jan Beulich <jbeulich@suse.com>
To: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Cc: Stefano Stabellini <sstabellini@kernel.org>,
Julien Grall <julien@xen.org>, Wei Liu <wl@xen.org>,
Konrad Wilk <konrad.wilk@oracle.com>,
George Dunlap <George.Dunlap@eu.citrix.com>,
Andrew Cooper <andrew.cooper3@citrix.com>,
Ian Jackson <ian.jackson@citrix.com>
Subject: [Xen-devel] [PATCH] IRQ: u16 is too narrow for an event channel number
Date: Tue, 14 Jan 2020 11:02:02 +0100 [thread overview]
Message-ID: <cb84362c-d175-7a71-89cc-17ce0c523b09@suse.com> (raw)
FIFO event channels allow ports up to 2^17, so we need to use a wider
field in struct pirq. Move "masked" such that it may share the 8-byte
slot with struct arch_pirq on 64-bit arches, rather than leaving a
7-byte hole in all cases.
Take the opportunity and also add a comment regarding "arch" placement
within the structure.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/include/xen/irq.h
+++ b/xen/include/xen/irq.h
@@ -127,9 +127,10 @@ struct vcpu;
struct pirq {
int pirq;
- u16 evtchn;
- bool_t masked;
+ evtchn_port_t evtchn;
struct rcu_head rcu_head;
+ bool masked;
+ /* Architectures may require this field to be last. */
struct arch_pirq arch;
};
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next reply other threads:[~2020-01-14 10:02 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-14 10:02 Jan Beulich [this message]
2020-01-14 10:16 ` [Xen-devel] [PATCH] IRQ: u16 is too narrow for an event channel number Julien Grall
2020-01-14 10:23 ` Jan Beulich
2020-01-14 10:39 ` Julien Grall
2020-01-14 10:41 ` Andrew Cooper
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