From: Leonard Crestez <leonard.crestez@nxp.com> To: Stephen Boyd <sboyd@kernel.org>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Rob Herring <robh+dt@kernel.org> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>, "Shawn Guo" <shawnguo@kernel.org>, "Chanwoo Choi" <cw00.choi@samsung.com>, "Mark Rutland" <mark.rutland@arm.com>, "Michael Turquette" <mturquette@baylibre.com>, "Artur Świgoń" <a.swigon@partner.samsung.com>, "Saravana Kannan" <saravanak@google.com>, "Angus Ainslie" <angus@akkea.ca>, "Martin Kepplinger" <martink@posteo.de>, "Matthias Kaehlcke" <mka@chromium.org>, "Krzysztof Kozlowski" <krzk@kernel.org>, "Alexandre Bailon" <abailon@baylibre.com>, "Georgi Djakov" <georgi.djakov@linaro.org>, "Dong Aisheng" <aisheng.dong@nxp.com>, "Abel Vesa" <abel.vesa@nxp.com>, "Jacky Bai" <ping.bai@nxp.com>, "Anson Huang" <Anson.Huang@nxp.com>, "Fabio Estevam" <fabio.estevam@nxp.com>, "Viresh Kumar" <viresh.kumar@linaro.org>, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 0/6] PM / devfreq: Add dynamic scaling for imx8m ddr controller Date: Sat, 9 Nov 2019 00:39:50 +0200 [thread overview] Message-ID: <cover.1573252696.git.leonard.crestez@nxp.com> (raw) This adds support for dynamic scaling of the DDR Controller (ddrc) present in imx8m series. Actual frequency switching is implemented inside TF-A, this driver wraps the SMC calls and synchronizes the clk tree. DRAM frequency switching requires clock manipulation but during this operation DRAM itself is briefly inaccessible so this operation is performed a SMC call to by TF-A which runs from a SRAM area. Upon returning to linux the clock tree is updated to correspond to hardware configuration. This is handled via CLK_GET_RATE_NO_CACHE for dividers but muxes are handled manually: the driver will prepare/enable the new parents ahead of switching (so that the expected roots are enabled) and afterwards it will call clk_set_parent to ensure the parents in clock framework are up-to-date. This series is atomically useful and roughly similar to devfreq drivers for tegra and rockchip. Running at lower dram rates saves power but can affect the functionality of other blocks in the chip (display, vpu etc). Support for in-kernel constraints will some separately. Angus/Martin: You previously attempted to test on purism boards, this updated version should work without hacks and has no dependencies. Changes since v3: * Rename to imx8m-ddrc. Similar blocks are present on imx7d and imx8qxp/imx8qm but soc integration is different. * Move dt bindings to /memory-controllers/fsl/ * Fix dt validation issues * Fix imx8mm.dtsi ddrc referencing ddrc_opp_table which is only defined in evk * Move opps to child of ddrc device node * Only add imx_ddrc_get_dev_status in perf patch. * Adjust print messages Link to v3: https://patchwork.kernel.org/cover/11221935/ Leonard Crestez (6): clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocks clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE dt-bindings: memory: Add bindings for imx8m ddr controller PM / devfreq: Add dynamic scaling for imx8m ddr controller PM / devfreq: imx8m-ddrc: Measure bandwidth with perf arm64: dts: imx8m: Add ddr controller nodes .../memory-controllers/fsl/imx8m-ddrc.yaml | 61 ++ arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 18 + arch/arm64/boot/dts/freescale/imx8mm.dtsi | 13 +- .../boot/dts/freescale/imx8mn-ddr4-evk.dts | 18 + arch/arm64/boot/dts/freescale/imx8mn.dtsi | 13 +- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 24 + arch/arm64/boot/dts/freescale/imx8mq.dtsi | 13 +- drivers/clk/imx/clk-imx8mm.c | 13 +- drivers/clk/imx/clk-imx8mn.c | 14 +- drivers/clk/imx/clk-imx8mq.c | 15 +- drivers/clk/imx/clk-pll14xx.c | 7 + drivers/clk/imx/clk.h | 1 + drivers/devfreq/Kconfig | 10 + drivers/devfreq/Makefile | 1 + drivers/devfreq/imx8m-ddrc.c | 569 ++++++++++++++++++ 15 files changed, 777 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml create mode 100644 drivers/devfreq/imx8m-ddrc.c -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Leonard Crestez <leonard.crestez@nxp.com> To: Stephen Boyd <sboyd@kernel.org>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Rob Herring <robh+dt@kernel.org> Cc: "Mark Rutland" <mark.rutland@arm.com>, "Artur Świgoń" <a.swigon@partner.samsung.com>, "Jacky Bai" <ping.bai@nxp.com>, "Viresh Kumar" <viresh.kumar@linaro.org>, "Michael Turquette" <mturquette@baylibre.com>, "Angus Ainslie" <angus@akkea.ca>, "Alexandre Bailon" <abailon@baylibre.com>, linux-clk@vger.kernel.org, "Abel Vesa" <abel.vesa@nxp.com>, "Saravana Kannan" <saravanak@google.com>, "Krzysztof Kozlowski" <krzk@kernel.org>, "Chanwoo Choi" <cw00.choi@samsung.com>, "Matthias Kaehlcke" <mka@chromium.org>, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, "Martin Kepplinger" <martink@posteo.de>, linux-arm-kernel@lists.infradead.org, "Dong Aisheng" <aisheng.dong@nxp.com>, "Anson Huang" <Anson.Huang@nxp.com>, "Rafael J. Wysocki" <rjw@rjwysocki.net>, kernel@pengutronix.de, "Fabio Estevam" <fabio.estevam@nxp.com>, "Shawn Guo" <shawnguo@kernel.org>, "Georgi Djakov" <georgi.djakov@linaro.org> Subject: [PATCH v4 0/6] PM / devfreq: Add dynamic scaling for imx8m ddr controller Date: Sat, 9 Nov 2019 00:39:50 +0200 [thread overview] Message-ID: <cover.1573252696.git.leonard.crestez@nxp.com> (raw) This adds support for dynamic scaling of the DDR Controller (ddrc) present in imx8m series. Actual frequency switching is implemented inside TF-A, this driver wraps the SMC calls and synchronizes the clk tree. DRAM frequency switching requires clock manipulation but during this operation DRAM itself is briefly inaccessible so this operation is performed a SMC call to by TF-A which runs from a SRAM area. Upon returning to linux the clock tree is updated to correspond to hardware configuration. This is handled via CLK_GET_RATE_NO_CACHE for dividers but muxes are handled manually: the driver will prepare/enable the new parents ahead of switching (so that the expected roots are enabled) and afterwards it will call clk_set_parent to ensure the parents in clock framework are up-to-date. This series is atomically useful and roughly similar to devfreq drivers for tegra and rockchip. Running at lower dram rates saves power but can affect the functionality of other blocks in the chip (display, vpu etc). Support for in-kernel constraints will some separately. Angus/Martin: You previously attempted to test on purism boards, this updated version should work without hacks and has no dependencies. Changes since v3: * Rename to imx8m-ddrc. Similar blocks are present on imx7d and imx8qxp/imx8qm but soc integration is different. * Move dt bindings to /memory-controllers/fsl/ * Fix dt validation issues * Fix imx8mm.dtsi ddrc referencing ddrc_opp_table which is only defined in evk * Move opps to child of ddrc device node * Only add imx_ddrc_get_dev_status in perf patch. * Adjust print messages Link to v3: https://patchwork.kernel.org/cover/11221935/ Leonard Crestez (6): clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocks clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE dt-bindings: memory: Add bindings for imx8m ddr controller PM / devfreq: Add dynamic scaling for imx8m ddr controller PM / devfreq: imx8m-ddrc: Measure bandwidth with perf arm64: dts: imx8m: Add ddr controller nodes .../memory-controllers/fsl/imx8m-ddrc.yaml | 61 ++ arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 18 + arch/arm64/boot/dts/freescale/imx8mm.dtsi | 13 +- .../boot/dts/freescale/imx8mn-ddr4-evk.dts | 18 + arch/arm64/boot/dts/freescale/imx8mn.dtsi | 13 +- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 24 + arch/arm64/boot/dts/freescale/imx8mq.dtsi | 13 +- drivers/clk/imx/clk-imx8mm.c | 13 +- drivers/clk/imx/clk-imx8mn.c | 14 +- drivers/clk/imx/clk-imx8mq.c | 15 +- drivers/clk/imx/clk-pll14xx.c | 7 + drivers/clk/imx/clk.h | 1 + drivers/devfreq/Kconfig | 10 + drivers/devfreq/Makefile | 1 + drivers/devfreq/imx8m-ddrc.c | 569 ++++++++++++++++++ 15 files changed, 777 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml create mode 100644 drivers/devfreq/imx8m-ddrc.c -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2019-11-08 22:40 UTC|newest] Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-08 22:39 Leonard Crestez [this message] 2019-11-08 22:39 ` [PATCH v4 0/6] PM / devfreq: Add dynamic scaling for imx8m ddr controller Leonard Crestez 2019-11-08 22:39 ` [PATCH v4 1/6] clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocks Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2019-11-12 11:18 ` Abel Vesa 2019-11-12 11:18 ` Abel Vesa 2019-11-12 13:43 ` Leonard Crestez 2019-11-12 13:43 ` Leonard Crestez 2019-11-12 15:10 ` Abel Vesa 2019-11-12 15:10 ` Abel Vesa 2019-11-08 22:39 ` [PATCH v4 2/6] clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2019-11-12 11:18 ` Abel Vesa 2019-11-12 11:18 ` Abel Vesa 2019-11-08 22:39 ` [PATCH v4 3/6] dt-bindings: memory: Add bindings for imx8m ddr controller Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2019-11-08 22:39 ` [PATCH v4 4/6] PM / devfreq: Add dynamic scaling " Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2019-11-11 3:23 ` Chanwoo Choi 2019-11-11 3:23 ` Chanwoo Choi 2019-11-11 17:23 ` Leonard Crestez 2019-11-11 17:23 ` Leonard Crestez 2019-11-12 1:00 ` Chanwoo Choi 2019-11-12 1:00 ` Chanwoo Choi 2019-11-12 14:47 ` Leonard Crestez 2019-11-12 14:47 ` Leonard Crestez 2019-11-08 22:39 ` [PATCH v4 5/6] PM / devfreq: imx8m-ddrc: Measure bandwidth with perf Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2019-11-11 5:18 ` Chanwoo Choi 2019-11-11 5:18 ` Chanwoo Choi 2019-11-12 13:17 ` Leonard Crestez 2019-11-12 13:17 ` Leonard Crestez 2019-11-13 1:43 ` Chanwoo Choi 2019-11-13 1:43 ` Chanwoo Choi 2019-11-08 22:39 ` [PATCH v4 6/6] arm64: dts: imx8m: Add ddr controller nodes Leonard Crestez 2019-11-08 22:39 ` Leonard Crestez 2020-06-22 13:58 ` [PATCH v4 0/6] PM / devfreq: Add dynamic scaling for imx8m ddr controller Martin Kepplinger 2020-06-24 6:08 ` Leonard Crestez 2020-06-24 6:08 ` Leonard Crestez 2020-06-25 6:57 ` Martin Kepplinger 2020-06-25 6:57 ` Martin Kepplinger 2020-06-25 14:47 ` Abel Vesa 2020-06-25 14:47 ` Abel Vesa 2020-06-29 6:32 ` Martin Kepplinger 2020-06-29 6:32 ` Martin Kepplinger
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=cover.1573252696.git.leonard.crestez@nxp.com \ --to=leonard.crestez@nxp.com \ --cc=Anson.Huang@nxp.com \ --cc=a.swigon@partner.samsung.com \ --cc=abailon@baylibre.com \ --cc=abel.vesa@nxp.com \ --cc=aisheng.dong@nxp.com \ --cc=angus@akkea.ca \ --cc=cw00.choi@samsung.com \ --cc=devicetree@vger.kernel.org \ --cc=fabio.estevam@nxp.com \ --cc=georgi.djakov@linaro.org \ --cc=kernel@pengutronix.de \ --cc=krzk@kernel.org \ --cc=kyungmin.park@samsung.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-clk@vger.kernel.org \ --cc=linux-imx@nxp.com \ --cc=linux-pm@vger.kernel.org \ --cc=mark.rutland@arm.com \ --cc=martink@posteo.de \ --cc=mka@chromium.org \ --cc=mturquette@baylibre.com \ --cc=myungjoo.ham@samsung.com \ --cc=ping.bai@nxp.com \ --cc=rjw@rjwysocki.net \ --cc=robh+dt@kernel.org \ --cc=saravanak@google.com \ --cc=sboyd@kernel.org \ --cc=shawnguo@kernel.org \ --cc=viresh.kumar@linaro.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.