[Xen-devel] [PATCH RFC] x86emul: unconditionally deliver #UD for LWP insns

[Jan Beulich <JBeulich@suse.com>]

This is to accompany commit  ("x86/svm: Drop support for AMD's
Lightweight Profiling").

Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
With AMD apparently having abandoned XOP encoded insns, another option
would seem to be to simply wire all unrecognized ones into #UD (rather
then returning UNIMPLEMENTED/UNRECOGNIZED).
---
TODO/RFC: Insert commit ID of referenced commit.

--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -10367,6 +10367,16 @@ x86_emulate(
          }
          goto unrecognized_insn;
  
+    case X86EMUL_OPC_XOP(09, 0x12): /* XOP Grp3 */
+        switch ( modrm_reg & 7 )
+        {
+        case 0: /* llwpcb r */
+        case 1: /* slwpcb r */
+            /* LWP is unsupported, so produce #UD unconditionally. */
+            generate_exception(EXC_UD);
+        }
+        goto unrecognized_insn;
+
      case X86EMUL_OPC_XOP(09, 0x82): /* vfrczss xmm/m128,xmm */
      case X86EMUL_OPC_XOP(09, 0x83): /* vfrczsd xmm/m128,xmm */
          generate_exception_if(vex.l, EXC_UD);
@@ -10451,6 +10461,16 @@ x86_emulate(
          break;
      }
  
+    case X86EMUL_OPC_XOP(0a, 0x12): /* XOP Grp4 */
+        switch ( modrm_reg & 7 )
+        {
+        case 0: /* lwpins $imm32,r/m,r */
+        case 1: /* lwpval $imm32,r/m,r */
+            /* LWP is unsupported, so produce #UD unconditionally. */
+            generate_exception(EXC_UD);
+        }
+        goto unrecognized_insn;
+
      default:
      unimplemented_insn:
          rc = X86EMUL_UNIMPLEMENTED;
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