From: "Guido Günther" <agx@sigxcpu.org> To: "Rob Herring" <robh+dt@kernel.org>, "Shawn Guo" <shawnguo@kernel.org>, "Sascha Hauer" <s.hauer@pengutronix.de>, "Pengutronix Kernel Team" <kernel@pengutronix.de>, "Fabio Estevam" <festevam@gmail.com>, "NXP Linux Team" <linux-imx@nxp.com>, "Peng Fan" <peng.fan@nxp.com>, "Dong Aisheng" <aisheng.dong@nxp.com>, "Anson Huang" <Anson.Huang@nxp.com>, "Krzysztof Kozlowski" <krzk@kernel.org>, "Shengjiu Wang" <shengjiu.wang@nxp.com>, "Guido Günther" <agx@sigxcpu.org>, "Philipp Zabel" <p.zabel@pengutronix.de>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: dts: imx8mq: Add clock parents for mipi dphy Date: Fri, 18 Dec 2020 18:50:05 +0100 [thread overview] Message-ID: <dd135fa55084d886bd6daf777d76677f232c53c6.1608313793.git.agx@sigxcpu.org> (raw) This makes sure the clock tree setup for the dphy is not dependent on other components. Without this change bringing up the display can fail like kernel: phy phy-30a00300.dphy.2: Invalid CM/CN/CO values: 165/217/1 kernel: phy phy-30a00300.dphy.2: for hs_clk/ref_clk=451656000/593999998 ~ 165/217 if LCDIF doesn't set up that part of the clock tree first. This was noticed when testing the Librem 5 devkit with defconfig. It doesn't happen when modules are built in. Signed-off-by: Guido Günther <agx@sigxcpu.org> --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index a841a023e8e0..ca0847e8f13c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1016,9 +1016,14 @@ dphy: dphy@30a00300 { reg = <0x30a00300 0x100>; clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; clock-names = "phy_ref"; - assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_CLK_DSI_PHY_REF>, + <&clk IMX8MQ_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_VIDEO_PLL1_OUT>; + assigned-clock-rates = <0>, <0>, <24000000>; #phy-cells = <0>; power-domains = <&pgc_mipi>; status = "disabled"; -- 2.29.2
WARNING: multiple messages have this Message-ID (diff)
From: "Guido Günther" <agx@sigxcpu.org> To: "Rob Herring" <robh+dt@kernel.org>, "Shawn Guo" <shawnguo@kernel.org>, "Sascha Hauer" <s.hauer@pengutronix.de>, "Pengutronix Kernel Team" <kernel@pengutronix.de>, "Fabio Estevam" <festevam@gmail.com>, "NXP Linux Team" <linux-imx@nxp.com>, "Peng Fan" <peng.fan@nxp.com>, "Dong Aisheng" <aisheng.dong@nxp.com>, "Anson Huang" <Anson.Huang@nxp.com>, "Krzysztof Kozlowski" <krzk@kernel.org>, "Shengjiu Wang" <shengjiu.wang@nxp.com>, "Guido Günther" <agx@sigxcpu.org>, "Philipp Zabel" <p.zabel@pengutronix.de>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: dts: imx8mq: Add clock parents for mipi dphy Date: Fri, 18 Dec 2020 18:50:05 +0100 [thread overview] Message-ID: <dd135fa55084d886bd6daf777d76677f232c53c6.1608313793.git.agx@sigxcpu.org> (raw) This makes sure the clock tree setup for the dphy is not dependent on other components. Without this change bringing up the display can fail like kernel: phy phy-30a00300.dphy.2: Invalid CM/CN/CO values: 165/217/1 kernel: phy phy-30a00300.dphy.2: for hs_clk/ref_clk=451656000/593999998 ~ 165/217 if LCDIF doesn't set up that part of the clock tree first. This was noticed when testing the Librem 5 devkit with defconfig. It doesn't happen when modules are built in. Signed-off-by: Guido Günther <agx@sigxcpu.org> --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index a841a023e8e0..ca0847e8f13c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1016,9 +1016,14 @@ dphy: dphy@30a00300 { reg = <0x30a00300 0x100>; clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; clock-names = "phy_ref"; - assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_CLK_DSI_PHY_REF>, + <&clk IMX8MQ_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_VIDEO_PLL1_OUT>; + assigned-clock-rates = <0>, <0>, <24000000>; #phy-cells = <0>; power-domains = <&pgc_mipi>; status = "disabled"; -- 2.29.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2020-12-18 17:50 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-18 17:50 Guido Günther [this message] 2020-12-18 17:50 ` [PATCH] arm64: dts: imx8mq: Add clock parents for mipi dphy Guido Günther 2021-01-10 12:46 ` Shawn Guo 2021-01-10 12:46 ` Shawn Guo 2021-01-10 17:03 ` Guido Günther 2021-01-10 17:03 ` Guido Günther
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