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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com
Subject: [Qemu-devel] [RFC v1 2/5] hw/riscv: Add support for loading a firmware
Date: Tue, 18 Jun 2019 17:38:50 -0700	[thread overview]
Message-ID: <e718da8df07915765217dece609255b6ad196955.1560904640.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1560904640.git.alistair.francis@wdc.com>

Add support for loading a firmware file for the virt machine and the
SiFive U. This can be run with the following command:

    qemu-system-riscv64 -machine virt -bios fw_jump.elf -kernel vmlinux

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c         | 41 +++++++++++++++++++++++++++++++++++++++--
 hw/riscv/sifive_e.c     |  2 +-
 hw/riscv/sifive_u.c     |  6 +++++-
 hw/riscv/spike.c        |  6 +++---
 hw/riscv/virt.c         |  7 ++++++-
 include/hw/riscv/boot.h |  4 +++-
 6 files changed, 57 insertions(+), 9 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 62f94aaf8a..392ca0cb2e 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -23,13 +23,50 @@
 #include "exec/cpu-defs.h"
 #include "hw/loader.h"
 #include "hw/riscv/boot.h"
+#include "hw/boards.h"
 #include "elf.h"
 
-target_ulong riscv_load_kernel(const char *kernel_filename)
+#if defined(TARGET_RISCV32)
+# define KERNEL_BOOT_ADDRESS 0x80400000
+#else
+# define KERNEL_BOOT_ADDRESS 0x80200000
+#endif
+
+static uint64_t kernel_translate(void *opaque, uint64_t addr)
+{
+    MachineState *machine = opaque;
+
+    /*
+     * If the user specified a firmware move the kernel to the offset
+     * start address.
+     */
+    if (machine->firmware) {
+        return (addr & 0x7fffffff) + KERNEL_BOOT_ADDRESS;
+    } else {
+        return addr;
+    }
+}
+
+target_ulong riscv_load_firmware(const char *firmware_filename)
+{
+    uint64_t firmware_entry, firmware_start, firmware_end;
+
+    if (load_elf(firmware_filename, NULL, NULL, NULL,
+                 &firmware_entry, &firmware_start, &firmware_end,
+                 0, EM_RISCV, 1, 0) < 0) {
+        error_report("could not load firmware '%s'", firmware_filename);
+        exit(1);
+    }
+
+    return firmware_entry;
+}
+
+target_ulong riscv_load_kernel(MachineState *machine,
+                               const char *kernel_filename)
 {
     uint64_t kernel_entry, kernel_high;
 
-    if (load_elf(kernel_filename, NULL, NULL, NULL,
+    if (load_elf(kernel_filename, NULL, kernel_translate, machine,
                  &kernel_entry, NULL, &kernel_high,
                  0, EM_RISCV, 1, 0) < 0) {
         error_report("could not load kernel '%s'", kernel_filename);
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 9d58ae362b..3695c686be 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -118,7 +118,7 @@ static void riscv_sifive_e_init(MachineState *machine)
                           memmap[SIFIVE_E_MROM].base, &address_space_memory);
 
     if (machine->kernel_filename) {
-        riscv_load_kernel(machine->kernel_filename);
+        riscv_load_kernel(machine, machine->kernel_filename);
     }
 }
 
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 1b9281bd4a..03a6c64d04 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -266,8 +266,12 @@ static void riscv_sifive_u_init(MachineState *machine)
     /* create device tree */
     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 
+    if (machine->firmware) {
+        riscv_load_firmware(machine->firmware);
+    }
+
     if (machine->kernel_filename) {
-        riscv_load_kernel(machine->kernel_filename);
+        riscv_load_kernel(machine, machine->kernel_filename);
     }
 
     /* reset vector */
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index e68be00a5f..81cef0dcea 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -186,7 +186,7 @@ static void spike_board_init(MachineState *machine)
                                 mask_rom);
 
     if (machine->kernel_filename) {
-        riscv_load_kernel(machine->kernel_filename);
+        riscv_load_kernel(machine, machine->kernel_filename);
     }
 
     /* reset vector */
@@ -274,7 +274,7 @@ static void spike_v1_10_0_board_init(MachineState *machine)
                                 mask_rom);
 
     if (machine->kernel_filename) {
-        riscv_load_kernel(machine->kernel_filename);
+        riscv_load_kernel(machine, machine->kernel_filename);
     }
 
     /* reset vector */
@@ -359,7 +359,7 @@ static void spike_v1_09_1_board_init(MachineState *machine)
                                 mask_rom);
 
     if (machine->kernel_filename) {
-        riscv_load_kernel(machine->kernel_filename);
+        riscv_load_kernel(machine, machine->kernel_filename);
     }
 
     /* reset vector */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 5f8c11471b..d3670b5a7c 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -380,8 +380,13 @@ static void riscv_virt_board_init(MachineState *machine)
     memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
                                 mask_rom);
 
+    if (machine->firmware) {
+        riscv_load_firmware(machine->firmware);
+    }
+
     if (machine->kernel_filename) {
-        uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
+        uint64_t kernel_entry = riscv_load_kernel(machine,
+                                                  machine->kernel_filename);
 
         if (machine->initrd_filename) {
             hwaddr start;
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index f84fd6c2df..6f586939c7 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -20,7 +20,9 @@
 #ifndef RISCV_BOOT_H
 #define RISCV_BOOT_H
 
-target_ulong riscv_load_kernel(const char *kernel_filename);
+target_ulong riscv_load_firmware(const char *firmware_filename);
+target_ulong riscv_load_kernel(MachineState *machine,
+                               const char *kernel_filename);
 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
                          uint64_t kernel_entry, hwaddr *start);
 
-- 
2.22.0



WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@sifive.com, alistair.francis@wdc.com, alistair23@gmail.com
Subject: [Qemu-riscv] [RFC v1 2/5] hw/riscv: Add support for loading a firmware
Date: Tue, 18 Jun 2019 17:38:50 -0700	[thread overview]
Message-ID: <e718da8df07915765217dece609255b6ad196955.1560904640.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1560904640.git.alistair.francis@wdc.com>

Add support for loading a firmware file for the virt machine and the
SiFive U. This can be run with the following command:

    qemu-system-riscv64 -machine virt -bios fw_jump.elf -kernel vmlinux

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c         | 41 +++++++++++++++++++++++++++++++++++++++--
 hw/riscv/sifive_e.c     |  2 +-
 hw/riscv/sifive_u.c     |  6 +++++-
 hw/riscv/spike.c        |  6 +++---
 hw/riscv/virt.c         |  7 ++++++-
 include/hw/riscv/boot.h |  4 +++-
 6 files changed, 57 insertions(+), 9 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 62f94aaf8a..392ca0cb2e 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -23,13 +23,50 @@
 #include "exec/cpu-defs.h"
 #include "hw/loader.h"
 #include "hw/riscv/boot.h"
+#include "hw/boards.h"
 #include "elf.h"
 
-target_ulong riscv_load_kernel(const char *kernel_filename)
+#if defined(TARGET_RISCV32)
+# define KERNEL_BOOT_ADDRESS 0x80400000
+#else
+# define KERNEL_BOOT_ADDRESS 0x80200000
+#endif
+
+static uint64_t kernel_translate(void *opaque, uint64_t addr)
+{
+    MachineState *machine = opaque;
+
+    /*
+     * If the user specified a firmware move the kernel to the offset
+     * start address.
+     */
+    if (machine->firmware) {
+        return (addr & 0x7fffffff) + KERNEL_BOOT_ADDRESS;
+    } else {
+        return addr;
+    }
+}
+
+target_ulong riscv_load_firmware(const char *firmware_filename)
+{
+    uint64_t firmware_entry, firmware_start, firmware_end;
+
+    if (load_elf(firmware_filename, NULL, NULL, NULL,
+                 &firmware_entry, &firmware_start, &firmware_end,
+                 0, EM_RISCV, 1, 0) < 0) {
+        error_report("could not load firmware '%s'", firmware_filename);
+        exit(1);
+    }
+
+    return firmware_entry;
+}
+
+target_ulong riscv_load_kernel(MachineState *machine,
+                               const char *kernel_filename)
 {
     uint64_t kernel_entry, kernel_high;
 
-    if (load_elf(kernel_filename, NULL, NULL, NULL,
+    if (load_elf(kernel_filename, NULL, kernel_translate, machine,
                  &kernel_entry, NULL, &kernel_high,
                  0, EM_RISCV, 1, 0) < 0) {
         error_report("could not load kernel '%s'", kernel_filename);
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 9d58ae362b..3695c686be 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -118,7 +118,7 @@ static void riscv_sifive_e_init(MachineState *machine)
                           memmap[SIFIVE_E_MROM].base, &address_space_memory);
 
     if (machine->kernel_filename) {
-        riscv_load_kernel(machine->kernel_filename);
+        riscv_load_kernel(machine, machine->kernel_filename);
     }
 }
 
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 1b9281bd4a..03a6c64d04 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -266,8 +266,12 @@ static void riscv_sifive_u_init(MachineState *machine)
     /* create device tree */
     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 
+    if (machine->firmware) {
+        riscv_load_firmware(machine->firmware);
+    }
+
     if (machine->kernel_filename) {
-        riscv_load_kernel(machine->kernel_filename);
+        riscv_load_kernel(machine, machine->kernel_filename);
     }
 
     /* reset vector */
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index e68be00a5f..81cef0dcea 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -186,7 +186,7 @@ static void spike_board_init(MachineState *machine)
                                 mask_rom);
 
     if (machine->kernel_filename) {
-        riscv_load_kernel(machine->kernel_filename);
+        riscv_load_kernel(machine, machine->kernel_filename);
     }
 
     /* reset vector */
@@ -274,7 +274,7 @@ static void spike_v1_10_0_board_init(MachineState *machine)
                                 mask_rom);
 
     if (machine->kernel_filename) {
-        riscv_load_kernel(machine->kernel_filename);
+        riscv_load_kernel(machine, machine->kernel_filename);
     }
 
     /* reset vector */
@@ -359,7 +359,7 @@ static void spike_v1_09_1_board_init(MachineState *machine)
                                 mask_rom);
 
     if (machine->kernel_filename) {
-        riscv_load_kernel(machine->kernel_filename);
+        riscv_load_kernel(machine, machine->kernel_filename);
     }
 
     /* reset vector */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 5f8c11471b..d3670b5a7c 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -380,8 +380,13 @@ static void riscv_virt_board_init(MachineState *machine)
     memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
                                 mask_rom);
 
+    if (machine->firmware) {
+        riscv_load_firmware(machine->firmware);
+    }
+
     if (machine->kernel_filename) {
-        uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
+        uint64_t kernel_entry = riscv_load_kernel(machine,
+                                                  machine->kernel_filename);
 
         if (machine->initrd_filename) {
             hwaddr start;
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index f84fd6c2df..6f586939c7 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -20,7 +20,9 @@
 #ifndef RISCV_BOOT_H
 #define RISCV_BOOT_H
 
-target_ulong riscv_load_kernel(const char *kernel_filename);
+target_ulong riscv_load_firmware(const char *firmware_filename);
+target_ulong riscv_load_kernel(MachineState *machine,
+                               const char *kernel_filename);
 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
                          uint64_t kernel_entry, hwaddr *start);
 
-- 
2.22.0



  parent reply	other threads:[~2019-06-19  0:53 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-19  0:38 [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default Alistair Francis
2019-06-19  0:38 ` [Qemu-riscv] " Alistair Francis
2019-06-19  0:38 ` [Qemu-devel] [RFC v1 1/5] hw/riscv: Split out the boot functions Alistair Francis
2019-06-19  0:38   ` [Qemu-riscv] " Alistair Francis
2019-06-19 15:16   ` [Qemu-devel] " Bin Meng
2019-06-19 15:16     ` [Qemu-riscv] " Bin Meng
2019-06-19 18:24     ` Alistair Francis
2019-06-19 18:24       ` [Qemu-riscv] " Alistair Francis
2019-06-19  0:38 ` Alistair Francis [this message]
2019-06-19  0:38   ` [Qemu-riscv] [RFC v1 2/5] hw/riscv: Add support for loading a firmware Alistair Francis
2019-06-19 15:16   ` [Qemu-devel] " Bin Meng
2019-06-19 15:16     ` [Qemu-riscv] " Bin Meng
2019-06-19 15:25     ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens
2019-06-19 15:25       ` [Qemu-riscv] [Qemu-devel] " Jonathan Behrens
2019-06-19 15:30       ` [Qemu-devel] [Qemu-riscv] " Bin Meng
2019-06-19 15:30         ` [Qemu-riscv] [Qemu-devel] " Bin Meng
2019-06-19 21:00         ` [Qemu-devel] [Qemu-riscv] " Alistair Francis
2019-06-19 21:00           ` [Qemu-riscv] [Qemu-devel] " Alistair Francis
2019-06-19  0:38 ` [Qemu-devel] [RFC v1 3/5] hw/riscv: Extend the kernel loading support Alistair Francis
2019-06-19  0:38   ` [Qemu-riscv] " Alistair Francis
2019-06-19 15:16   ` [Qemu-devel] " Bin Meng
2019-06-19 15:16     ` [Qemu-riscv] " Bin Meng
2019-06-19 21:01     ` Alistair Francis
2019-06-19 21:01       ` [Qemu-riscv] " Alistair Francis
2019-06-19 22:06       ` Alistair Francis
2019-06-19 22:06         ` [Qemu-riscv] " Alistair Francis
2019-06-19  0:38 ` [Qemu-devel] [RFC v1 4/5] roms: Add OpenSBI version 0.3 Alistair Francis
2019-06-19  0:38   ` [Qemu-riscv] " Alistair Francis
2019-06-19  5:14   ` [Qemu-devel] " Anup Patel
2019-06-19  5:14     ` Anup Patel
2019-06-19 15:18     ` [Qemu-devel] " Bin Meng
2019-06-19 15:18       ` [Qemu-riscv] [Qemu-devel] " Bin Meng
2019-06-19 18:27       ` [Qemu-devel] [Qemu-riscv] " Alistair Francis
2019-06-19 18:27         ` [Qemu-riscv] [Qemu-devel] " Alistair Francis
2019-06-21  5:41         ` [Qemu-devel] [Qemu-riscv] " Bin Meng
2019-06-21  5:41           ` [Qemu-riscv] [Qemu-devel] " Bin Meng
2019-06-21 22:41           ` [Qemu-devel] [Qemu-riscv] " Alistair Francis
2019-06-21 22:41             ` [Qemu-riscv] [Qemu-devel] " Alistair Francis
2019-06-19  0:38 ` [Qemu-devel] [RFC v1 5/5] hw/riscv: Load OpenSBI as the default firmware Alistair Francis
2019-06-19  0:38   ` [Qemu-riscv] " Alistair Francis
2019-06-19  5:16   ` [Qemu-devel] " Anup Patel
2019-06-19  5:16     ` Anup Patel
2019-06-19 14:26 ` [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default Bin Meng
2019-06-19 14:26   ` [Qemu-riscv] " Bin Meng
2019-06-19 14:29   ` Alistair Francis
2019-06-19 14:29     ` [Qemu-riscv] " Alistair Francis
2019-06-19 14:42     ` Bin Meng
2019-06-19 14:42       ` [Qemu-riscv] " Bin Meng
2019-06-19 18:23       ` Alistair Francis
2019-06-19 18:23         ` [Qemu-riscv] " Alistair Francis
2019-06-20  8:16         ` [Qemu-devel] [Qemu-riscv] " Andrea Bolognani
2019-06-20  8:16           ` [Qemu-riscv] [Qemu-devel] " Andrea Bolognani
2019-06-20 17:59           ` [Qemu-devel] [Qemu-riscv] " Alistair Francis
2019-06-20 17:59             ` [Qemu-riscv] [Qemu-devel] " Alistair Francis
2019-06-20 18:43             ` [Qemu-devel] [Qemu-riscv] " David Abdurachmanov
2019-06-20 18:43               ` [Qemu-riscv] [Qemu-devel] " David Abdurachmanov
2019-06-21 12:35               ` [Qemu-devel] [Qemu-riscv] " Andrea Bolognani
2019-06-21 12:35                 ` [Qemu-riscv] [Qemu-devel] " Andrea Bolognani
2019-06-27 13:49                 ` [Qemu-devel] [Qemu-riscv] " Andrea Bolognani
2019-06-27 13:49                   ` [Qemu-riscv] [Qemu-devel] " Andrea Bolognani

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