From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com
Subject: [PATCH v1 07/36] target/riscv: Add the virtulisation mode
Date: Mon, 9 Dec 2019 10:10:58 -0800 [thread overview]
Message-ID: <ee07ff556701bfdf0173e73d9ac393273a07d2ce.1575914822.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1575914822.git.alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 4 ++++
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 18 ++++++++++++++++++
3 files changed, 25 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bab938103d..a73292cd20 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -117,6 +117,8 @@ struct CPURISCVState {
#ifndef CONFIG_USER_ONLY
target_ulong priv;
+ /* This contains QEMU specific information about the virt state. */
+ target_ulong virt;
target_ulong resetvec;
target_ulong mhartid;
@@ -269,6 +271,8 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
+bool riscv_cpu_virt_enabled(CPURISCVState *env);
+void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index eeaa03c0f8..2cdb0de4fe 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -430,6 +430,9 @@
#define PRV_H 2 /* Reserved */
#define PRV_M 3
+/* Virtulisation Register Fields */
+#define VIRT_ONOFF 1
+
/* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000
#define SATP32_ASID 0x7fc00000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index c201919c54..046f3549cc 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -82,6 +82,24 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
return false;
}
+bool riscv_cpu_virt_enabled(CPURISCVState *env)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return false;
+ }
+
+ return get_field(env->virt, VIRT_ONOFF);
+}
+
+void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return;
+ }
+
+ env->virt = set_field(env->virt, VIRT_ONOFF, enable);
+}
+
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{
CPURISCVState *env = &cpu->env;
--
2.24.0
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com, alistair23@gmail.com
Subject: [PATCH v1 07/36] target/riscv: Add the virtulisation mode
Date: Mon, 9 Dec 2019 10:10:58 -0800 [thread overview]
Message-ID: <ee07ff556701bfdf0173e73d9ac393273a07d2ce.1575914822.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1575914822.git.alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 4 ++++
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 18 ++++++++++++++++++
3 files changed, 25 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bab938103d..a73292cd20 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -117,6 +117,8 @@ struct CPURISCVState {
#ifndef CONFIG_USER_ONLY
target_ulong priv;
+ /* This contains QEMU specific information about the virt state. */
+ target_ulong virt;
target_ulong resetvec;
target_ulong mhartid;
@@ -269,6 +271,8 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
+bool riscv_cpu_virt_enabled(CPURISCVState *env);
+void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index eeaa03c0f8..2cdb0de4fe 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -430,6 +430,9 @@
#define PRV_H 2 /* Reserved */
#define PRV_M 3
+/* Virtulisation Register Fields */
+#define VIRT_ONOFF 1
+
/* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000
#define SATP32_ASID 0x7fc00000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index c201919c54..046f3549cc 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -82,6 +82,24 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
return false;
}
+bool riscv_cpu_virt_enabled(CPURISCVState *env)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return false;
+ }
+
+ return get_field(env->virt, VIRT_ONOFF);
+}
+
+void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return;
+ }
+
+ env->virt = set_field(env->virt, VIRT_ONOFF, enable);
+}
+
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{
CPURISCVState *env = &cpu->env;
--
2.24.0
next prev parent reply other threads:[~2019-12-09 18:25 UTC|newest]
Thread overview: 131+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-09 18:10 [PATCH v1 00/36] Add RISC-V Hypervisor Extension v0.5 Alistair Francis
2019-12-09 18:10 ` Alistair Francis
2019-12-09 18:10 ` [PATCH v1 01/36] target/riscv: Convert MIP CSR to target_ulong Alistair Francis
2019-12-09 18:10 ` Alistair Francis
2019-12-09 18:10 ` [PATCH v1 02/36] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-12-09 18:10 ` Alistair Francis
2019-12-09 18:10 ` [PATCH v1 03/36] target/riscv: Add the Hypervisor extension Alistair Francis
2019-12-09 18:10 ` Alistair Francis
2019-12-09 18:10 ` [PATCH v1 04/36] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis
2019-12-09 18:10 ` Alistair Francis
2019-12-09 18:10 ` [PATCH v1 05/36] target/riscv: Add support for the new execption numbers Alistair Francis
2019-12-09 18:10 ` Alistair Francis
2019-12-09 18:10 ` [PATCH v1 06/36] target/riscv: Rename the H irqs to VS irqs Alistair Francis
2019-12-09 18:10 ` Alistair Francis
2019-12-09 18:10 ` Alistair Francis [this message]
2019-12-09 18:10 ` [PATCH v1 07/36] target/riscv: Add the virtulisation mode Alistair Francis
2019-12-09 18:11 ` [PATCH v1 08/36] target/riscv: Add the force HS exception mode Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 09/36] target/riscv: Fix CSR perm checking for HS mode Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 10/36] target/riscv: Print priv and virt in disas log Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 11/36] target/riscv: Dump Hypervisor registers if enabled Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 12/36] target/riscv: Add Hypervisor CSR access functions Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 13/36] target/riscv: Add Hypervisor virtual CSRs accesses Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 14/36] " Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 15/36] target/riscv: Convert mstatus to pointers Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 16/36] target/riscv: Add virtual register swapping function Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 18/36] target/riscv: Extend the MIE CSR to support virtulisation Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 19/36] target/riscv: Extend the SIP " Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 20/36] target/riscv: Add support for virtual interrupt setting Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 21/36] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 22/36] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 23/36] target/riscv: Add hypvervisor trap support Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2020-01-20 8:34 ` Jiangyifei
2020-01-20 8:34 ` Jiangyifei
2020-01-31 21:25 ` Alistair Francis
2020-01-31 21:25 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 24/36] target/riscv: Add Hypervisor trap return support Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 25/36] target/riscv: Add hfence instructions Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 26/36] target/riscv: Remove the hret instruction Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 27/36] target/riscv: Disable guest FP support based on virtual status Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 28/36] target/riscv: Mark both sstatus and vsstatus as dirty Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 29/36] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:11 ` [PATCH v1 30/36] target/riscv: Allow specifying MMU stage Alistair Francis
2019-12-09 18:11 ` Alistair Francis
2019-12-09 18:12 ` [PATCH v1 31/36] target/riscv: Implement second stage MMU Alistair Francis
2019-12-09 18:12 ` Alistair Francis
2019-12-09 18:12 ` [PATCH v1 32/36] target/riscv: Raise the new execptions when 2nd stage translation fails Alistair Francis
2019-12-09 18:12 ` Alistair Francis
2019-12-09 18:12 ` [PATCH v1 33/36] target/riscv: Set htval and mtval2 on execptions Alistair Francis
2019-12-09 18:12 ` Alistair Francis
2019-12-09 18:12 ` [PATCH v1 34/36] target/riscv: Add support for the 32-bit MSTATUSH CSR Alistair Francis
2019-12-09 18:12 ` Alistair Francis
2019-12-09 18:12 ` [PATCH v1 35/36] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Alistair Francis
2019-12-09 18:12 ` Alistair Francis
2019-12-09 18:12 ` [PATCH v1 36/36] target/riscv: Allow enabling the Hypervisor extension Alistair Francis
2019-12-09 18:12 ` Alistair Francis
2019-12-09 22:55 ` [PATCH v1 00/36] Add RISC-V Hypervisor Extension v0.5 Aleksandar Markovic
2019-12-09 22:55 ` Aleksandar Markovic
2019-12-10 0:03 ` Alistair Francis
2019-12-10 0:03 ` Alistair Francis
2019-12-10 19:05 ` Aleksandar Markovic
2019-12-10 19:05 ` Aleksandar Markovic
2020-01-02 18:18 ` [PATCH v1 01/36] target/riscv: Convert MIP CSR to target_ulong Palmer Dabbelt
2020-01-03 2:08 ` Alistair Francis
2020-01-03 2:08 ` Alistair Francis
2020-01-06 17:51 ` [PATCH v1 02/36] target/riscv: Don't set write permissions on dirty PTEs Palmer Dabbelt
2020-01-07 1:33 ` Alistair Francis
2020-01-07 1:33 ` Alistair Francis
2020-01-07 18:28 ` [PATCH v1 04/36] target/riscv: Add the Hypervisor CSRs to CPUState Palmer Dabbelt
2020-01-07 18:28 ` [PATCH v1 05/36] target/riscv: Add support for the new execption numbers Palmer Dabbelt
2020-01-07 18:28 ` [PATCH v1 06/36] target/riscv: Rename the H irqs to VS irqs Palmer Dabbelt
2020-01-07 18:28 ` [PATCH v1 07/36] target/riscv: Add the virtulisation mode Palmer Dabbelt
2020-01-08 0:06 ` [PATCH v1 09/36] target/riscv: Fix CSR perm checking for HS mode Palmer Dabbelt
2020-01-08 0:07 ` [PATCH v1 12/36] target/riscv: Add Hypervisor CSR access functions Palmer Dabbelt
2020-01-08 0:07 ` [PATCH v1 14/36] target/riscv: Add Hypervisor virtual CSRs accesses Palmer Dabbelt
2020-01-08 1:30 ` [PATCH v1 15/36] target/riscv: Convert mstatus to pointers Palmer Dabbelt
2020-01-21 11:02 ` Alistair Francis
2020-01-21 11:02 ` Alistair Francis
2020-01-21 12:56 ` Jonathan Behrens
2020-01-21 12:56 ` Jonathan Behrens
2020-01-22 0:00 ` Alistair Francis
2020-01-22 0:00 ` Alistair Francis
2020-01-22 22:13 ` Jonathan Behrens
2020-01-22 22:13 ` Jonathan Behrens
2020-01-30 14:48 ` Palmer Dabbelt
2020-01-31 17:31 ` Alistair Francis
2020-01-31 17:31 ` Alistair Francis
2020-02-01 0:09 ` Alistair Francis
2020-02-01 0:09 ` Alistair Francis
2020-01-08 2:07 ` [PATCH v1 16/36] target/riscv: Add virtual register swapping function Palmer Dabbelt
2020-01-08 2:07 ` [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension Palmer Dabbelt
2020-01-21 11:11 ` Alistair Francis
2020-01-21 11:11 ` Alistair Francis
2020-01-21 11:29 ` Anup Patel
2020-01-21 11:29 ` Anup Patel
2020-01-08 20:25 ` [PATCH v1 18/36] target/riscv: Extend the MIE CSR to support virtulisation Palmer Dabbelt
2020-01-09 0:49 ` [PATCH v1 19/36] target/riscv: Extend the SIP " Palmer Dabbelt
2020-01-09 0:49 ` [PATCH v1 26/36] target/riscv: Remove the hret instruction Palmer Dabbelt
2020-01-09 0:49 ` [PATCH v1 20/36] target/riscv: Add support for virtual interrupt setting Palmer Dabbelt
2020-01-09 2:33 ` Richard Henderson
2020-01-09 2:33 ` Richard Henderson
2020-01-10 23:21 ` Palmer Dabbelt
2020-01-09 0:58 ` [PATCH v1 29/36] target/riscv: Respect MPRV and SPRV for floating point ops Palmer Dabbelt
2020-01-09 1:41 ` [PATCH v1 30/36] target/riscv: Allow specifying MMU stage Palmer Dabbelt
2020-01-09 2:01 ` [PATCH v1 31/36] target/riscv: Implement second stage MMU Palmer Dabbelt
2020-01-09 2:29 ` [PATCH v1 32/36] target/riscv: Raise the new execptions when 2nd stage translation fails Palmer Dabbelt
2020-01-09 2:29 ` [PATCH v1 33/36] target/riscv: Set htval and mtval2 on execptions Palmer Dabbelt
2020-01-09 2:29 ` [PATCH v1 34/36] target/riscv: Add support for the 32-bit MSTATUSH CSR Palmer Dabbelt
2020-01-09 2:36 ` [PATCH v1 35/36] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Palmer Dabbelt
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