All of lore.kernel.org
 help / color / mirror / Atom feed
From: Pu Wen <puwen@hygon.cn>
To: xen-devel@lists.xenproject.org
Cc: "Pu Wen" <puwen@hygon.cn>,
	"Roger Pau Monné" <roger.pau@citrix.com>,
	"Wei Liu" <wei.liu2@citrix.com>,
	"Jan Beulich" <jbeulich@suse.com>,
	"Andrew Cooper" <andrew.cooper3@citrix.com>
Subject: [PATCH v5 10/15] x86/pv: Add Hygon Dhyana support to emulate MSRs access
Date: Thu, 4 Apr 2019 21:47:16 +0800	[thread overview]
Message-ID: <f07f2119915eb6717c5978c661acaf84d9d98492.1554382869.git.puwen@hygon.cn> (raw)
In-Reply-To: <cover.1554382869.git.puwen@hygon.cn>

The Hygon Dhyana CPU supports lots of MSRs(such as perf event select and
counter MSRs, hardware configuration MSR, MMIO configuration base address
MSR, MPERF/APERF MSRs) as AMD CPU does, so add Hygon Dhyana support to the
PV emulation infrastructure by using the code path of AMD.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/pv/emul-priv-op.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index 84ce67c..4f73375 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -924,7 +924,9 @@ static int read_msr(unsigned int reg, uint64_t *val,
             /* fall through */
     case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5:
     case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3:
-            if ( vpmu_msr || (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) )
+            if ( vpmu_msr ||
+                (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) ||
+                (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) )
             {
                 if ( vpmu_do_rdmsr(reg, val) )
                     break;
@@ -1006,7 +1008,8 @@ static int write_msr(unsigned int reg, uint64_t val,
     case MSR_K8_PSTATE6:
     case MSR_K8_PSTATE7:
     case MSR_K8_HWCR:
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD )
+        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
+             boot_cpu_data.x86_vendor != X86_VENDOR_HYGON )
             break;
         if ( likely(!is_cpufreq_controller(currd)) ||
              wrmsr_safe(reg, val) == 0 )
@@ -1027,8 +1030,9 @@ static int write_msr(unsigned int reg, uint64_t val,
         break;
 
     case MSR_FAM10H_MMIO_CONF_BASE:
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
-             boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 )
+        if ( (boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
+              boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17) &&
+              boot_cpu_data.x86_vendor != X86_VENDOR_HYGON )
             break;
         if ( !is_hwdom_pinned_vcpu(curr) )
             return X86EMUL_OKAY;
@@ -1067,7 +1071,8 @@ static int write_msr(unsigned int reg, uint64_t val,
     case MSR_IA32_MPERF:
     case MSR_IA32_APERF:
         if ( (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) &&
-             (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) )
+             (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) &&
+             (boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) )
             break;
         if ( likely(!is_cpufreq_controller(currd)) ||
              wrmsr_safe(reg, val) == 0 )
@@ -1099,7 +1104,9 @@ static int write_msr(unsigned int reg, uint64_t val,
             vpmu_msr = true;
     case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5:
     case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3:
-            if ( vpmu_msr || (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) )
+            if ( vpmu_msr ||
+                (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) ||
+                (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) )
             {
                 if ( (vpmu_mode & XENPMU_MODE_ALL) &&
                      !is_hardware_domain(currd) )
-- 
2.7.4


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

  parent reply	other threads:[~2019-04-04 13:50 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-04 13:44 [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Pu Wen
2019-04-04 13:45 ` [PATCH v5 01/15] x86/cpu: Create Hygon Dhyana architecture support file Pu Wen
2019-04-04 14:02   ` Andrew Cooper
2019-04-04 16:39     ` Pu Wen
2019-04-05  7:49       ` Jan Beulich
2019-04-05  7:49         ` [Xen-devel] " Jan Beulich
2019-04-12 16:14         ` Pu Wen
2019-04-12 16:14           ` [Xen-devel] " Pu Wen
2019-04-17 15:03           ` Wei Liu
2019-04-17 15:03             ` [Xen-devel] " Wei Liu
2019-04-18  2:15             ` Pu Wen
2019-04-18  2:15               ` [Xen-devel] " Pu Wen
2019-04-18  9:14               ` Wei Liu
2019-04-18  9:14                 ` [Xen-devel] " Wei Liu
2019-04-04 13:45 ` [PATCH v5 02/15] x86/cpu: Fix common cpuid faulting probing for AMD and Hygon Pu Wen
2019-04-04 13:45 ` [PATCH v5 03/15] x86/cpu/mtrr: Add Hygon Dhyana support to get TOP_MEM2 Pu Wen
2019-04-04 13:46 ` [PATCH v5 04/15] x86/cpu/vpmu: Add Hygon Dhyana and AMD Zen support for vPMU Pu Wen
2019-04-04 13:46 ` [PATCH v5 05/15] x86/cpu/mce: Add Hygon Dhyana support to the MCA infrastructure Pu Wen
2019-04-04 13:46 ` [PATCH v5 06/15] x86/spec_ctrl: Add Hygon Dhyana to the respective mitigation machinery Pu Wen
2019-04-04 13:46 ` [PATCH v5 07/15] x86/apic: Add Hygon Dhyana support Pu Wen
2019-04-04 13:46 ` [PATCH v5 08/15] x86/acpi: " Pu Wen
2019-04-04 13:47 ` [PATCH v5 09/15] x86/iommu: " Pu Wen
2019-04-04 13:47 ` Pu Wen [this message]
2019-04-04 13:47 ` [PATCH v5 11/15] x86/domain: " Pu Wen
2019-04-04 13:47 ` [PATCH v5 12/15] x86/domctl: " Pu Wen
2019-04-04 13:47 ` [PATCH v5 13/15] x86/traps: " Pu Wen
2019-04-04 13:48 ` [PATCH v5 14/15] x86/cpuid: " Pu Wen
2019-04-04 13:48 ` [PATCH v5 15/15] tools/libxc: " Pu Wen
2019-04-04 16:26   ` Wei Liu
2019-04-04 16:40     ` Pu Wen
2019-04-04 13:53 ` [PATCH v5 00/15] Add support for Hygon Dhyana Family 18h processor Julien Grall
2019-04-04 16:47   ` Pu Wen
2019-04-04 17:00     ` Julien Grall
2019-06-06 16:31 ` [Xen-devel] " Andrew Cooper
     [not found] ` <201906070115.x571Fd9j014046@spam1.hygon.cn>
2019-06-07 15:54   ` Pu Wen
2019-06-12 15:10   ` Pu Wen
2019-06-12 15:58     ` Andrew Cooper

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=f07f2119915eb6717c5978c661acaf84d9d98492.1554382869.git.puwen@hygon.cn \
    --to=puwen@hygon.cn \
    --cc=andrew.cooper3@citrix.com \
    --cc=jbeulich@suse.com \
    --cc=roger.pau@citrix.com \
    --cc=wei.liu2@citrix.com \
    --cc=xen-devel@lists.xenproject.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.