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From: shijie001@208suo.com
To: alexander.deucher@amd.com, christian.koenig@amd.com,
	Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch
Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH] drm/radeon: ERROR: open brace '{' following struct go on the same line
Date: Fri, 14 Jul 2023 13:24:32 +0800	[thread overview]
Message-ID: <f4a5c6ecc5679fb82df04eb0a06d04b8@208suo.com> (raw)
In-Reply-To: <tencent_1C2FF78DB4C3129E02E585FC536F6FB07809@qq.com>

Fix seventeen occurrences of the checkpatch.pl error:
ERROR: open brace '{' following struct go on the same line

Signed-off-by: Jie Shi <shijie001@208suo.com>
---
  drivers/gpu/drm/radeon/smu7_discrete.h | 51 +++++++++-----------------
  1 file changed, 17 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/radeon/smu7_discrete.h 
b/drivers/gpu/drm/radeon/smu7_discrete.h
index 0b0b404ff091..1f63cbbd6515 100644
--- a/drivers/gpu/drm/radeon/smu7_discrete.h
+++ b/drivers/gpu/drm/radeon/smu7_discrete.h
@@ -35,8 +35,7 @@
  #define SMU7_NUM_GPU_TES 1
  #define SMU7_NUM_NON_TES 2

-struct SMU7_SoftRegisters
-{
+struct SMU7_SoftRegisters {
      uint32_t        RefClockFrequency;
      uint32_t        PmTimerP;
      uint32_t        FeatureEnables;
@@ -89,8 +88,7 @@ struct SMU7_SoftRegisters

  typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;

-struct SMU7_Discrete_VoltageLevel
-{
+struct SMU7_Discrete_VoltageLevel {
      uint16_t    Voltage;
      uint16_t    StdVoltageHiSidd;
      uint16_t    StdVoltageLoSidd;
@@ -100,8 +98,7 @@ struct SMU7_Discrete_VoltageLevel

  typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel;

-struct SMU7_Discrete_GraphicsLevel
-{
+struct SMU7_Discrete_GraphicsLevel {
      uint32_t    Flags;
      uint32_t    MinVddc;
      uint32_t    MinVddcPhases;
@@ -131,8 +128,7 @@ struct SMU7_Discrete_GraphicsLevel

  typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel;

-struct SMU7_Discrete_ACPILevel
-{
+struct SMU7_Discrete_ACPILevel {
      uint32_t    Flags;
      uint32_t    MinVddc;
      uint32_t    MinVddcPhases;
@@ -153,8 +149,7 @@ struct SMU7_Discrete_ACPILevel

  typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel;

-struct SMU7_Discrete_Ulv
-{
+struct SMU7_Discrete_Ulv {
      uint32_t    CcPwrDynRm;
      uint32_t    CcPwrDynRm1;
      uint16_t    VddcOffset;
@@ -165,8 +160,7 @@ struct SMU7_Discrete_Ulv

  typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv;

-struct SMU7_Discrete_MemoryLevel
-{
+struct SMU7_Discrete_MemoryLevel {
      uint32_t    MinVddc;
      uint32_t    MinVddcPhases;
      uint32_t    MinVddci;
@@ -206,8 +200,7 @@ struct SMU7_Discrete_MemoryLevel

  typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel;

-struct SMU7_Discrete_LinkLevel
-{
+struct SMU7_Discrete_LinkLevel {
      uint8_t     PcieGenSpeed;
      uint8_t     PcieLaneCount;
      uint8_t     EnabledForActivity;
@@ -220,8 +213,7 @@ struct SMU7_Discrete_LinkLevel
  typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel;

-struct SMU7_Discrete_MCArbDramTimingTableEntry
-{
+struct SMU7_Discrete_MCArbDramTimingTableEntry {
      uint32_t McArbDramTiming;
      uint32_t McArbDramTiming2;
      uint8_t  McArbBurstTime;
@@ -230,15 +222,13 @@ struct SMU7_Discrete_MCArbDramTimingTableEntry

  typedef struct SMU7_Discrete_MCArbDramTimingTableEntry 
SMU7_Discrete_MCArbDramTimingTableEntry;

-struct SMU7_Discrete_MCArbDramTimingTable
-{
+struct SMU7_Discrete_MCArbDramTimingTable {
      SMU7_Discrete_MCArbDramTimingTableEntry 
entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
  };

  typedef struct SMU7_Discrete_MCArbDramTimingTable 
SMU7_Discrete_MCArbDramTimingTable;

-struct SMU7_Discrete_UvdLevel
-{
+struct SMU7_Discrete_UvdLevel {
      uint32_t VclkFrequency;
      uint32_t DclkFrequency;
      uint16_t MinVddc;
@@ -250,8 +240,7 @@ struct SMU7_Discrete_UvdLevel

  typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel;

-struct SMU7_Discrete_ExtClkLevel
-{
+struct SMU7_Discrete_ExtClkLevel {
      uint32_t Frequency;
      uint16_t MinVoltage;
      uint8_t  MinPhases;
@@ -260,8 +249,7 @@ struct SMU7_Discrete_ExtClkLevel

  typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel;

-struct SMU7_Discrete_StateInfo
-{
+struct SMU7_Discrete_StateInfo {
      uint32_t SclkFrequency;
      uint32_t MclkFrequency;
      uint32_t VclkFrequency;
@@ -285,8 +273,7 @@ struct SMU7_Discrete_StateInfo
  typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo;

-struct SMU7_Discrete_DpmTable
-{
+struct SMU7_Discrete_DpmTable {
      SMU7_PIDController                  GraphicsPIDController;
      SMU7_PIDController                  MemoryPIDController;
      SMU7_PIDController                  LinkPIDController;
@@ -406,23 +393,20 @@ typedef struct SMU7_Discrete_DpmTable 
SMU7_Discrete_DpmTable;
  #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
  #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT 
SMU7_MAX_LEVELS_MEMORY

-struct SMU7_Discrete_MCRegisterAddress
-{
+struct SMU7_Discrete_MCRegisterAddress {
      uint16_t s0;
      uint16_t s1;
  };

  typedef struct SMU7_Discrete_MCRegisterAddress 
SMU7_Discrete_MCRegisterAddress;

-struct SMU7_Discrete_MCRegisterSet
-{
+struct SMU7_Discrete_MCRegisterSet {
      uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
  };

  typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet;

-struct SMU7_Discrete_MCRegisters
-{
+struct SMU7_Discrete_MCRegisters {
      uint8_t                             last;
      uint8_t                             reserved[3];
      SMU7_Discrete_MCRegisterAddress     
address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
@@ -431,8 +415,7 @@ struct SMU7_Discrete_MCRegisters

  typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters;

-struct SMU7_Discrete_FanTable
-{
+struct SMU7_Discrete_FanTable {
      uint16_t FdoMode;
      int16_t  TempMin;
      int16_t  TempMed;

WARNING: multiple messages have this Message-ID (diff)
From: shijie001@208suo.com
To: alexander.deucher@amd.com, christian.koenig@amd.com,
	Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch
Cc: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH] drm/radeon: ERROR: open brace '{' following struct go on the same line
Date: Fri, 14 Jul 2023 13:24:32 +0800	[thread overview]
Message-ID: <f4a5c6ecc5679fb82df04eb0a06d04b8@208suo.com> (raw)
In-Reply-To: <tencent_1C2FF78DB4C3129E02E585FC536F6FB07809@qq.com>

Fix seventeen occurrences of the checkpatch.pl error:
ERROR: open brace '{' following struct go on the same line

Signed-off-by: Jie Shi <shijie001@208suo.com>
---
  drivers/gpu/drm/radeon/smu7_discrete.h | 51 +++++++++-----------------
  1 file changed, 17 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/radeon/smu7_discrete.h 
b/drivers/gpu/drm/radeon/smu7_discrete.h
index 0b0b404ff091..1f63cbbd6515 100644
--- a/drivers/gpu/drm/radeon/smu7_discrete.h
+++ b/drivers/gpu/drm/radeon/smu7_discrete.h
@@ -35,8 +35,7 @@
  #define SMU7_NUM_GPU_TES 1
  #define SMU7_NUM_NON_TES 2

-struct SMU7_SoftRegisters
-{
+struct SMU7_SoftRegisters {
      uint32_t        RefClockFrequency;
      uint32_t        PmTimerP;
      uint32_t        FeatureEnables;
@@ -89,8 +88,7 @@ struct SMU7_SoftRegisters

  typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;

-struct SMU7_Discrete_VoltageLevel
-{
+struct SMU7_Discrete_VoltageLevel {
      uint16_t    Voltage;
      uint16_t    StdVoltageHiSidd;
      uint16_t    StdVoltageLoSidd;
@@ -100,8 +98,7 @@ struct SMU7_Discrete_VoltageLevel

  typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel;

-struct SMU7_Discrete_GraphicsLevel
-{
+struct SMU7_Discrete_GraphicsLevel {
      uint32_t    Flags;
      uint32_t    MinVddc;
      uint32_t    MinVddcPhases;
@@ -131,8 +128,7 @@ struct SMU7_Discrete_GraphicsLevel

  typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel;

-struct SMU7_Discrete_ACPILevel
-{
+struct SMU7_Discrete_ACPILevel {
      uint32_t    Flags;
      uint32_t    MinVddc;
      uint32_t    MinVddcPhases;
@@ -153,8 +149,7 @@ struct SMU7_Discrete_ACPILevel

  typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel;

-struct SMU7_Discrete_Ulv
-{
+struct SMU7_Discrete_Ulv {
      uint32_t    CcPwrDynRm;
      uint32_t    CcPwrDynRm1;
      uint16_t    VddcOffset;
@@ -165,8 +160,7 @@ struct SMU7_Discrete_Ulv

  typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv;

-struct SMU7_Discrete_MemoryLevel
-{
+struct SMU7_Discrete_MemoryLevel {
      uint32_t    MinVddc;
      uint32_t    MinVddcPhases;
      uint32_t    MinVddci;
@@ -206,8 +200,7 @@ struct SMU7_Discrete_MemoryLevel

  typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel;

-struct SMU7_Discrete_LinkLevel
-{
+struct SMU7_Discrete_LinkLevel {
      uint8_t     PcieGenSpeed;
      uint8_t     PcieLaneCount;
      uint8_t     EnabledForActivity;
@@ -220,8 +213,7 @@ struct SMU7_Discrete_LinkLevel
  typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel;

-struct SMU7_Discrete_MCArbDramTimingTableEntry
-{
+struct SMU7_Discrete_MCArbDramTimingTableEntry {
      uint32_t McArbDramTiming;
      uint32_t McArbDramTiming2;
      uint8_t  McArbBurstTime;
@@ -230,15 +222,13 @@ struct SMU7_Discrete_MCArbDramTimingTableEntry

  typedef struct SMU7_Discrete_MCArbDramTimingTableEntry 
SMU7_Discrete_MCArbDramTimingTableEntry;

-struct SMU7_Discrete_MCArbDramTimingTable
-{
+struct SMU7_Discrete_MCArbDramTimingTable {
      SMU7_Discrete_MCArbDramTimingTableEntry 
entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
  };

  typedef struct SMU7_Discrete_MCArbDramTimingTable 
SMU7_Discrete_MCArbDramTimingTable;

-struct SMU7_Discrete_UvdLevel
-{
+struct SMU7_Discrete_UvdLevel {
      uint32_t VclkFrequency;
      uint32_t DclkFrequency;
      uint16_t MinVddc;
@@ -250,8 +240,7 @@ struct SMU7_Discrete_UvdLevel

  typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel;

-struct SMU7_Discrete_ExtClkLevel
-{
+struct SMU7_Discrete_ExtClkLevel {
      uint32_t Frequency;
      uint16_t MinVoltage;
      uint8_t  MinPhases;
@@ -260,8 +249,7 @@ struct SMU7_Discrete_ExtClkLevel

  typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel;

-struct SMU7_Discrete_StateInfo
-{
+struct SMU7_Discrete_StateInfo {
      uint32_t SclkFrequency;
      uint32_t MclkFrequency;
      uint32_t VclkFrequency;
@@ -285,8 +273,7 @@ struct SMU7_Discrete_StateInfo
  typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo;

-struct SMU7_Discrete_DpmTable
-{
+struct SMU7_Discrete_DpmTable {
      SMU7_PIDController                  GraphicsPIDController;
      SMU7_PIDController                  MemoryPIDController;
      SMU7_PIDController                  LinkPIDController;
@@ -406,23 +393,20 @@ typedef struct SMU7_Discrete_DpmTable 
SMU7_Discrete_DpmTable;
  #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
  #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT 
SMU7_MAX_LEVELS_MEMORY

-struct SMU7_Discrete_MCRegisterAddress
-{
+struct SMU7_Discrete_MCRegisterAddress {
      uint16_t s0;
      uint16_t s1;
  };

  typedef struct SMU7_Discrete_MCRegisterAddress 
SMU7_Discrete_MCRegisterAddress;

-struct SMU7_Discrete_MCRegisterSet
-{
+struct SMU7_Discrete_MCRegisterSet {
      uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
  };

  typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet;

-struct SMU7_Discrete_MCRegisters
-{
+struct SMU7_Discrete_MCRegisters {
      uint8_t                             last;
      uint8_t                             reserved[3];
      SMU7_Discrete_MCRegisterAddress     
address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
@@ -431,8 +415,7 @@ struct SMU7_Discrete_MCRegisters

  typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters;

-struct SMU7_Discrete_FanTable
-{
+struct SMU7_Discrete_FanTable {
      uint16_t FdoMode;
      int16_t  TempMin;
      int16_t  TempMed;

       reply	other threads:[~2023-07-14  5:24 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <tencent_1C2FF78DB4C3129E02E585FC536F6FB07809@qq.com>
2023-07-14  5:24 ` shijie001 [this message]
2023-07-14  5:24   ` [PATCH] drm/radeon: ERROR: open brace '{' following struct go on the same line shijie001

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