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From: Yunfeng Ye <yeyunfeng@huawei.com>
To: <catalin.marinas@arm.com>, <will@kernel.org>,
	<wangkefeng.wang@huawei.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Cc: <wuxu.wu@huawei.com>, Hewenliang <hewenliang4@huawei.com>
Subject: [PATCH v3 2/2] arm64: mm: Use asid feature macro for cheanup
Date: Thu, 9 Dec 2021 09:46:03 +0800	[thread overview]
Message-ID: <f71c75d3-735e-b32a-8414-b3e513c77240@huawei.com> (raw)
In-Reply-To: <c31516eb-6d15-94e0-421c-305fc010ea79@huawei.com>

The commit 95b54c3e4c92 ("KVM: arm64: Add feature register flag
definitions") introduce the ID_AA64MMFR0_ASID_8 and ID_AA64MMFR0_ASID_16
macros.

We can use these macros for cheanup in get_cpu_asid_bits().

No functional change.

Signed-off-by: Yunfeng Ye <yeyunfeng@huawei.com>
Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
v2 -> v3:
 - Delete the first blank line
 - Add "Signed-off-by" and "Reviewed-by"

v1 -> v2:
 - Split the patch

 arch/arm64/mm/context.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index bbc2708fe928..b8b4cf0bcf39 100644
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -50,10 +50,10 @@ static u32 get_cpu_asid_bits(void)
 		pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n",
 					smp_processor_id(),  fld);
 		fallthrough;
-	case 0:
+	case ID_AA64MMFR0_ASID_8:
 		asid = 8;
 		break;
-	case 2:
+	case ID_AA64MMFR0_ASID_16:
 		asid = 16;
 	}

-- 
2.27.0

WARNING: multiple messages have this Message-ID (diff)
From: Yunfeng Ye <yeyunfeng@huawei.com>
To: <catalin.marinas@arm.com>, <will@kernel.org>,
	<wangkefeng.wang@huawei.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Cc: <wuxu.wu@huawei.com>, Hewenliang <hewenliang4@huawei.com>
Subject: [PATCH v3 2/2] arm64: mm: Use asid feature macro for cheanup
Date: Thu, 9 Dec 2021 09:46:03 +0800	[thread overview]
Message-ID: <f71c75d3-735e-b32a-8414-b3e513c77240@huawei.com> (raw)
In-Reply-To: <c31516eb-6d15-94e0-421c-305fc010ea79@huawei.com>

The commit 95b54c3e4c92 ("KVM: arm64: Add feature register flag
definitions") introduce the ID_AA64MMFR0_ASID_8 and ID_AA64MMFR0_ASID_16
macros.

We can use these macros for cheanup in get_cpu_asid_bits().

No functional change.

Signed-off-by: Yunfeng Ye <yeyunfeng@huawei.com>
Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
v2 -> v3:
 - Delete the first blank line
 - Add "Signed-off-by" and "Reviewed-by"

v1 -> v2:
 - Split the patch

 arch/arm64/mm/context.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index bbc2708fe928..b8b4cf0bcf39 100644
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -50,10 +50,10 @@ static u32 get_cpu_asid_bits(void)
 		pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n",
 					smp_processor_id(),  fld);
 		fallthrough;
-	case 0:
+	case ID_AA64MMFR0_ASID_8:
 		asid = 8;
 		break;
-	case 2:
+	case ID_AA64MMFR0_ASID_16:
 		asid = 16;
 	}

-- 
2.27.0

_______________________________________________
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  reply	other threads:[~2021-12-09  1:46 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-09  1:42 [PATCH v3 1/2] arm64: mm: Rename asid2idx() to ctxid2asid() Yunfeng Ye
2021-12-09  1:42 ` Yunfeng Ye
2021-12-09  1:46 ` Yunfeng Ye [this message]
2021-12-09  1:46   ` [PATCH v3 2/2] arm64: mm: Use asid feature macro for cheanup Yunfeng Ye
2021-12-10 18:40 ` [PATCH v3 1/2] arm64: mm: Rename asid2idx() to ctxid2asid() Catalin Marinas
2021-12-10 18:40   ` Catalin Marinas

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