From: Stafford Horne <shorne@gmail.com> To: qemu-devel@nongnu.org Cc: openrisc@lists.librecores.org, Stafford Horne <shorne@gmail.com> Subject: [Qemu-devel] [PATCH 3/7] target/openrisc: add numcores and coreid support Date: Mon, 17 Apr 2017 08:23:52 +0900 [thread overview] Message-ID: <f8e2371c7a99cc6694b65d5be4f6c265dceae66a.1492384862.git.shorne@gmail.com> (raw) In-Reply-To: <cover.1492384862.git.shorne@gmail.com> In-Reply-To: <cover.1492384862.git.shorne@gmail.com> These are used to identify the processor in SMP system. Their definition has been defined in verilog cores but it not yet part of the spec but it will be soon. The proposal for this is available: https://openrisc.io/proposals/core-identifier-and-number-of-cores Signed-off-by: Stafford Horne <shorne@gmail.com> --- target/openrisc/sys_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 2eaff87..bd5051b 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -227,6 +227,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 64): /* ESR */ return env->esr; + case TO_SPR(0, 128): /* COREID */ + return 0; + + case TO_SPR(0, 129): /* NUMCORES */ + return 1; + case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); return env->tlb->dtlb[0][idx].mr; -- 2.9.3
WARNING: multiple messages have this Message-ID (diff)
From: Stafford Horne <shorne@gmail.com> To: openrisc@lists.librecores.org Subject: [OpenRISC] [PATCH 3/7] target/openrisc: add numcores and coreid support Date: Mon, 17 Apr 2017 08:23:52 +0900 [thread overview] Message-ID: <f8e2371c7a99cc6694b65d5be4f6c265dceae66a.1492384862.git.shorne@gmail.com> (raw) In-Reply-To: <cover.1492384862.git.shorne@gmail.com> These are used to identify the processor in SMP system. Their definition has been defined in verilog cores but it not yet part of the spec but it will be soon. The proposal for this is available: https://openrisc.io/proposals/core-identifier-and-number-of-cores Signed-off-by: Stafford Horne <shorne@gmail.com> --- target/openrisc/sys_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 2eaff87..bd5051b 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -227,6 +227,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 64): /* ESR */ return env->esr; + case TO_SPR(0, 128): /* COREID */ + return 0; + + case TO_SPR(0, 129): /* NUMCORES */ + return 1; + case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); return env->tlb->dtlb[0][idx].mr; -- 2.9.3
next prev parent reply other threads:[~2017-04-16 23:24 UTC|newest] Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-04-16 23:23 [Qemu-devel] [PATCH 0/7] Openrisc misc features / fixes Stafford Horne 2017-04-16 23:23 ` [OpenRISC] " Stafford Horne 2017-04-16 23:23 ` [Qemu-devel] [PATCH 1/7] target/openrisc: Fixes for memory debugging Stafford Horne 2017-04-16 23:23 ` [OpenRISC] " Stafford Horne 2017-04-18 7:47 ` [Qemu-devel] " Richard Henderson 2017-04-18 7:47 ` [OpenRISC] " Richard Henderson 2017-04-18 14:18 ` Stafford Horne 2017-04-18 14:18 ` [OpenRISC] " Stafford Horne 2017-04-18 15:00 ` Richard Henderson 2017-04-18 15:00 ` [OpenRISC] " Richard Henderson 2017-04-19 20:06 ` Stafford Horne 2017-04-19 20:06 ` [OpenRISC] " Stafford Horne 2017-04-16 23:23 ` [Qemu-devel] [PATCH 2/7] target/openrisc: add shutdown logic Stafford Horne 2017-04-16 23:23 ` [OpenRISC] " Stafford Horne 2017-04-18 7:52 ` [Qemu-devel] " Richard Henderson 2017-04-18 7:52 ` [OpenRISC] " Richard Henderson 2017-04-18 14:20 ` Stafford Horne 2017-04-18 14:20 ` [OpenRISC] " Stafford Horne 2017-04-22 10:09 ` Stafford Horne 2017-04-22 10:09 ` [OpenRISC] " Stafford Horne 2017-04-22 15:25 ` Richard Henderson 2017-04-22 15:25 ` [OpenRISC] " Richard Henderson 2017-04-23 21:28 ` [OpenRISC] [PATCH PMR] target/openrisc: Support non-busy idle state using PMR SPR Stafford Horne 2017-04-23 21:54 ` [Qemu-devel] [PATCH RFC] " Stafford Horne 2017-04-23 21:54 ` [OpenRISC] " Stafford Horne 2017-04-25 10:11 ` [Qemu-devel] " Richard Henderson 2017-04-25 10:11 ` [OpenRISC] " Richard Henderson 2017-04-25 14:10 ` [Qemu-devel] [PATCH RFC v2] " Stafford Horne 2017-04-25 14:10 ` [OpenRISC] " Stafford Horne 2017-04-25 14:18 ` [Qemu-devel] [PATCH RFC] " Stafford Horne 2017-04-25 14:18 ` [OpenRISC] " Stafford Horne 2017-04-25 14:51 ` [Qemu-devel] " Richard Henderson 2017-04-25 14:51 ` [OpenRISC] " Richard Henderson 2022-04-27 17:44 ` [Qemu-devel] [PATCH 2/7] target/openrisc: add shutdown logic Jason A. Donenfeld 2022-04-27 17:44 ` [OpenRISC] " Jason A. Donenfeld 2022-04-27 18:47 ` Peter Maydell 2022-04-27 18:47 ` [OpenRISC] " Peter Maydell 2022-04-27 21:48 ` Stafford Horne 2022-04-27 21:48 ` [OpenRISC] " Stafford Horne 2022-04-28 0:04 ` Jason A. Donenfeld 2022-04-28 0:04 ` [OpenRISC] " Jason A. Donenfeld 2022-04-28 11:16 ` Jason A. Donenfeld 2022-04-28 11:16 ` [OpenRISC] " Jason A. Donenfeld 2022-04-28 11:47 ` Stafford Horne 2022-04-28 11:47 ` [OpenRISC] " Stafford Horne 2022-04-28 9:19 ` Peter Maydell 2022-04-28 9:19 ` [OpenRISC] " Peter Maydell 2017-04-16 23:23 ` Stafford Horne [this message] 2017-04-16 23:23 ` [OpenRISC] [PATCH 3/7] target/openrisc: add numcores and coreid support Stafford Horne 2017-04-18 8:01 ` [Qemu-devel] " Richard Henderson 2017-04-18 8:01 ` [OpenRISC] " Richard Henderson 2017-04-16 23:23 ` [Qemu-devel] [PATCH 4/7] target/openrisc: implement shadow registers Stafford Horne 2017-04-16 23:23 ` [OpenRISC] " Stafford Horne 2017-04-18 8:11 ` [Qemu-devel] " Richard Henderson 2017-04-18 8:11 ` [OpenRISC] " Richard Henderson 2017-04-18 14:26 ` Stafford Horne 2017-04-18 14:26 ` [OpenRISC] " Stafford Horne 2017-04-16 23:23 ` [Qemu-devel] [PATCH 5/7] migration: Add VMSTATE_UINTTL_2DARRAY() Stafford Horne 2017-04-16 23:23 ` [OpenRISC] " Stafford Horne 2017-04-16 23:23 ` [Qemu-devel] [PATCH 6/7] migration: Add VMSTATE_STRUCT_2DARRAY() Stafford Horne 2017-04-16 23:23 ` [OpenRISC] " Stafford Horne 2017-04-16 23:23 ` [Qemu-devel] [PATCH 7/7] target/openrisc: Implement full vmstate serialization Stafford Horne 2017-04-16 23:23 ` [OpenRISC] " Stafford Horne 2017-04-18 8:14 ` [Qemu-devel] " Richard Henderson 2017-04-18 8:14 ` [OpenRISC] " Richard Henderson 2017-04-18 14:27 ` Stafford Horne 2017-04-18 14:27 ` [OpenRISC] " Stafford Horne 2017-04-16 23:33 ` [Qemu-devel] [PATCH 0/7] Openrisc misc features / fixes no-reply 2017-04-16 23:33 ` [OpenRISC] " no-reply
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