From: Simon Horman <horms+renesas@verge.net.au>
To: linux-renesas-soc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
Magnus Damm <magnus.damm@gmail.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Simon Horman <horms+renesas@verge.net.au>
Subject: [PATCH 6/9] arm64: dts: r8a7796: Add SYSC PM Domains
Date: Thu, 30 Jun 2016 16:15:04 +0200 [thread overview]
Message-ID: <fbb099e4ec724e320bec0126a47dbb683ca3cab0.1467291676.git.horms+renesas@verge.net.au> (raw)
In-Reply-To: <cover.1467291676.git.horms+renesas@verge.net.au>
From: Geert Uytterhoeven <geert+renesas@glider.be>
Add a device node for the System Controller.
Hook up the Cortex-A57 CPU core and L2 cache/SCU to their respective PM
Domains.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 178debf68318..85f0843ddd87 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a7796-sysc.h>
/ {
compatible = "renesas,r8a7796";
@@ -30,6 +31,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
device_type = "cpu";
+ power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
};
@@ -37,6 +39,7 @@
L2_CA57: cache-controller@0 {
compatible = "cache";
reg = <0>;
+ power-domains = <&sysc R8A7796_PD_CA57_SCU>;
cache-unified;
cache-level = <2>;
};
@@ -104,6 +107,12 @@
#power-domain-cells = <0>;
};
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7796-sysc";
+ reg = <0 0xe6180000 0 0x0400>;
+ #power-domain-cells = <1>;
+ };
+
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a7796",
"renesas,rcar-gen3-scif", "renesas,scif";
--
2.7.0.rc3.207.g0ac5344
WARNING: multiple messages have this Message-ID (diff)
From: horms+renesas@verge.net.au (Simon Horman)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 6/9] arm64: dts: r8a7796: Add SYSC PM Domains
Date: Thu, 30 Jun 2016 16:15:04 +0200 [thread overview]
Message-ID: <fbb099e4ec724e320bec0126a47dbb683ca3cab0.1467291676.git.horms+renesas@verge.net.au> (raw)
In-Reply-To: <cover.1467291676.git.horms+renesas@verge.net.au>
From: Geert Uytterhoeven <geert+renesas@glider.be>
Add a device node for the System Controller.
Hook up the Cortex-A57 CPU core and L2 cache/SCU to their respective PM
Domains.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 178debf68318..85f0843ddd87 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a7796-sysc.h>
/ {
compatible = "renesas,r8a7796";
@@ -30,6 +31,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
device_type = "cpu";
+ power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
};
@@ -37,6 +39,7 @@
L2_CA57: cache-controller at 0 {
compatible = "cache";
reg = <0>;
+ power-domains = <&sysc R8A7796_PD_CA57_SCU>;
cache-unified;
cache-level = <2>;
};
@@ -104,6 +107,12 @@
#power-domain-cells = <0>;
};
+ sysc: system-controller at e6180000 {
+ compatible = "renesas,r8a7796-sysc";
+ reg = <0 0xe6180000 0 0x0400>;
+ #power-domain-cells = <1>;
+ };
+
scif2: serial at e6e88000 {
compatible = "renesas,scif-r8a7796",
"renesas,rcar-gen3-scif", "renesas,scif";
--
2.7.0.rc3.207.g0ac5344
next prev parent reply other threads:[~2016-06-30 14:15 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-30 14:15 [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v4.8 Simon Horman
2016-06-30 14:15 ` Simon Horman
2016-06-30 14:14 ` [PATCH 1/9] arm64: dts: r8a7795: Add missing blank lines between cpu nodes Simon Horman
2016-06-30 14:14 ` Simon Horman
2016-06-30 14:15 ` [PATCH 2/9] arm64: dts: r8a7795: Add CAN FD support Simon Horman
2016-06-30 14:15 ` Simon Horman
2016-06-30 14:15 ` [PATCH 3/9] clk: renesas: Add r8a7796 CPG Core Clock Definitions Simon Horman
2016-06-30 14:15 ` Simon Horman
2016-06-30 14:15 ` [PATCH 4/9] arm64: dts: r8a7796: Add Renesas R8A7796 SoC support Simon Horman
2016-06-30 14:15 ` Simon Horman
2016-06-30 14:15 ` [PATCH 5/9] arm64: dts: salvator-x: add Salvator-X board on R8A7796 SoC Simon Horman
2016-06-30 14:15 ` Simon Horman
2016-06-30 14:15 ` Simon Horman [this message]
2016-06-30 14:15 ` [PATCH 6/9] arm64: dts: r8a7796: Add SYSC PM Domains Simon Horman
2016-06-30 14:15 ` [PATCH 7/9] arm64: dts: r8a7796: Use SYSC "always-on" PM Domain Simon Horman
2016-06-30 14:15 ` Simon Horman
2016-06-30 14:15 ` [PATCH 8/9] arm64: dts: r8a7796: Add RWDT node Simon Horman
2016-06-30 14:15 ` Simon Horman
2016-06-30 14:15 ` [PATCH 9/9] arm64: dts: r8a7796/salvator-x: Enable watchdog timer Simon Horman
2016-06-30 14:15 ` Simon Horman
2016-07-07 5:06 ` [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v4.8 Olof Johansson
2016-07-07 5:06 ` Olof Johansson
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