From: Baruch Siach <baruch@tkos.co.il>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Baruch Siach <baruch.siach@siklu.com>,
Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>,
Kathiravan T <kathirav@codeaurora.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Robert Marko <robert.marko@sartura.hr>,
linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-tegra@vger.kernel.org
Subject: [PATCH v4 1/3] arm64: dts: qcom: ipq6018: add pcie max-link-speed
Date: Mon, 27 Dec 2021 08:46:03 +0200 [thread overview]
Message-ID: <fcf41277cf8529437374a5c10b2b1fcad30cd7c2.1640587131.git.baruch@tkos.co.il> (raw)
In-Reply-To: <cover.1640587131.git.baruch@tkos.co.il>
From: Baruch Siach <baruch.siach@siklu.com>
Add the generic 'max-link-speed' property to describe the IPQ6018 PCIe
link generation limit. This allows the generic dwc code to configure the
link speed correctly.
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index a717fc17523d..665ee301b85d 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -438,6 +438,7 @@ pcie0: pci@20000000 {
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
+ max-link-speed = <3>;
#address-cells = <3>;
#size-cells = <2>;
--
2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Baruch Siach <baruch@tkos.co.il>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Baruch Siach <baruch.siach@siklu.com>,
Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>,
Kathiravan T <kathirav@codeaurora.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Robert Marko <robert.marko@sartura.hr>,
linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-tegra@vger.kernel.org
Subject: [PATCH v4 1/3] arm64: dts: qcom: ipq6018: add pcie max-link-speed
Date: Mon, 27 Dec 2021 08:46:03 +0200 [thread overview]
Message-ID: <fcf41277cf8529437374a5c10b2b1fcad30cd7c2.1640587131.git.baruch@tkos.co.il> (raw)
In-Reply-To: <cover.1640587131.git.baruch@tkos.co.il>
From: Baruch Siach <baruch.siach@siklu.com>
Add the generic 'max-link-speed' property to describe the IPQ6018 PCIe
link generation limit. This allows the generic dwc code to configure the
link speed correctly.
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index a717fc17523d..665ee301b85d 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -438,6 +438,7 @@ pcie0: pci@20000000 {
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
+ max-link-speed = <3>;
#address-cells = <3>;
#size-cells = <2>;
--
2.34.1
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next prev parent reply other threads:[~2021-12-27 6:46 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-27 6:46 [PATCH v4 0/3] PCI: IPQ6018 PCIe controller support Baruch Siach
2021-12-27 6:46 ` Baruch Siach
2021-12-27 6:46 ` Baruch Siach [this message]
2021-12-27 6:46 ` [PATCH v4 1/3] arm64: dts: qcom: ipq6018: add pcie max-link-speed Baruch Siach
2022-02-01 5:19 ` (subset) " Bjorn Andersson
2022-02-01 5:19 ` Bjorn Andersson
2021-12-27 6:46 ` [PATCH v4 2/3] PCI: dwc: tegra: move GEN3_RELATED DBI register to common header Baruch Siach
2021-12-27 6:46 ` Baruch Siach
2021-12-27 6:46 ` [PATCH v4 3/3] PCI: qcom: add support for IPQ60xx PCIe controller Baruch Siach
2021-12-27 6:46 ` Baruch Siach
2022-01-06 14:45 ` Lorenzo Pieralisi
2022-01-06 14:45 ` Lorenzo Pieralisi
2022-01-06 18:05 ` Baruch Siach
2022-01-06 18:05 ` Baruch Siach
2022-01-06 23:20 ` Bjorn Andersson
2022-01-06 23:20 ` Bjorn Andersson
2022-01-06 23:54 ` Pali Rohár
2022-01-06 23:54 ` Pali Rohár
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