From: "Paul E. McKenney" <paulmck@kernel.org>
To: w@1wt.eu
Cc: rcu@vger.kernel.org
Subject: Making races happen more often
Date: Sat, 25 Sep 2021 20:51:03 -0700 [thread overview]
Message-ID: <20210926035103.GA1953486@paulmck-ThinkPad-P17-Gen-1> (raw)
Hello, Willy!
Continuing from linkedin:
> Maybe this doesn't work as well as expected because of the common L3 cache
> that runs at a single frequency and that imposes discrete timings. Also,
> I noticed that on modern CPUs, cache lines tend to "stick" at least a few
> cycles once they're in a cache, which helps the corresponding CPU chain
> a few atomic ops undisturbed. For example on a 8-core Ryzen I'm seeing a
> minimum of 8ns between two threads of the same core (L1 probably split in
> two halves), 25ns between two L2 and 60ns between the two halves (CCX)
> of the L3. This certainly makes it much harder to trigger concurrency
> issues. Well let's continue by e-mail, it's a real pain to type in this
> awful interface.
Indeed, I get best (worst?) results from memory latency on multi-socket
systems. And these results were not subtle:
https://paulmck.livejournal.com/62071.html
All that aside, any advice on portably and usefully getting 2-3x clock
frequency differences into testing would be quite welcome.
Thanx, Paul
next reply other threads:[~2021-09-26 3:51 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-26 3:51 Paul E. McKenney [this message]
2021-09-26 4:41 ` Making races happen more often Willy Tarreau
2021-09-27 3:25 ` Paul E. McKenney
2021-09-27 6:49 ` Willy Tarreau
2021-09-28 4:01 ` Paul E. McKenney
2021-09-29 19:59 ` Willy Tarreau
2021-09-30 18:46 ` Paul E. McKenney
2021-09-30 21:12 ` Willy Tarreau
2021-10-07 0:44 ` Paul E. McKenney
2021-10-07 17:53 ` Willy Tarreau
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