From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EABCC433EF for ; Sat, 30 Oct 2021 00:02:16 +0000 (UTC) Received: by mail.kernel.org (Postfix) id F143261037; Sat, 30 Oct 2021 00:02:15 +0000 (UTC) Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) (using TLSv1.2 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ADA7760720; Sat, 30 Oct 2021 00:02:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org ADA7760720 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=tempfail smtp.mailfrom=quicinc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1635552135; x=1667088135; h=from:to:cc:subject:date:message-id:mime-version; bh=jl0Mely6L4weR8bSYe4b936KJqFueiKv+9RIem6A3xw=; b=nMR07nTTVKGqXCadrqJlRI2wLyBcpyoBC793BEjEYcPPp1N01+fzV2hL 7lXNXNkw3/OVulDJNnyhMNHV4tbVMWrnW7Qe1stBzGZWhySjSS+LfZ4+A mD+qgwH37Cw+mF1g0DWOVSetlLzM+NdFZqebHUMOnxYV7BCqiUxt0Krku U=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 29 Oct 2021 17:02:15 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2021 17:02:14 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Fri, 29 Oct 2021 17:02:14 -0700 Received: from hu-vamslank-sd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Fri, 29 Oct 2021 17:02:13 -0700 From: List-Id: To: , , , , , , CC: , , , , , Vamsi Krishna Lanka Subject: [PATCH v3 0/3] Add devicetree support for SDX65 Modem and MTP Date: Fri, 29 Oct 2021 17:02:02 -0700 Message-ID: <1635552125-16407-1-git-send-email-quic_vamslank@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) From: Vamsi Krishna Lanka Hello, Changes from v2: - Added cmd-db node to the sdx65 dtsi file Changes from v1: - Addressed Bjorn's comments This series adds devicetree support for Qualcomm SDX65 platform and MTP board. This series functionally depends on Add Pdc, GCC and RPMh Clock support series [1] and Add pinctrl support for SDX65 [2] which are under review. With this current devicetree support, the MTP can boot into initramfs shell. Thanks, Vamsi Vamsi krishna Lanka (3): dt-bindings: arm: qcom: Document SDX65 platform and boards ARM: dts: qcom: Add SDX65 platform and MTP board support ARM: dts: qcom: sdx65: Add pincontrol node Documentation/devicetree/bindings/arm/qcom.yaml | 6 + arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 25 +++ arch/arm/boot/dts/qcom-sdx65.dtsi | 222 ++++++++++++++++++++++++ 4 files changed, 255 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/qcom-sdx65-mtp.dts create mode 100644 arch/arm/boot/dts/qcom-sdx65.dtsi -- 2.7.4