SOC Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH v1] ARM: dts: add Nuvoton NPCM730 device tree
@ 2020-11-19  8:00 Tomer Maimon
  2020-11-19  8:00 ` Tomer Maimon
                   ` (2 more replies)
  0 siblings, 3 replies; 7+ messages in thread
From: Tomer Maimon @ 2020-11-19  8:00 UTC (permalink / raw)
  To: joel, arnd, olof, arm, soc, avifishman70, robh+dt, mark.rutland,
	yuenn, benjaminfair
  Cc: devicetree, linux-kernel, openbmc, Tomer Maimon

Add Nuvoton NPCM730 SoC device tree.

The Nuvoton NPCN730 SoC is a part of the
Nuvoton NPCM7xx SoCs family.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 arch/arm/boot/dts/nuvoton-npcm730.dtsi | 44 ++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi

diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
new file mode 100644
index 000000000000..86ec12ec2b50
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2020 Nuvoton Technology
+
+#include "nuvoton-common-npcm7xx.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "nuvoton,npcm750-smp";
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			clocks = <&clk NPCM7XX_CLK_CPU>;
+			clock-names = "clk_cpu";
+			reg = <0>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			clocks = <&clk NPCM7XX_CLK_CPU>;
+			clock-names = "clk_cpu";
+			reg = <1>;
+			next-level-cache = <&l2>;
+		};
+	};
+
+	soc {
+		timer@3fe600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x3fe600 0x20>;
+			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+						  IRQ_TYPE_LEVEL_HIGH)>;
+			clocks = <&clk NPCM7XX_CLK_AHB>;
+		};
+	};
+};
-- 
2.22.0


^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH v1] ARM: dts: add Nuvoton NPCM730 device tree
  2020-11-19  8:00 [PATCH v1] ARM: dts: add Nuvoton NPCM730 device tree Tomer Maimon
@ 2020-11-19  8:00 ` Tomer Maimon
  2020-11-19 18:39 ` Benjamin Fair
  2020-11-23 16:52 ` Arnd Bergmann
  2 siblings, 0 replies; 7+ messages in thread
From: Tomer Maimon @ 2020-11-19  8:00 UTC (permalink / raw)
  To: joel, arnd, olof, arm, soc, avifishman70, robh+dt, mark.rutland,
	yuenn, benjaminfair
  Cc: devicetree, openbmc, linux-kernel, Tomer Maimon

Add Nuvoton NPCM730 SoC device tree.

The Nuvoton NPCN730 SoC is a part of the
Nuvoton NPCM7xx SoCs family.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 arch/arm/boot/dts/nuvoton-npcm730.dtsi | 44 ++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi

diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
new file mode 100644
index 000000000000..86ec12ec2b50
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2020 Nuvoton Technology
+
+#include "nuvoton-common-npcm7xx.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "nuvoton,npcm750-smp";
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			clocks = <&clk NPCM7XX_CLK_CPU>;
+			clock-names = "clk_cpu";
+			reg = <0>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			clocks = <&clk NPCM7XX_CLK_CPU>;
+			clock-names = "clk_cpu";
+			reg = <1>;
+			next-level-cache = <&l2>;
+		};
+	};
+
+	soc {
+		timer@3fe600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x3fe600 0x20>;
+			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+						  IRQ_TYPE_LEVEL_HIGH)>;
+			clocks = <&clk NPCM7XX_CLK_AHB>;
+		};
+	};
+};
-- 
2.22.0


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH v1] ARM: dts: add Nuvoton NPCM730 device tree
  2020-11-19  8:00 [PATCH v1] ARM: dts: add Nuvoton NPCM730 device tree Tomer Maimon
  2020-11-19  8:00 ` Tomer Maimon
@ 2020-11-19 18:39 ` Benjamin Fair
  2020-11-19 18:39   ` Benjamin Fair
  2020-11-19 18:39   ` Benjamin Fair
  2020-11-23 16:52 ` Arnd Bergmann
  2 siblings, 2 replies; 7+ messages in thread
From: Benjamin Fair @ 2020-11-19 18:39 UTC (permalink / raw)
  To: Tomer Maimon
  Cc: Joel Stanley, Arnd Bergmann, olof, arm, soc, avifishman70,
	Rob Herring, mark.rutland, Nancy Yuen, devicetree, linux-kernel,
	OpenBMC Maillist

On Thu, 19 Nov 2020 at 00:00, Tomer Maimon <tmaimon77@gmail.com> wrote:
>
> Add Nuvoton NPCM730 SoC device tree.
>
> The Nuvoton NPCN730 SoC is a part of the
> Nuvoton NPCM7xx SoCs family.
>
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>

Reviewed-by: Benjamin Fair <benjaminfair@google.com>

>
> ---
>  arch/arm/boot/dts/nuvoton-npcm730.dtsi | 44 ++++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
>  create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi
>
> diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
> new file mode 100644
> index 000000000000..86ec12ec2b50
> --- /dev/null
> +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2020 Nuvoton Technology
> +
> +#include "nuvoton-common-npcm7xx.dtsi"
> +
> +/ {
> +       #address-cells = <1>;
> +       #size-cells = <1>;
> +       interrupt-parent = <&gic>;
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               enable-method = "nuvoton,npcm750-smp";
> +
> +               cpu@0 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a9";
> +                       clocks = <&clk NPCM7XX_CLK_CPU>;
> +                       clock-names = "clk_cpu";
> +                       reg = <0>;
> +                       next-level-cache = <&l2>;
> +               };
> +
> +               cpu@1 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a9";
> +                       clocks = <&clk NPCM7XX_CLK_CPU>;
> +                       clock-names = "clk_cpu";
> +                       reg = <1>;
> +                       next-level-cache = <&l2>;
> +               };
> +       };
> +
> +       soc {
> +               timer@3fe600 {
> +                       compatible = "arm,cortex-a9-twd-timer";
> +                       reg = <0x3fe600 0x20>;
> +                       interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
> +                                                 IRQ_TYPE_LEVEL_HIGH)>;
> +                       clocks = <&clk NPCM7XX_CLK_AHB>;
> +               };
> +       };
> +};
> --
> 2.22.0
>

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH v1] ARM: dts: add Nuvoton NPCM730 device tree
  2020-11-19 18:39 ` Benjamin Fair
  2020-11-19 18:39   ` Benjamin Fair
@ 2020-11-19 18:39   ` Benjamin Fair
  1 sibling, 0 replies; 7+ messages in thread
From: Benjamin Fair @ 2020-11-19 18:39 UTC (permalink / raw)
  To: Tomer Maimon
  Cc: Joel Stanley, Arnd Bergmann, olof, arm, soc, avifishman70,
	Rob Herring, mark.rutland, Nancy Yuen, devicetree, linux-kernel,
	OpenBMC Maillist

On Thu, 19 Nov 2020 at 00:00, Tomer Maimon <tmaimon77@gmail.com> wrote:
>
> Add Nuvoton NPCM730 SoC device tree.
>
> The Nuvoton NPCN730 SoC is a part of the
> Nuvoton NPCM7xx SoCs family.
>
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>

Reviewed-by: Benjamin Fair <benjaminfair@google.com>

>
> ---
>  arch/arm/boot/dts/nuvoton-npcm730.dtsi | 44 ++++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
>  create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi
>
> diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
> new file mode 100644
> index 000000000000..86ec12ec2b50
> --- /dev/null
> +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2020 Nuvoton Technology
> +
> +#include "nuvoton-common-npcm7xx.dtsi"
> +
> +/ {
> +       #address-cells = <1>;
> +       #size-cells = <1>;
> +       interrupt-parent = <&gic>;
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               enable-method = "nuvoton,npcm750-smp";
> +
> +               cpu@0 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a9";
> +                       clocks = <&clk NPCM7XX_CLK_CPU>;
> +                       clock-names = "clk_cpu";
> +                       reg = <0>;
> +                       next-level-cache = <&l2>;
> +               };
> +
> +               cpu@1 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a9";
> +                       clocks = <&clk NPCM7XX_CLK_CPU>;
> +                       clock-names = "clk_cpu";
> +                       reg = <1>;
> +                       next-level-cache = <&l2>;
> +               };
> +       };
> +
> +       soc {
> +               timer@3fe600 {
> +                       compatible = "arm,cortex-a9-twd-timer";
> +                       reg = <0x3fe600 0x20>;
> +                       interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
> +                                                 IRQ_TYPE_LEVEL_HIGH)>;
> +                       clocks = <&clk NPCM7XX_CLK_AHB>;
> +               };
> +       };
> +};
> --
> 2.22.0
>

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH v1] ARM: dts: add Nuvoton NPCM730 device tree
  2020-11-19 18:39 ` Benjamin Fair
@ 2020-11-19 18:39   ` Benjamin Fair
  2020-11-19 18:39   ` Benjamin Fair
  1 sibling, 0 replies; 7+ messages in thread
From: Benjamin Fair @ 2020-11-19 18:39 UTC (permalink / raw)
  To: Tomer Maimon
  Cc: mark.rutland, devicetree, Arnd Bergmann, avifishman70,
	OpenBMC Maillist, linux-kernel, Rob Herring, soc, arm, olof

On Thu, 19 Nov 2020 at 00:00, Tomer Maimon <tmaimon77@gmail.com> wrote:
>
> Add Nuvoton NPCM730 SoC device tree.
>
> The Nuvoton NPCN730 SoC is a part of the
> Nuvoton NPCM7xx SoCs family.
>
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>

Reviewed-by: Benjamin Fair <benjaminfair@google.com>

>
> ---
>  arch/arm/boot/dts/nuvoton-npcm730.dtsi | 44 ++++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
>  create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi
>
> diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
> new file mode 100644
> index 000000000000..86ec12ec2b50
> --- /dev/null
> +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2020 Nuvoton Technology
> +
> +#include "nuvoton-common-npcm7xx.dtsi"
> +
> +/ {
> +       #address-cells = <1>;
> +       #size-cells = <1>;
> +       interrupt-parent = <&gic>;
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               enable-method = "nuvoton,npcm750-smp";
> +
> +               cpu@0 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a9";
> +                       clocks = <&clk NPCM7XX_CLK_CPU>;
> +                       clock-names = "clk_cpu";
> +                       reg = <0>;
> +                       next-level-cache = <&l2>;
> +               };
> +
> +               cpu@1 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a9";
> +                       clocks = <&clk NPCM7XX_CLK_CPU>;
> +                       clock-names = "clk_cpu";
> +                       reg = <1>;
> +                       next-level-cache = <&l2>;
> +               };
> +       };
> +
> +       soc {
> +               timer@3fe600 {
> +                       compatible = "arm,cortex-a9-twd-timer";
> +                       reg = <0x3fe600 0x20>;
> +                       interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
> +                                                 IRQ_TYPE_LEVEL_HIGH)>;
> +                       clocks = <&clk NPCM7XX_CLK_AHB>;
> +               };
> +       };
> +};
> --
> 2.22.0
>

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH v1] ARM: dts: add Nuvoton NPCM730 device tree
  2020-11-19  8:00 [PATCH v1] ARM: dts: add Nuvoton NPCM730 device tree Tomer Maimon
  2020-11-19  8:00 ` Tomer Maimon
  2020-11-19 18:39 ` Benjamin Fair
@ 2020-11-23 16:52 ` Arnd Bergmann
  2020-11-23 16:52   ` Arnd Bergmann
  2 siblings, 1 reply; 7+ messages in thread
From: Arnd Bergmann @ 2020-11-23 16:52 UTC (permalink / raw)
  To: mark.rutland, soc, olof, benjaminfair, avifishman70, arm, joel,
	robh+dt, yuenn, Tomer Maimon
  Cc: Arnd Bergmann, devicetree, openbmc, linux-kernel

From: Arnd Bergmann <arnd@arndb.de>

On Thu, 19 Nov 2020 10:00:02 +0200, Tomer Maimon wrote:
> Add Nuvoton NPCM730 SoC device tree.
> 
> The Nuvoton NPCN730 SoC is a part of the
> Nuvoton NPCM7xx SoCs family.

Applied to arm/dt, thanks!

[1/1] ARM: dts: add Nuvoton NPCM730 device tree
      commit: b2d91953b66c724eaf8d7f84f37c006d966f67ac

       Arnd

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH v1] ARM: dts: add Nuvoton NPCM730 device tree
  2020-11-23 16:52 ` Arnd Bergmann
@ 2020-11-23 16:52   ` Arnd Bergmann
  0 siblings, 0 replies; 7+ messages in thread
From: Arnd Bergmann @ 2020-11-23 16:52 UTC (permalink / raw)
  To: mark.rutland, soc, olof, benjaminfair, avifishman70, arm, joel,
	robh+dt, yuenn, Tomer Maimon
  Cc: devicetree, openbmc, linux-kernel, Arnd Bergmann

From: Arnd Bergmann <arnd@arndb.de>

On Thu, 19 Nov 2020 10:00:02 +0200, Tomer Maimon wrote:
> Add Nuvoton NPCM730 SoC device tree.
> 
> The Nuvoton NPCN730 SoC is a part of the
> Nuvoton NPCM7xx SoCs family.

Applied to arm/dt, thanks!

[1/1] ARM: dts: add Nuvoton NPCM730 device tree
      commit: b2d91953b66c724eaf8d7f84f37c006d966f67ac

       Arnd

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, back to index

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-19  8:00 [PATCH v1] ARM: dts: add Nuvoton NPCM730 device tree Tomer Maimon
2020-11-19  8:00 ` Tomer Maimon
2020-11-19 18:39 ` Benjamin Fair
2020-11-19 18:39   ` Benjamin Fair
2020-11-19 18:39   ` Benjamin Fair
2020-11-23 16:52 ` Arnd Bergmann
2020-11-23 16:52   ` Arnd Bergmann

SOC Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/soc/0 soc/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 soc soc/ https://lore.kernel.org/soc \
		soc@kernel.org
	public-inbox-index soc

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.lore.soc


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git