Changes from v2: - Introduce boards to Makefile in same patch as the board dts is added (Vladimir Oltean) - Use alphabetical ordering for labels (Vladimir Oltean) - Remove address-cells and size-cells in qca8337 switch nodes (Vladimir Oltean) - Remove "cpu" labels from switch nodes' CPU ports (Vladimir Oltean) - Various LED fixes, utilising dt-bindings/leds/common.h and correctly specifying LEDs in the form "led-N" and with the color/function/ function-enumerator properties. - Fix PWM LEDs and corresponding pinctrl bindings. (Vladimir Oltean) The following changes were submitted as a separate series: - Introduce patches to disable QSPI by default and enable where used (Vladimir Oltean) - Move mdio@18032000 node from board related file to SoC (Vladimir Oltean) - In addition to above, relocate mdio-mux to bcm-nsp.dtsi and fix the resulting usb3_phy issues Changes from v3: - Sort labels on mx64 a0 dts files into alphabetical order as well - move include directives for input/input.h and leds/common.h to bcm958625-mx6x-common.dtsi - Whitespace fixes in bcm958625-mx6x-common.dtsi - rename "senao_nvram" partition to "nvram" Changes from v4: - Move chosen and memory nodes from bcm958625-mx6x-common.dtsi to each .dts file (Arnd Bergmann). - Append [@<unit-address>] to memory nodes. - Create Ax stepping-specific dtsi for Ax devices (Arnd Bergmann). - Append read-only property to at24 eeprom node. - Remove L2 properties which should be defined at platform-level. - Correct NAND node names. Matthew Hagan (5): ARM: dts: NSP: Add common bindings for MX64/MX65 ARM: dts: NSP: Add Ax stepping modifications ARM: dts: NSP: Add DT files for Meraki MX64 series ARM: dts: NSP: Add DT files for Meraki MX65 series dt-bindings: arm: bcm: NSP: add Meraki MX64/MX65 .../devicetree/bindings/arm/bcm/brcm,nsp.yaml | 6 + arch/arm/boot/dts/Makefile | 6 + arch/arm/boot/dts/bcm-nsp-ax.dtsi | 71 +++++ arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 279 ++++++++++++++++++ .../boot/dts/bcm958625-meraki-kingpin.dtsi | 163 ++++++++++ .../arm/boot/dts/bcm958625-meraki-mx64-a0.dts | 25 ++ arch/arm/boot/dts/bcm958625-meraki-mx64.dts | 24 ++ .../boot/dts/bcm958625-meraki-mx64w-a0.dts | 33 +++ arch/arm/boot/dts/bcm958625-meraki-mx64w.dts | 32 ++ arch/arm/boot/dts/bcm958625-meraki-mx65.dts | 24 ++ arch/arm/boot/dts/bcm958625-meraki-mx65w.dts | 32 ++ .../dts/bcm958625-meraki-mx6x-common.dtsi | 129 ++++++++ 12 files changed, 824 insertions(+) create mode 100644 arch/arm/boot/dts/bcm-nsp-ax.dtsi create mode 100644 arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi create mode 100644 arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65w.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi -- 2.26.3
Changes from v2: - Introduce boards to Makefile in same patch as the board dts is added (Vladimir Oltean) - Use alphabetical ordering for labels (Vladimir Oltean) - Remove address-cells and size-cells in qca8337 switch nodes (Vladimir Oltean) - Remove "cpu" labels from switch nodes' CPU ports (Vladimir Oltean) - Various LED fixes, utilising dt-bindings/leds/common.h and correctly specifying LEDs in the form "led-N" and with the color/function/ function-enumerator properties. - Fix PWM LEDs and corresponding pinctrl bindings. (Vladimir Oltean) The following changes were submitted as a separate series: - Introduce patches to disable QSPI by default and enable where used (Vladimir Oltean) - Move mdio@18032000 node from board related file to SoC (Vladimir Oltean) - In addition to above, relocate mdio-mux to bcm-nsp.dtsi and fix the resulting usb3_phy issues Changes from v3: - Sort labels on mx64 a0 dts files into alphabetical order as well - move include directives for input/input.h and leds/common.h to bcm958625-mx6x-common.dtsi - Whitespace fixes in bcm958625-mx6x-common.dtsi - rename "senao_nvram" partition to "nvram" Changes from v4: - Move chosen and memory nodes from bcm958625-mx6x-common.dtsi to each .dts file (Arnd Bergmann). - Append [@<unit-address>] to memory nodes. - Create Ax stepping-specific dtsi for Ax devices (Arnd Bergmann). - Append read-only property to at24 eeprom node. - Remove L2 properties which should be defined at platform-level. - Correct NAND node names. Matthew Hagan (5): ARM: dts: NSP: Add common bindings for MX64/MX65 ARM: dts: NSP: Add Ax stepping modifications ARM: dts: NSP: Add DT files for Meraki MX64 series ARM: dts: NSP: Add DT files for Meraki MX65 series dt-bindings: arm: bcm: NSP: add Meraki MX64/MX65 .../devicetree/bindings/arm/bcm/brcm,nsp.yaml | 6 + arch/arm/boot/dts/Makefile | 6 + arch/arm/boot/dts/bcm-nsp-ax.dtsi | 71 +++++ arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 279 ++++++++++++++++++ .../boot/dts/bcm958625-meraki-kingpin.dtsi | 163 ++++++++++ .../arm/boot/dts/bcm958625-meraki-mx64-a0.dts | 25 ++ arch/arm/boot/dts/bcm958625-meraki-mx64.dts | 24 ++ .../boot/dts/bcm958625-meraki-mx64w-a0.dts | 33 +++ arch/arm/boot/dts/bcm958625-meraki-mx64w.dts | 32 ++ arch/arm/boot/dts/bcm958625-meraki-mx65.dts | 24 ++ arch/arm/boot/dts/bcm958625-meraki-mx65w.dts | 32 ++ .../dts/bcm958625-meraki-mx6x-common.dtsi | 129 ++++++++ 12 files changed, 824 insertions(+) create mode 100644 arch/arm/boot/dts/bcm-nsp-ax.dtsi create mode 100644 arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi create mode 100644 arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65w.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi -- 2.26.3
Changes from v2: - Introduce boards to Makefile in same patch as the board dts is added (Vladimir Oltean) - Use alphabetical ordering for labels (Vladimir Oltean) - Remove address-cells and size-cells in qca8337 switch nodes (Vladimir Oltean) - Remove "cpu" labels from switch nodes' CPU ports (Vladimir Oltean) - Various LED fixes, utilising dt-bindings/leds/common.h and correctly specifying LEDs in the form "led-N" and with the color/function/ function-enumerator properties. - Fix PWM LEDs and corresponding pinctrl bindings. (Vladimir Oltean) The following changes were submitted as a separate series: - Introduce patches to disable QSPI by default and enable where used (Vladimir Oltean) - Move mdio@18032000 node from board related file to SoC (Vladimir Oltean) - In addition to above, relocate mdio-mux to bcm-nsp.dtsi and fix the resulting usb3_phy issues Changes from v3: - Sort labels on mx64 a0 dts files into alphabetical order as well - move include directives for input/input.h and leds/common.h to bcm958625-mx6x-common.dtsi - Whitespace fixes in bcm958625-mx6x-common.dtsi - rename "senao_nvram" partition to "nvram" Changes from v4: - Move chosen and memory nodes from bcm958625-mx6x-common.dtsi to each .dts file (Arnd Bergmann). - Append [@<unit-address>] to memory nodes. - Create Ax stepping-specific dtsi for Ax devices (Arnd Bergmann). - Append read-only property to at24 eeprom node. - Remove L2 properties which should be defined at platform-level. - Correct NAND node names. Matthew Hagan (5): ARM: dts: NSP: Add common bindings for MX64/MX65 ARM: dts: NSP: Add Ax stepping modifications ARM: dts: NSP: Add DT files for Meraki MX64 series ARM: dts: NSP: Add DT files for Meraki MX65 series dt-bindings: arm: bcm: NSP: add Meraki MX64/MX65 .../devicetree/bindings/arm/bcm/brcm,nsp.yaml | 6 + arch/arm/boot/dts/Makefile | 6 + arch/arm/boot/dts/bcm-nsp-ax.dtsi | 71 +++++ arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 279 ++++++++++++++++++ .../boot/dts/bcm958625-meraki-kingpin.dtsi | 163 ++++++++++ .../arm/boot/dts/bcm958625-meraki-mx64-a0.dts | 25 ++ arch/arm/boot/dts/bcm958625-meraki-mx64.dts | 24 ++ .../boot/dts/bcm958625-meraki-mx64w-a0.dts | 33 +++ arch/arm/boot/dts/bcm958625-meraki-mx64w.dts | 32 ++ arch/arm/boot/dts/bcm958625-meraki-mx65.dts | 24 ++ arch/arm/boot/dts/bcm958625-meraki-mx65w.dts | 32 ++ .../dts/bcm958625-meraki-mx6x-common.dtsi | 129 ++++++++ 12 files changed, 824 insertions(+) create mode 100644 arch/arm/boot/dts/bcm-nsp-ax.dtsi create mode 100644 arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi create mode 100644 arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65w.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi -- 2.26.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
These bindings are required for all Meraki MX64/MX65 devices. These common bindings include memory (2GB), PWM LEDs, AMAC, I2C (AT24), NAND partitions, EHCI, OHCI and pinctrl. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> --- .../dts/bcm958625-meraki-mx6x-common.dtsi | 129 ++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi new file mode 100644 index 000000000000..bcdd38954f1d --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +#include "bcm-nsp.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + pwm-leds { + compatible = "pwm-leds"; + + led-1 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_RED>; + pwms = <&pwm 1 50000>; + max-brightness = <255>; + }; + + led-2 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_GREEN>; + pwms = <&pwm 2 50000>; + max-brightness = <255>; + }; + + led-3 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_BLUE>; + pwms = <&pwm 3 50000>; + max-brightness = <255>; + }; + }; +}; + +&amac2 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + read-only; + }; +}; + +&nand_controller { + nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "shmoo"; + reg = <0x80000 0x80000>; + read-only; + }; + + partition@100000 { + label = "bootkernel1"; + reg = <0x100000 0x300000>; + }; + + partition@400000 { + label = "nvram"; + reg = <0x400000 0x100000>; + }; + + partition@500000 { + label = "bootkernel2"; + reg = <0x500000 0x300000>; + }; + + partition@800000 { + label = "ubi"; + reg = <0x800000 0x3f700000>; + }; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_leds>; + + pwm_leds: pwm_leds { + function = "pwm"; + groups = "pwm1_grp", "pwm2_grp", "pwm3_grp"; + }; +}; + +&pwm { + status = "okay"; + #pwm-cells = <2>; +}; + +&uart0 { + clock-frequency = <62500000>; + status = "okay"; +}; -- 2.26.3
These bindings are required for all Meraki MX64/MX65 devices. These common bindings include memory (2GB), PWM LEDs, AMAC, I2C (AT24), NAND partitions, EHCI, OHCI and pinctrl. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> --- .../dts/bcm958625-meraki-mx6x-common.dtsi | 129 ++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi new file mode 100644 index 000000000000..bcdd38954f1d --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +#include "bcm-nsp.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + pwm-leds { + compatible = "pwm-leds"; + + led-1 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_RED>; + pwms = <&pwm 1 50000>; + max-brightness = <255>; + }; + + led-2 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_GREEN>; + pwms = <&pwm 2 50000>; + max-brightness = <255>; + }; + + led-3 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_BLUE>; + pwms = <&pwm 3 50000>; + max-brightness = <255>; + }; + }; +}; + +&amac2 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + read-only; + }; +}; + +&nand_controller { + nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "shmoo"; + reg = <0x80000 0x80000>; + read-only; + }; + + partition@100000 { + label = "bootkernel1"; + reg = <0x100000 0x300000>; + }; + + partition@400000 { + label = "nvram"; + reg = <0x400000 0x100000>; + }; + + partition@500000 { + label = "bootkernel2"; + reg = <0x500000 0x300000>; + }; + + partition@800000 { + label = "ubi"; + reg = <0x800000 0x3f700000>; + }; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_leds>; + + pwm_leds: pwm_leds { + function = "pwm"; + groups = "pwm1_grp", "pwm2_grp", "pwm3_grp"; + }; +}; + +&pwm { + status = "okay"; + #pwm-cells = <2>; +}; + +&uart0 { + clock-frequency = <62500000>; + status = "okay"; +}; -- 2.26.3
These bindings are required for all Meraki MX64/MX65 devices. These common bindings include memory (2GB), PWM LEDs, AMAC, I2C (AT24), NAND partitions, EHCI, OHCI and pinctrl. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> --- .../dts/bcm958625-meraki-mx6x-common.dtsi | 129 ++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi new file mode 100644 index 000000000000..bcdd38954f1d --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +#include "bcm-nsp.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + pwm-leds { + compatible = "pwm-leds"; + + led-1 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_RED>; + pwms = <&pwm 1 50000>; + max-brightness = <255>; + }; + + led-2 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_GREEN>; + pwms = <&pwm 2 50000>; + max-brightness = <255>; + }; + + led-3 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_BLUE>; + pwms = <&pwm 3 50000>; + max-brightness = <255>; + }; + }; +}; + +&amac2 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + read-only; + }; +}; + +&nand_controller { + nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "shmoo"; + reg = <0x80000 0x80000>; + read-only; + }; + + partition@100000 { + label = "bootkernel1"; + reg = <0x100000 0x300000>; + }; + + partition@400000 { + label = "nvram"; + reg = <0x400000 0x100000>; + }; + + partition@500000 { + label = "bootkernel2"; + reg = <0x500000 0x300000>; + }; + + partition@800000 { + label = "ubi"; + reg = <0x800000 0x3f700000>; + }; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_leds>; + + pwm_leds: pwm_leds { + function = "pwm"; + groups = "pwm1_grp", "pwm2_grp", "pwm3_grp"; + }; +}; + +&pwm { + status = "okay"; + #pwm-cells = <2>; +}; + +&uart0 { + clock-frequency = <62500000>; + status = "okay"; +}; -- 2.26.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
While uncommon, some Ax NSP SoCs exist in the wild. This stepping requires a modified secondary CPU boot-reg and removal of DMA coherency properties. Without these modifications, the secondary CPU will be inactive and many peripherals will exhibit undefined behaviour. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> --- arch/arm/boot/dts/bcm-nsp-ax.dtsi | 70 +++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 arch/arm/boot/dts/bcm-nsp-ax.dtsi diff --git a/arch/arm/boot/dts/bcm-nsp-ax.dtsi b/arch/arm/boot/dts/bcm-nsp-ax.dtsi new file mode 100644 index 000000000000..a21e275935ce --- /dev/null +++ b/arch/arm/boot/dts/bcm-nsp-ax.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom Northstar Plus Ax stepping-specific bindings. + * Notable differences from B0+ are the secondary-boot-reg and + * lack of DMA coherency. + */ + +&cpu1 { + secondary-boot-reg = <0xffff042c>; +}; + +&dma { + /delete-property/ dma-coherent; +}; + +&sdio { + /delete-property/ dma-coherent; +}; + +&amac0 { + /delete-property/ dma-coherent; +}; + +&amac1 { + /delete-property/ dma-coherent; +}; + +&amac2 { + /delete-property/ dma-coherent; +}; + +&ehci0 { + /delete-property/ dma-coherent; +}; + +&mailbox { + /delete-property/ dma-coherent; +}; + +&xhci { + /delete-property/ dma-coherent; +}; + +&ehci0 { + /delete-property/ dma-coherent; +}; + +&ohci0 { + /delete-property/ dma-coherent; +}; + +&i2c0 { + /delete-property/ dma-coherent; +}; + +&sata { + /delete-property/ dma-coherent; +}; + +&pcie0 { + /delete-property/ dma-coherent; +}; + +&pcie1 { + /delete-property/ dma-coherent; +}; + +&pcie2 { + /delete-property/ dma-coherent; +}; -- 2.26.3
While uncommon, some Ax NSP SoCs exist in the wild. This stepping requires a modified secondary CPU boot-reg and removal of DMA coherency properties. Without these modifications, the secondary CPU will be inactive and many peripherals will exhibit undefined behaviour. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> --- arch/arm/boot/dts/bcm-nsp-ax.dtsi | 70 +++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 arch/arm/boot/dts/bcm-nsp-ax.dtsi diff --git a/arch/arm/boot/dts/bcm-nsp-ax.dtsi b/arch/arm/boot/dts/bcm-nsp-ax.dtsi new file mode 100644 index 000000000000..a21e275935ce --- /dev/null +++ b/arch/arm/boot/dts/bcm-nsp-ax.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom Northstar Plus Ax stepping-specific bindings. + * Notable differences from B0+ are the secondary-boot-reg and + * lack of DMA coherency. + */ + +&cpu1 { + secondary-boot-reg = <0xffff042c>; +}; + +&dma { + /delete-property/ dma-coherent; +}; + +&sdio { + /delete-property/ dma-coherent; +}; + +&amac0 { + /delete-property/ dma-coherent; +}; + +&amac1 { + /delete-property/ dma-coherent; +}; + +&amac2 { + /delete-property/ dma-coherent; +}; + +&ehci0 { + /delete-property/ dma-coherent; +}; + +&mailbox { + /delete-property/ dma-coherent; +}; + +&xhci { + /delete-property/ dma-coherent; +}; + +&ehci0 { + /delete-property/ dma-coherent; +}; + +&ohci0 { + /delete-property/ dma-coherent; +}; + +&i2c0 { + /delete-property/ dma-coherent; +}; + +&sata { + /delete-property/ dma-coherent; +}; + +&pcie0 { + /delete-property/ dma-coherent; +}; + +&pcie1 { + /delete-property/ dma-coherent; +}; + +&pcie2 { + /delete-property/ dma-coherent; +}; -- 2.26.3
While uncommon, some Ax NSP SoCs exist in the wild. This stepping requires a modified secondary CPU boot-reg and removal of DMA coherency properties. Without these modifications, the secondary CPU will be inactive and many peripherals will exhibit undefined behaviour. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> --- arch/arm/boot/dts/bcm-nsp-ax.dtsi | 70 +++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 arch/arm/boot/dts/bcm-nsp-ax.dtsi diff --git a/arch/arm/boot/dts/bcm-nsp-ax.dtsi b/arch/arm/boot/dts/bcm-nsp-ax.dtsi new file mode 100644 index 000000000000..a21e275935ce --- /dev/null +++ b/arch/arm/boot/dts/bcm-nsp-ax.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom Northstar Plus Ax stepping-specific bindings. + * Notable differences from B0+ are the secondary-boot-reg and + * lack of DMA coherency. + */ + +&cpu1 { + secondary-boot-reg = <0xffff042c>; +}; + +&dma { + /delete-property/ dma-coherent; +}; + +&sdio { + /delete-property/ dma-coherent; +}; + +&amac0 { + /delete-property/ dma-coherent; +}; + +&amac1 { + /delete-property/ dma-coherent; +}; + +&amac2 { + /delete-property/ dma-coherent; +}; + +&ehci0 { + /delete-property/ dma-coherent; +}; + +&mailbox { + /delete-property/ dma-coherent; +}; + +&xhci { + /delete-property/ dma-coherent; +}; + +&ehci0 { + /delete-property/ dma-coherent; +}; + +&ohci0 { + /delete-property/ dma-coherent; +}; + +&i2c0 { + /delete-property/ dma-coherent; +}; + +&sata { + /delete-property/ dma-coherent; +}; + +&pcie0 { + /delete-property/ dma-coherent; +}; + +&pcie1 { + /delete-property/ dma-coherent; +}; + +&pcie2 { + /delete-property/ dma-coherent; +}; -- 2.26.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
MX64 & MX64W Hardware info: - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) - Storage: 1 GB (Micron MT29F8G08ABACA) - Networking: BCM58625 internal switch (5x 1GbE ports) - USB: 1x USB2.0 - Serial: Internal header - WLAN(MX64W only): 2x Broadcom BCM43520KMLG on the PCI bus This patch adds the Meraki MX64 series-specific bindings. Since some devices make use of the older A0 SoC, changes need to be made to accommodate this case, including removal of coherency options and modification to the secondary-boot-reg. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> --- arch/arm/boot/dts/Makefile | 4 + .../boot/dts/bcm958625-meraki-kingpin.dtsi | 163 ++++++++++++++++++ .../arm/boot/dts/bcm958625-meraki-mx64-a0.dts | 25 +++ arch/arm/boot/dts/bcm958625-meraki-mx64.dts | 24 +++ .../boot/dts/bcm958625-meraki-mx64w-a0.dts | 33 ++++ arch/arm/boot/dts/bcm958625-meraki-mx64w.dts | 32 ++++ 6 files changed, 281 insertions(+) create mode 100644 arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 863347b6b65e..17f7bdab50ef 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -155,6 +155,10 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \ bcm958525xmc.dtb \ bcm958622hr.dtb \ bcm958623hr.dtb \ + bcm958625-meraki-mx64.dtb \ + bcm958625-meraki-mx64-a0.dtb \ + bcm958625-meraki-mx64w.dtb \ + bcm958625-meraki-mx64w-a0.dtb \ bcm958625hr.dtb \ bcm988312hr.dtb \ bcm958625k.dtb diff --git a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi new file mode 100644 index 000000000000..7c487c74fd10 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 series (Kingpin). + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +#include "bcm958625-meraki-mx6x-common.dtsi" + +/ { + + keys { + compatible = "gpio-keys-polled"; + autorepeat; + poll-interval = <20>; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpioa 6 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + /* green:lan1-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <0>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 19 GPIO_ACTIVE_LOW>; + }; + + led-1 { + /* green:lan1-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <1>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 18 GPIO_ACTIVE_LOW>; + }; + + led-2 { + /* green:lan2-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <2>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 24 GPIO_ACTIVE_LOW>; + }; + + led-3 { + /* green:lan2-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <3>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 20 GPIO_ACTIVE_LOW>; + }; + + led-4 { + /* green:lan3-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <4>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 26 GPIO_ACTIVE_LOW>; + }; + + led-5 { + /* green:lan3-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <5>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 25 GPIO_ACTIVE_LOW>; + }; + + led-6 { + /* green:lan4-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <6>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 28 GPIO_ACTIVE_LOW>; + }; + + led-7 { + /* green:lan4-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <7>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 27 GPIO_ACTIVE_LOW>; + }; + + led-8 { + /* green:wan-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <8>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 30 GPIO_ACTIVE_LOW>; + }; + + led-9 { + /* green:wan-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <9>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 29 GPIO_ACTIVE_LOW>; + }; + + led-a { + /* amber:power */ + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_AMBER>; + gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-b { + /* white:status */ + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_WHITE>; + gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&srab { + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + port@0 { + label = "lan1"; + reg = <0>; + }; + + port@1 { + label = "lan2"; + reg = <1>; + }; + + port@2 { + label = "lan3"; + reg = <2>; + }; + + port@3 { + label = "lan4"; + reg = <3>; + }; + + port@4 { + label = "wan"; + reg = <4>; + }; + + port@8 { + ethernet = <&amac2>; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts new file mode 100644 index 000000000000..9944566c1195 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 with A0 SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" +#include "bcm-nsp-ax.dtsi" + +/ { + model = "Cisco Meraki MX64(A0)"; + compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64.dts new file mode 100644 index 000000000000..06939438e874 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" + +/ { + model = "Cisco Meraki MX64"; + compatible = "meraki,mx64", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts new file mode 100644 index 000000000000..112fddb1eed8 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64W with A0 SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" +#include "bcm-nsp-ax.dtsi" + +/ { + model = "Cisco Meraki MX64W(A0)"; + compatible = "meraki,mx64w-a0", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts new file mode 100644 index 000000000000..de2e367c3e78 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64W with B0+ SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" + +/ { + model = "Cisco Meraki MX64W"; + compatible = "meraki,mx64w", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; -- 2.26.3
MX64 & MX64W Hardware info: - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) - Storage: 1 GB (Micron MT29F8G08ABACA) - Networking: BCM58625 internal switch (5x 1GbE ports) - USB: 1x USB2.0 - Serial: Internal header - WLAN(MX64W only): 2x Broadcom BCM43520KMLG on the PCI bus This patch adds the Meraki MX64 series-specific bindings. Since some devices make use of the older A0 SoC, changes need to be made to accommodate this case, including removal of coherency options and modification to the secondary-boot-reg. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> --- arch/arm/boot/dts/Makefile | 4 + .../boot/dts/bcm958625-meraki-kingpin.dtsi | 163 ++++++++++++++++++ .../arm/boot/dts/bcm958625-meraki-mx64-a0.dts | 25 +++ arch/arm/boot/dts/bcm958625-meraki-mx64.dts | 24 +++ .../boot/dts/bcm958625-meraki-mx64w-a0.dts | 33 ++++ arch/arm/boot/dts/bcm958625-meraki-mx64w.dts | 32 ++++ 6 files changed, 281 insertions(+) create mode 100644 arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 863347b6b65e..17f7bdab50ef 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -155,6 +155,10 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \ bcm958525xmc.dtb \ bcm958622hr.dtb \ bcm958623hr.dtb \ + bcm958625-meraki-mx64.dtb \ + bcm958625-meraki-mx64-a0.dtb \ + bcm958625-meraki-mx64w.dtb \ + bcm958625-meraki-mx64w-a0.dtb \ bcm958625hr.dtb \ bcm988312hr.dtb \ bcm958625k.dtb diff --git a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi new file mode 100644 index 000000000000..7c487c74fd10 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 series (Kingpin). + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +#include "bcm958625-meraki-mx6x-common.dtsi" + +/ { + + keys { + compatible = "gpio-keys-polled"; + autorepeat; + poll-interval = <20>; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpioa 6 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + /* green:lan1-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <0>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 19 GPIO_ACTIVE_LOW>; + }; + + led-1 { + /* green:lan1-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <1>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 18 GPIO_ACTIVE_LOW>; + }; + + led-2 { + /* green:lan2-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <2>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 24 GPIO_ACTIVE_LOW>; + }; + + led-3 { + /* green:lan2-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <3>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 20 GPIO_ACTIVE_LOW>; + }; + + led-4 { + /* green:lan3-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <4>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 26 GPIO_ACTIVE_LOW>; + }; + + led-5 { + /* green:lan3-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <5>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 25 GPIO_ACTIVE_LOW>; + }; + + led-6 { + /* green:lan4-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <6>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 28 GPIO_ACTIVE_LOW>; + }; + + led-7 { + /* green:lan4-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <7>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 27 GPIO_ACTIVE_LOW>; + }; + + led-8 { + /* green:wan-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <8>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 30 GPIO_ACTIVE_LOW>; + }; + + led-9 { + /* green:wan-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <9>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 29 GPIO_ACTIVE_LOW>; + }; + + led-a { + /* amber:power */ + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_AMBER>; + gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-b { + /* white:status */ + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_WHITE>; + gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&srab { + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + port@0 { + label = "lan1"; + reg = <0>; + }; + + port@1 { + label = "lan2"; + reg = <1>; + }; + + port@2 { + label = "lan3"; + reg = <2>; + }; + + port@3 { + label = "lan4"; + reg = <3>; + }; + + port@4 { + label = "wan"; + reg = <4>; + }; + + port@8 { + ethernet = <&amac2>; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts new file mode 100644 index 000000000000..9944566c1195 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 with A0 SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" +#include "bcm-nsp-ax.dtsi" + +/ { + model = "Cisco Meraki MX64(A0)"; + compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64.dts new file mode 100644 index 000000000000..06939438e874 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" + +/ { + model = "Cisco Meraki MX64"; + compatible = "meraki,mx64", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts new file mode 100644 index 000000000000..112fddb1eed8 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64W with A0 SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" +#include "bcm-nsp-ax.dtsi" + +/ { + model = "Cisco Meraki MX64W(A0)"; + compatible = "meraki,mx64w-a0", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts new file mode 100644 index 000000000000..de2e367c3e78 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64W with B0+ SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" + +/ { + model = "Cisco Meraki MX64W"; + compatible = "meraki,mx64w", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; -- 2.26.3
MX64 & MX64W Hardware info: - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) - Storage: 1 GB (Micron MT29F8G08ABACA) - Networking: BCM58625 internal switch (5x 1GbE ports) - USB: 1x USB2.0 - Serial: Internal header - WLAN(MX64W only): 2x Broadcom BCM43520KMLG on the PCI bus This patch adds the Meraki MX64 series-specific bindings. Since some devices make use of the older A0 SoC, changes need to be made to accommodate this case, including removal of coherency options and modification to the secondary-boot-reg. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> --- arch/arm/boot/dts/Makefile | 4 + .../boot/dts/bcm958625-meraki-kingpin.dtsi | 163 ++++++++++++++++++ .../arm/boot/dts/bcm958625-meraki-mx64-a0.dts | 25 +++ arch/arm/boot/dts/bcm958625-meraki-mx64.dts | 24 +++ .../boot/dts/bcm958625-meraki-mx64w-a0.dts | 33 ++++ arch/arm/boot/dts/bcm958625-meraki-mx64w.dts | 32 ++++ 6 files changed, 281 insertions(+) create mode 100644 arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 863347b6b65e..17f7bdab50ef 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -155,6 +155,10 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \ bcm958525xmc.dtb \ bcm958622hr.dtb \ bcm958623hr.dtb \ + bcm958625-meraki-mx64.dtb \ + bcm958625-meraki-mx64-a0.dtb \ + bcm958625-meraki-mx64w.dtb \ + bcm958625-meraki-mx64w-a0.dtb \ bcm958625hr.dtb \ bcm988312hr.dtb \ bcm958625k.dtb diff --git a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi new file mode 100644 index 000000000000..7c487c74fd10 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 series (Kingpin). + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +#include "bcm958625-meraki-mx6x-common.dtsi" + +/ { + + keys { + compatible = "gpio-keys-polled"; + autorepeat; + poll-interval = <20>; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpioa 6 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + /* green:lan1-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <0>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 19 GPIO_ACTIVE_LOW>; + }; + + led-1 { + /* green:lan1-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <1>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 18 GPIO_ACTIVE_LOW>; + }; + + led-2 { + /* green:lan2-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <2>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 24 GPIO_ACTIVE_LOW>; + }; + + led-3 { + /* green:lan2-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <3>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 20 GPIO_ACTIVE_LOW>; + }; + + led-4 { + /* green:lan3-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <4>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 26 GPIO_ACTIVE_LOW>; + }; + + led-5 { + /* green:lan3-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <5>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 25 GPIO_ACTIVE_LOW>; + }; + + led-6 { + /* green:lan4-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <6>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 28 GPIO_ACTIVE_LOW>; + }; + + led-7 { + /* green:lan4-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <7>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 27 GPIO_ACTIVE_LOW>; + }; + + led-8 { + /* green:wan-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <8>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 30 GPIO_ACTIVE_LOW>; + }; + + led-9 { + /* green:wan-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <9>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 29 GPIO_ACTIVE_LOW>; + }; + + led-a { + /* amber:power */ + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_AMBER>; + gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-b { + /* white:status */ + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_WHITE>; + gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&srab { + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + port@0 { + label = "lan1"; + reg = <0>; + }; + + port@1 { + label = "lan2"; + reg = <1>; + }; + + port@2 { + label = "lan3"; + reg = <2>; + }; + + port@3 { + label = "lan4"; + reg = <3>; + }; + + port@4 { + label = "wan"; + reg = <4>; + }; + + port@8 { + ethernet = <&amac2>; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts new file mode 100644 index 000000000000..9944566c1195 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 with A0 SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" +#include "bcm-nsp-ax.dtsi" + +/ { + model = "Cisco Meraki MX64(A0)"; + compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64.dts new file mode 100644 index 000000000000..06939438e874 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" + +/ { + model = "Cisco Meraki MX64"; + compatible = "meraki,mx64", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts new file mode 100644 index 000000000000..112fddb1eed8 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64W with A0 SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" +#include "bcm-nsp-ax.dtsi" + +/ { + model = "Cisco Meraki MX64W(A0)"; + compatible = "meraki,mx64w-a0", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts new file mode 100644 index 000000000000..de2e367c3e78 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64W with B0+ SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" + +/ { + model = "Cisco Meraki MX64W"; + compatible = "meraki,mx64w", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; -- 2.26.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
MX65 & MX65W Hardware info: - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) - Storage: 1 GB (Micron MT29F8G08ABACA) - Networking: BCM58625 switch (2x 1GbE ports) 2x Qualcomm QCA8337 switches (10x 1GbE ports total) - PSE: Broadcom BCM59111KMLG connected to LAN ports 11 & 12 - USB: 1x USB2.0 - Serial: Internal header - WLAN(MX65W Only): 2x Broadcom BCM43520KMLG on the PCI bus. Note that a driver and firmware image for the BCM59111 PSE has been released under GPL, but this is not present in the kernel. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 279 ++++++++++++++++++ arch/arm/boot/dts/bcm958625-meraki-mx65.dts | 24 ++ arch/arm/boot/dts/bcm958625-meraki-mx65w.dts | 32 ++ 4 files changed, 337 insertions(+) create mode 100644 arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65w.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 17f7bdab50ef..3586b540e3b6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -159,6 +159,8 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \ bcm958625-meraki-mx64-a0.dtb \ bcm958625-meraki-mx64w.dtb \ bcm958625-meraki-mx64w-a0.dtb \ + bcm958625-meraki-mx65.dtb \ + bcm958625-meraki-mx65w.dtb \ bcm958625hr.dtb \ bcm988312hr.dtb \ bcm958625k.dtb diff --git a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi new file mode 100644 index 000000000000..8860f2fefc63 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX65 series (Alamo). + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +#include "bcm958625-meraki-mx6x-common.dtsi" + +/ { + keys { + compatible = "gpio-keys-polled"; + autorepeat; + poll-interval = <20>; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpioa 8 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + /* green:wan1-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <0>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 25 GPIO_ACTIVE_LOW>; + }; + + led-1 { + /* green:wan1-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <1>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 24 GPIO_ACTIVE_LOW>; + }; + + led-2 { + /* green:wan2-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <2>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 27 GPIO_ACTIVE_LOW>; + }; + + led-3 { + /* green:wan2-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <3>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 26 GPIO_ACTIVE_LOW>; + }; + + led-4 { + /* amber:power */ + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_AMBER>; + gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-5 { + /* white:status */ + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_WHITE>; + gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>; + }; + }; + + mdio-mii-mux { + compatible = "mdio-mux-mmioreg"; + reg = <0x1803f1c0 0x4>; + mux-mask = <0x2000>; + mdio-parent-bus = <&mdio_ext>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + phy_port6: phy@0 { + reg = <0>; + }; + + phy_port7: phy@1 { + reg = <1>; + }; + + phy_port8: phy@2 { + reg = <2>; + }; + + phy_port9: phy@3 { + reg = <3>; + }; + + phy_port10: phy@4 { + reg = <4>; + }; + + switch@10 { + compatible = "qca,qca8337"; + reg = <0x10>; + dsa,member = <1 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + ethernet = <&sgmii1>; + phy-mode = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan8"; + phy-handle = <&phy_port6>; + }; + + port@2 { + reg = <2>; + label = "lan9"; + phy-handle = <&phy_port7>; + }; + + port@3 { + reg = <3>; + label = "lan10"; + phy-handle = <&phy_port8>; + }; + + port@4 { + reg = <4>; + label = "lan11"; + phy-handle = <&phy_port9>; + }; + + port@5 { + reg = <5>; + label = "lan12"; + phy-handle = <&phy_port10>; + }; + }; + }; + }; + + mdio-mii@2000 { + reg = <0x2000>; + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + + switch@10 { + compatible = "qca,qca8337"; + reg = <0x10>; + dsa,member = <2 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + ethernet = <&sgmii0>; + phy-mode = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan3"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan4"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan5"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan6"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "lan7"; + phy-handle = <&phy_port5>; + }; + }; + }; + }; + }; +}; + +&srab { + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; + status = "okay"; + dsa,member = <0 0>; + + ports { + port@0 { + label = "wan1"; + reg = <0>; + }; + + port@1 { + label = "wan2"; + reg = <1>; + }; + + sgmii0: port@4 { + label = "sw0"; + reg = <4>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + sgmii1: port@5 { + label = "sw1"; + reg = <5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@8 { + ethernet = <&amac2>; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65.dts b/arch/arm/boot/dts/bcm958625-meraki-mx65.dts new file mode 100644 index 000000000000..d1b684dcdbfa --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx65.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX65. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-alamo.dtsi" + +/ { + model = "Cisco Meraki MX65"; + compatible = "meraki,mx65", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts new file mode 100644 index 000000000000..a2165aba3676 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX65W. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-alamo.dtsi" + +/ { + model = "Cisco Meraki MX65W"; + compatible = "meraki,mx65w", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; -- 2.26.3
MX65 & MX65W Hardware info: - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) - Storage: 1 GB (Micron MT29F8G08ABACA) - Networking: BCM58625 switch (2x 1GbE ports) 2x Qualcomm QCA8337 switches (10x 1GbE ports total) - PSE: Broadcom BCM59111KMLG connected to LAN ports 11 & 12 - USB: 1x USB2.0 - Serial: Internal header - WLAN(MX65W Only): 2x Broadcom BCM43520KMLG on the PCI bus. Note that a driver and firmware image for the BCM59111 PSE has been released under GPL, but this is not present in the kernel. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 279 ++++++++++++++++++ arch/arm/boot/dts/bcm958625-meraki-mx65.dts | 24 ++ arch/arm/boot/dts/bcm958625-meraki-mx65w.dts | 32 ++ 4 files changed, 337 insertions(+) create mode 100644 arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65w.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 17f7bdab50ef..3586b540e3b6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -159,6 +159,8 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \ bcm958625-meraki-mx64-a0.dtb \ bcm958625-meraki-mx64w.dtb \ bcm958625-meraki-mx64w-a0.dtb \ + bcm958625-meraki-mx65.dtb \ + bcm958625-meraki-mx65w.dtb \ bcm958625hr.dtb \ bcm988312hr.dtb \ bcm958625k.dtb diff --git a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi new file mode 100644 index 000000000000..8860f2fefc63 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX65 series (Alamo). + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +#include "bcm958625-meraki-mx6x-common.dtsi" + +/ { + keys { + compatible = "gpio-keys-polled"; + autorepeat; + poll-interval = <20>; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpioa 8 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + /* green:wan1-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <0>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 25 GPIO_ACTIVE_LOW>; + }; + + led-1 { + /* green:wan1-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <1>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 24 GPIO_ACTIVE_LOW>; + }; + + led-2 { + /* green:wan2-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <2>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 27 GPIO_ACTIVE_LOW>; + }; + + led-3 { + /* green:wan2-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <3>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 26 GPIO_ACTIVE_LOW>; + }; + + led-4 { + /* amber:power */ + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_AMBER>; + gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-5 { + /* white:status */ + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_WHITE>; + gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>; + }; + }; + + mdio-mii-mux { + compatible = "mdio-mux-mmioreg"; + reg = <0x1803f1c0 0x4>; + mux-mask = <0x2000>; + mdio-parent-bus = <&mdio_ext>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + phy_port6: phy@0 { + reg = <0>; + }; + + phy_port7: phy@1 { + reg = <1>; + }; + + phy_port8: phy@2 { + reg = <2>; + }; + + phy_port9: phy@3 { + reg = <3>; + }; + + phy_port10: phy@4 { + reg = <4>; + }; + + switch@10 { + compatible = "qca,qca8337"; + reg = <0x10>; + dsa,member = <1 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + ethernet = <&sgmii1>; + phy-mode = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan8"; + phy-handle = <&phy_port6>; + }; + + port@2 { + reg = <2>; + label = "lan9"; + phy-handle = <&phy_port7>; + }; + + port@3 { + reg = <3>; + label = "lan10"; + phy-handle = <&phy_port8>; + }; + + port@4 { + reg = <4>; + label = "lan11"; + phy-handle = <&phy_port9>; + }; + + port@5 { + reg = <5>; + label = "lan12"; + phy-handle = <&phy_port10>; + }; + }; + }; + }; + + mdio-mii@2000 { + reg = <0x2000>; + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + + switch@10 { + compatible = "qca,qca8337"; + reg = <0x10>; + dsa,member = <2 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + ethernet = <&sgmii0>; + phy-mode = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan3"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan4"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan5"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan6"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "lan7"; + phy-handle = <&phy_port5>; + }; + }; + }; + }; + }; +}; + +&srab { + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; + status = "okay"; + dsa,member = <0 0>; + + ports { + port@0 { + label = "wan1"; + reg = <0>; + }; + + port@1 { + label = "wan2"; + reg = <1>; + }; + + sgmii0: port@4 { + label = "sw0"; + reg = <4>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + sgmii1: port@5 { + label = "sw1"; + reg = <5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@8 { + ethernet = <&amac2>; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65.dts b/arch/arm/boot/dts/bcm958625-meraki-mx65.dts new file mode 100644 index 000000000000..d1b684dcdbfa --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx65.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX65. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-alamo.dtsi" + +/ { + model = "Cisco Meraki MX65"; + compatible = "meraki,mx65", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts new file mode 100644 index 000000000000..a2165aba3676 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX65W. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-alamo.dtsi" + +/ { + model = "Cisco Meraki MX65W"; + compatible = "meraki,mx65w", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; -- 2.26.3
MX65 & MX65W Hardware info: - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) - Storage: 1 GB (Micron MT29F8G08ABACA) - Networking: BCM58625 switch (2x 1GbE ports) 2x Qualcomm QCA8337 switches (10x 1GbE ports total) - PSE: Broadcom BCM59111KMLG connected to LAN ports 11 & 12 - USB: 1x USB2.0 - Serial: Internal header - WLAN(MX65W Only): 2x Broadcom BCM43520KMLG on the PCI bus. Note that a driver and firmware image for the BCM59111 PSE has been released under GPL, but this is not present in the kernel. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 279 ++++++++++++++++++ arch/arm/boot/dts/bcm958625-meraki-mx65.dts | 24 ++ arch/arm/boot/dts/bcm958625-meraki-mx65w.dts | 32 ++ 4 files changed, 337 insertions(+) create mode 100644 arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65w.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 17f7bdab50ef..3586b540e3b6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -159,6 +159,8 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \ bcm958625-meraki-mx64-a0.dtb \ bcm958625-meraki-mx64w.dtb \ bcm958625-meraki-mx64w-a0.dtb \ + bcm958625-meraki-mx65.dtb \ + bcm958625-meraki-mx65w.dtb \ bcm958625hr.dtb \ bcm988312hr.dtb \ bcm958625k.dtb diff --git a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi new file mode 100644 index 000000000000..8860f2fefc63 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX65 series (Alamo). + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +#include "bcm958625-meraki-mx6x-common.dtsi" + +/ { + keys { + compatible = "gpio-keys-polled"; + autorepeat; + poll-interval = <20>; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpioa 8 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + /* green:wan1-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <0>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 25 GPIO_ACTIVE_LOW>; + }; + + led-1 { + /* green:wan1-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <1>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 24 GPIO_ACTIVE_LOW>; + }; + + led-2 { + /* green:wan2-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <2>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 27 GPIO_ACTIVE_LOW>; + }; + + led-3 { + /* green:wan2-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <3>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioa 26 GPIO_ACTIVE_LOW>; + }; + + led-4 { + /* amber:power */ + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_AMBER>; + gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-5 { + /* white:status */ + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_WHITE>; + gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>; + }; + }; + + mdio-mii-mux { + compatible = "mdio-mux-mmioreg"; + reg = <0x1803f1c0 0x4>; + mux-mask = <0x2000>; + mdio-parent-bus = <&mdio_ext>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + phy_port6: phy@0 { + reg = <0>; + }; + + phy_port7: phy@1 { + reg = <1>; + }; + + phy_port8: phy@2 { + reg = <2>; + }; + + phy_port9: phy@3 { + reg = <3>; + }; + + phy_port10: phy@4 { + reg = <4>; + }; + + switch@10 { + compatible = "qca,qca8337"; + reg = <0x10>; + dsa,member = <1 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + ethernet = <&sgmii1>; + phy-mode = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan8"; + phy-handle = <&phy_port6>; + }; + + port@2 { + reg = <2>; + label = "lan9"; + phy-handle = <&phy_port7>; + }; + + port@3 { + reg = <3>; + label = "lan10"; + phy-handle = <&phy_port8>; + }; + + port@4 { + reg = <4>; + label = "lan11"; + phy-handle = <&phy_port9>; + }; + + port@5 { + reg = <5>; + label = "lan12"; + phy-handle = <&phy_port10>; + }; + }; + }; + }; + + mdio-mii@2000 { + reg = <0x2000>; + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + + switch@10 { + compatible = "qca,qca8337"; + reg = <0x10>; + dsa,member = <2 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + ethernet = <&sgmii0>; + phy-mode = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan3"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan4"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan5"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan6"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "lan7"; + phy-handle = <&phy_port5>; + }; + }; + }; + }; + }; +}; + +&srab { + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; + status = "okay"; + dsa,member = <0 0>; + + ports { + port@0 { + label = "wan1"; + reg = <0>; + }; + + port@1 { + label = "wan2"; + reg = <1>; + }; + + sgmii0: port@4 { + label = "sw0"; + reg = <4>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + sgmii1: port@5 { + label = "sw1"; + reg = <5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@8 { + ethernet = <&amac2>; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65.dts b/arch/arm/boot/dts/bcm958625-meraki-mx65.dts new file mode 100644 index 000000000000..d1b684dcdbfa --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx65.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX65. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-alamo.dtsi" + +/ { + model = "Cisco Meraki MX65"; + compatible = "meraki,mx65", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts new file mode 100644 index 000000000000..a2165aba3676 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX65W. + * + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com> + */ + +/dts-v1/; + +#include "bcm958625-meraki-alamo.dtsi" + +/ { + model = "Cisco Meraki MX65W"; + compatible = "meraki,mx65w", "brcm,bcm58625", "brcm,nsp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; -- 2.26.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Add bindings for the Meraki MX64/MX65 series. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Acked-by: Rob Herring <robh@kernel.org> --- Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml index 78dfa315f3d0..7d184ba7d180 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml @@ -62,6 +62,12 @@ properties: - enum: - brcm,bcm958625hr - brcm,bcm958625k + - meraki,mx64 + - meraki,mx64-a0 + - meraki,mx64w + - meraki,mx64w-a0 + - meraki,mx65 + - meraki,mx65w - const: brcm,bcm58625 - const: brcm,nsp -- 2.26.3
Add bindings for the Meraki MX64/MX65 series. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Acked-by: Rob Herring <robh@kernel.org> --- Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml index 78dfa315f3d0..7d184ba7d180 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml @@ -62,6 +62,12 @@ properties: - enum: - brcm,bcm958625hr - brcm,bcm958625k + - meraki,mx64 + - meraki,mx64-a0 + - meraki,mx64w + - meraki,mx64w-a0 + - meraki,mx65 + - meraki,mx65w - const: brcm,bcm58625 - const: brcm,nsp -- 2.26.3
Add bindings for the Meraki MX64/MX65 series. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Acked-by: Rob Herring <robh@kernel.org> --- Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml index 78dfa315f3d0..7d184ba7d180 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml @@ -62,6 +62,12 @@ properties: - enum: - brcm,bcm958625hr - brcm,bcm958625k + - meraki,mx64 + - meraki,mx64-a0 + - meraki,mx64w + - meraki,mx64w-a0 + - meraki,mx65 + - meraki,mx65w - const: brcm,bcm58625 - const: brcm,nsp -- 2.26.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Fri, 6 Aug 2021 21:44:32 +0100, Matthew Hagan <mnhagan88@gmail.com> wrote: > These bindings are required for all Meraki MX64/MX65 devices. These > common bindings include memory (2GB), PWM LEDs, AMAC, I2C (AT24), NAND > partitions, EHCI, OHCI and pinctrl. > > Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> > --- Applied to https://github.com/Broadcom/stblinux/commits/master, thanks! -- Florian _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Fri, 6 Aug 2021 21:44:33 +0100, Matthew Hagan <mnhagan88@gmail.com> wrote: > While uncommon, some Ax NSP SoCs exist in the wild. This stepping > requires a modified secondary CPU boot-reg and removal of DMA coherency > properties. Without these modifications, the secondary CPU will be > inactive and many peripherals will exhibit undefined behaviour. > > Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> > --- Applied to https://github.com/Broadcom/stblinux/commits/master, thanks! -- Florian _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Fri, 6 Aug 2021 21:44:34 +0100, Matthew Hagan <mnhagan88@gmail.com> wrote: > MX64 & MX64W Hardware info: > - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz > - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) > - Storage: 1 GB (Micron MT29F8G08ABACA) > - Networking: BCM58625 internal switch (5x 1GbE ports) > - USB: 1x USB2.0 > - Serial: Internal header > - WLAN(MX64W only): 2x Broadcom BCM43520KMLG on the PCI bus > > This patch adds the Meraki MX64 series-specific bindings. Since some > devices make use of the older A0 SoC, changes need to be made to > accommodate this case, including removal of coherency options and > modification to the secondary-boot-reg. > > Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> > --- Applied to https://github.com/Broadcom/stblinux/commits/master, thanks! -- Florian _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Fri, 6 Aug 2021 21:44:35 +0100, Matthew Hagan <mnhagan88@gmail.com> wrote: > MX65 & MX65W Hardware info: > - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz > - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) > - Storage: 1 GB (Micron MT29F8G08ABACA) > - Networking: BCM58625 switch (2x 1GbE ports) > 2x Qualcomm QCA8337 switches (10x 1GbE ports total) > - PSE: Broadcom BCM59111KMLG connected to LAN ports 11 & 12 > - USB: 1x USB2.0 > - Serial: Internal header > - WLAN(MX65W Only): 2x Broadcom BCM43520KMLG on the PCI bus. > > Note that a driver and firmware image for the BCM59111 PSE has been > released under GPL, but this is not present in the kernel. > > Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> > --- Applied to https://github.com/Broadcom/stblinux/commits/master, thanks! -- Florian _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Fri, 6 Aug 2021 21:44:36 +0100, Matthew Hagan <mnhagan88@gmail.com> wrote: > Add bindings for the Meraki MX64/MX65 series. > > Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> > Acked-by: Rob Herring <robh@kernel.org> > --- Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks! -- Florian _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On 8/6/2021 10:44 PM, Matthew Hagan wrote: > Changes from v2: > - Introduce boards to Makefile in same patch as the board dts is added > (Vladimir Oltean) > - Use alphabetical ordering for labels (Vladimir Oltean) > - Remove address-cells and size-cells in qca8337 switch nodes (Vladimir > Oltean) > - Remove "cpu" labels from switch nodes' CPU ports (Vladimir Oltean) > - Various LED fixes, utilising dt-bindings/leds/common.h and correctly > specifying LEDs in the form "led-N" and with the color/function/ > function-enumerator properties. > - Fix PWM LEDs and corresponding pinctrl bindings. (Vladimir Oltean) > > The following changes were submitted as a separate series: > - Introduce patches to disable QSPI by default and enable where used > (Vladimir Oltean) > - Move mdio@18032000 node from board related file to SoC (Vladimir > Oltean) > - In addition to above, relocate mdio-mux to bcm-nsp.dtsi and fix > the resulting usb3_phy issues > > Changes from v3: > - Sort labels on mx64 a0 dts files into alphabetical order as well > - move include directives for input/input.h and leds/common.h to > bcm958625-mx6x-common.dtsi > - Whitespace fixes in bcm958625-mx6x-common.dtsi > - rename "senao_nvram" partition to "nvram" > > Changes from v4: > - Move chosen and memory nodes from bcm958625-mx6x-common.dtsi to > each .dts file (Arnd Bergmann). > - Append [@<unit-address>] to memory nodes. > - Create Ax stepping-specific dtsi for Ax devices (Arnd Bergmann). > - Append read-only property to at24 eeprom node. > - Remove L2 properties which should be defined at platform-level. > - Correct NAND node names. I applied patch 1 first such that we don't get warnings when we apply patches from there on during bisection builds. -- Florian _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel