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From: Andrej Picej <andrej.picej@norik.com>
To: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	soc@kernel.org, kernel@pengutronix.de, shawnguo@kernel.org,
	leoyang.li@nxp.com, krzysztof.kozlowski@canonical.com,
	linux@rempel-privat.de, festevam@gmail.com, arnd@arndb.de,
	linux-imx@nxp.com, y.bas@phytec.de
Subject: Re: [PATCH 1/4] dt-bindings: arm: fsl: add PHYTEC phyGATE Tauri i.MX6 ULL
Date: Thu, 16 Dec 2021 09:45:17 +0100	[thread overview]
Message-ID: <698c247b-ba61-765b-9572-9181d1e141b8@norik.com> (raw)
In-Reply-To: <Ybeb5I/mP3JFrDsQ@robh.at.kernel.org>

Hi Rob,

On 13. 12. 21 20:15, Rob Herring wrote:
> On Wed, Dec 01, 2021 at 01:53:24PM +0100, Andrej Picej wrote:
>> Add devicetree bindings for phyGATE Tauri board with phyCORE-i.MX6 ULL.
>>
>> Signed-off-by: Andrej Picej <andrej.picej@norik.com>
>> ---
>>   Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
>> index 0b595b26061f..9c37f22b6c61 100644
>> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
>> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
>> @@ -602,6 +602,15 @@ properties:
>>             - const: phytec,imx6ull-pcl063  # PHYTEC phyCORE-i.MX 6ULL
>>             - const: fsl,imx6ull
>>   
>> +      - description: i.MX6ULL PHYTEC phyGATE-Tauri
>> +        items:
>> +          - enum:
>> +              - phytec,imx6ull-phygate-tauri-emmc
>> +              - phytec,imx6ull-phygate-tauri-nand
>> +          - const: phytec,imx6ull-phygate-tauri # PHYTEC phyGATE-Tauri with i.MX6 ULL
> 
> Is there really a need for 2 compatibles here? Either
> phytec,imx6ull-phygate-tauri is specific enough (as nand/emmc can be
> described elsewhere) or you need
> phytec,imx6ull-phygate-tauri-emmc/phytec,imx6ull-phygate-tauri-nand.

sorry for late reply. Yes, I think we need both. We have two board types 
for Tauri, one with eMMC and the other with NAND. Depending on this the 
NAND or eMMC gets enabled. The same logic is already used with other 
PHYTEC boards (e.g. Segin and Mira). Or did you had something other in mind?
> 
> 
>> +          - const: phytec,imx6ull-pcl063        # PHYTEC phyCORE-i.MX 6ULL
>> +          - const: fsl,imx6ull
>> +
>>         - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules
>>           items:
>>             - enum:
>> -- 
>> 2.25.1
>>
>>

  reply	other threads:[~2021-12-16  8:45 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-01 12:53 [PATCH 0/4] PHYTEC i.MX 6UL/ULL devicetree patches Andrej Picej
2021-12-01 12:53 ` [PATCH 1/4] dt-bindings: arm: fsl: add PHYTEC phyGATE Tauri i.MX6 ULL Andrej Picej
2021-12-13 19:15   ` Rob Herring
2021-12-16  8:45     ` Andrej Picej [this message]
2021-12-01 12:53 ` [PATCH 2/4] ARM: dts: imx6ull: Add support for PHYTEC phyGATE-Tauri-S with i.MX 6ULL Andrej Picej
2021-12-01 12:53 ` [PATCH 3/4] ARM: dts: imx6ul: phycore: Change USB LDO voltage for usb compliance Andrej Picej
2021-12-01 12:53 ` [PATCH 4/4] ARM: dts: imx6ul: peb-av-02: move to 3 cell pwm Andrej Picej
2021-12-13 16:13 ` [PATCH 0/4] PHYTEC i.MX 6UL/ULL devicetree patches Arnd Bergmann
2021-12-16  7:13   ` Andrej Picej

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