* [PATCH 00/11] Add STM32MP25 support
@ 2023-05-29 16:20 Alexandre Torgue
2023-05-29 16:20 ` [PATCH 01/11] dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages Alexandre Torgue
` (11 more replies)
0 siblings, 12 replies; 28+ messages in thread
From: Alexandre Torgue @ 2023-05-29 16:20 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc
Cc: linux-arm-kernel, devicetree, Alexandre Torgue, linux-stm32,
linux-kernel, linux-gpio
I'm pleased to announce extension of the STM32 MPU family with the addition of
the STM32MP25 Armv8 based SoCs.
STM32MP25 family is composed of 4 SoCs defined as following:
-STM32MP251: common part composed of 1*Cortex-A35, common peripherals like
SDMMC, UART, SPI, I2C, PCIe, USB3, parallel and DSI display, 1*ETH ...
-STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD and
LVDS display.
-STM32MP255: STM32MP253 + GPU/AI and video encode/decode.
-STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports).
A second diversity layer exists for security features/ A35 frequency:
-STM32MP25xY, "Y" gives information:
-Y = A means A35@1.2GHz + no cryp IP and no secure boot.
-Y = C means A35@1.2GHz + cryp IP and secure boot.
-Y = D means A35@1.5GHz + no cryp IP and no secure boot.
-Y = F means A35@1.5GHz + cryp IP and secure boot.
This series adds the STM32MP257F EV1 board support. This board embeds a
STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA,
1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...
Thanks
Alex
Alexandre Torgue (10):
dt-bindings: pinctrl: stm32: support for stm32mp257 and additional
packages
pinctrl: stm32: add stm32mp257 pinctrl support
dt-bindings: stm32: add st,stm32mp25 compatibles to the stm32 family
arm64: introduce STM32 family on Armv8 architecture
arm64: dts: st: introduce stm32mp25 SoCs family
arm64: dts: st: introduce stm32mp25 pinctrl files
dt-bindings: stm32: document stm32mp257f-ev1 board
arm64: dts: st: add stm32mp257f-ev1 board support
arm64: defconfig: enable ARCH_STM32 and STM32 serial driver
MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE
Patrick Delaunay (1):
dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon
.../bindings/arm/stm32/st,stm32-syscon.yaml | 1 +
.../devicetree/bindings/arm/stm32/stm32.yaml | 12 +
.../bindings/pinctrl/st,stm32-pinctrl.yaml | 4 +-
MAINTAINERS | 1 +
arch/arm64/Kconfig.platforms | 14 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/st/Makefile | 2 +
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 38 +
arch/arm64/boot/dts/st/stm32mp251.dtsi | 279 ++
arch/arm64/boot/dts/st/stm32mp253.dtsi | 23 +
arch/arm64/boot/dts/st/stm32mp255.dtsi | 9 +
arch/arm64/boot/dts/st/stm32mp257.dtsi | 9 +
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 50 +
arch/arm64/boot/dts/st/stm32mp25xc.dtsi | 8 +
arch/arm64/boot/dts/st/stm32mp25xf.dtsi | 8 +
.../boot/dts/st/stm32mp25xxai-pinctrl.dtsi | 83 +
.../boot/dts/st/stm32mp25xxak-pinctrl.dtsi | 71 +
.../boot/dts/st/stm32mp25xxal-pinctrl.dtsi | 71 +
arch/arm64/configs/defconfig | 3 +
drivers/pinctrl/stm32/Kconfig | 6 +
drivers/pinctrl/stm32/Makefile | 1 +
drivers/pinctrl/stm32/pinctrl-stm32.h | 3 +
drivers/pinctrl/stm32/pinctrl-stm32mp257.c | 2581 +++++++++++++++++
include/dt-bindings/pinctrl/stm32-pinfunc.h | 3 +
24 files changed, 3280 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/st/Makefile
create mode 100644 arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp251.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp253.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp255.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp257.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
create mode 100644 arch/arm64/boot/dts/st/stm32mp25xc.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp25xf.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi
create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32mp257.c
--
2.17.1
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 01/11] dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages
2023-05-29 16:20 [PATCH 00/11] Add STM32MP25 support Alexandre Torgue
@ 2023-05-29 16:20 ` Alexandre Torgue
2023-05-29 18:00 ` Conor Dooley
2023-05-29 16:20 ` [PATCH 02/11] pinctrl: stm32: add stm32mp257 pinctrl support Alexandre Torgue
` (10 subsequent siblings)
11 siblings, 1 reply; 28+ messages in thread
From: Alexandre Torgue @ 2023-05-29 16:20 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc
Cc: linux-arm-kernel, devicetree, Alexandre Torgue, linux-stm32,
linux-kernel, linux-gpio
Add support for st,stm32mp257-pinctrl and st,stm32mp257-z-pinctrl.
Add packages AI, AK and AL (values : 0x100, 0x400 and 0x800)
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
index 1ab0f8dde477..2120ef71a78d 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
@@ -27,6 +27,8 @@ properties:
- st,stm32mp135-pinctrl
- st,stm32mp157-pinctrl
- st,stm32mp157-z-pinctrl
+ - st,stm32mp257-pinctrl
+ - st,stm32mp257-z-pinctrl
'#address-cells':
const: 1
@@ -56,7 +58,7 @@ properties:
Indicates the SOC package used.
More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
$ref: /schemas/types.yaml#/definitions/uint32
- enum: [1, 2, 4, 8]
+ enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800]
patternProperties:
'^gpio@[0-9a-f]*$':
diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h
index e6fb8ada3f4d..28ad0235086a 100644
--- a/include/dt-bindings/pinctrl/stm32-pinfunc.h
+++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h
@@ -37,6 +37,9 @@
#define STM32MP_PKG_AB 0x2
#define STM32MP_PKG_AC 0x4
#define STM32MP_PKG_AD 0x8
+#define STM32MP_PKG_AI 0x100
+#define STM32MP_PKG_AK 0x400
+#define STM32MP_PKG_AL 0x800
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 02/11] pinctrl: stm32: add stm32mp257 pinctrl support
2023-05-29 16:20 [PATCH 00/11] Add STM32MP25 support Alexandre Torgue
2023-05-29 16:20 ` [PATCH 01/11] dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages Alexandre Torgue
@ 2023-05-29 16:20 ` Alexandre Torgue
2023-05-29 18:04 ` Conor Dooley
2023-05-29 16:20 ` [PATCH 03/11] dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon Alexandre Torgue
` (9 subsequent siblings)
11 siblings, 1 reply; 28+ messages in thread
From: Alexandre Torgue @ 2023-05-29 16:20 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc
Cc: linux-arm-kernel, devicetree, Alexandre Torgue, linux-stm32,
linux-kernel, linux-gpio
Add stm32mp257 pinctrl support.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
index d532f3c6f670..2656d3d3ae40 100644
--- a/drivers/pinctrl/stm32/Kconfig
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -51,4 +51,10 @@ config PINCTRL_STM32MP157
depends on OF && HAS_IOMEM
default MACH_STM32MP157
select PINCTRL_STM32
+
+config PINCTRL_STM32MP257
+ bool "STMicroelectronics STM32MP257 pin control" if COMPILE_TEST && !MACH_STM32MP25
+ depends on OF && HAS_IOMEM
+ default MACH_STM32MP25
+ select PINCTRL_STM32
endif
diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile
index 619629ee9944..7b17464d8de1 100644
--- a/drivers/pinctrl/stm32/Makefile
+++ b/drivers/pinctrl/stm32/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_STM32F769) += pinctrl-stm32f769.o
obj-$(CONFIG_PINCTRL_STM32H743) += pinctrl-stm32h743.o
obj-$(CONFIG_PINCTRL_STM32MP135) += pinctrl-stm32mp135.o
obj-$(CONFIG_PINCTRL_STM32MP157) += pinctrl-stm32mp157.o
+obj-$(CONFIG_PINCTRL_STM32MP257) += pinctrl-stm32mp257.o
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h
index e0c31c4c8bca..5e5de92ddd58 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.h
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.h
@@ -24,6 +24,9 @@
#define STM32MP_PKG_AB BIT(1)
#define STM32MP_PKG_AC BIT(2)
#define STM32MP_PKG_AD BIT(3)
+#define STM32MP_PKG_AI BIT(8)
+#define STM32MP_PKG_AK BIT(10)
+#define STM32MP_PKG_AL BIT(11)
struct stm32_desc_function {
const char *name;
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32mp257.c b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c
new file mode 100644
index 000000000000..73f091cd827e
--- /dev/null
+++ b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c
@@ -0,0 +1,2581 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-stm32.h"
+
+static const struct stm32_desc_pin stm32mp257_pins[] = {
+ STM32_PIN_PKG(
+ PINCTRL_PIN(0, "PA0"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOA0"),
+ STM32_FUNCTION(2, "LPTIM1_CH2"),
+ STM32_FUNCTION(3, "SPI5_RDY"),
+ STM32_FUNCTION(4, "UART8_CTS"),
+ STM32_FUNCTION(5, "SAI2_MCLK_B"),
+ STM32_FUNCTION(6, "UART5_TX"),
+ STM32_FUNCTION(7, "USART3_TX"),
+ STM32_FUNCTION(8, "TIM3_ETR"),
+ STM32_FUNCTION(9, "TIM5_CH2"),
+ STM32_FUNCTION(11, "ETH2_MII_RXD2 ETH2_RGMII_RXD2"),
+ STM32_FUNCTION(13, "FMC_NL"),
+ STM32_FUNCTION(15, "DCMI_D9 PSSI_D9 DCMIPP_D9"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(1, "PA1"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOA1"),
+ STM32_FUNCTION(3, "SPI6_MISO"),
+ STM32_FUNCTION(5, "SAI3_SD_A"),
+ STM32_FUNCTION(6, "USART1_RTS"),
+ STM32_FUNCTION(7, "USART6_CK"),
+ STM32_FUNCTION(8, "TIM4_CH2"),
+ STM32_FUNCTION(9, "I2C4_SDA"),
+ STM32_FUNCTION(10, "I2C6_SDA"),
+ STM32_FUNCTION(12, "LCD_R3"),
+ STM32_FUNCTION(14, "DCMI_D5 PSSI_D5 DCMIPP_D5"),
+ STM32_FUNCTION(15, "ETH3_PHY_INTN"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(2, "PA2"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOA2"),
+ STM32_FUNCTION(2, "LPTIM2_IN1"),
+ STM32_FUNCTION(3, "SPI7_MISO"),
+ STM32_FUNCTION(6, "MDF1_SDI7"),
+ STM32_FUNCTION(7, "USART1_RX"),
+ STM32_FUNCTION(9, "I3C1_SDA"),
+ STM32_FUNCTION(11, "I2C1_SDA"),
+ STM32_FUNCTION(12, "LCD_B0"),
+ STM32_FUNCTION(14, "DCMI_D3 PSSI_D3 DCMIPP_D3"),
+ STM32_FUNCTION(15, "ETH3_RGMII_RX_CTL ETH3_RMII_CRS_DV"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(3, "PA3"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOA3"),
+ STM32_FUNCTION(2, "LPTIM2_ETR"),
+ STM32_FUNCTION(3, "SPI7_MOSI"),
+ STM32_FUNCTION(6, "MDF1_CKI7"),
+ STM32_FUNCTION(7, "USART1_TX"),
+ STM32_FUNCTION(9, "I3C1_SCL"),
+ STM32_FUNCTION(10, "I2C7_SMBA"),
+ STM32_FUNCTION(11, "I2C1_SCL"),
+ STM32_FUNCTION(12, "LCD_B1"),
+ STM32_FUNCTION(14, "DCMI_D2 PSSI_D2 DCMIPP_D2"),
+ STM32_FUNCTION(15, "ETH3_RGMII_TX_CTL ETH3_RMII_TX_EN"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(4, "PA4"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOA4"),
+ STM32_FUNCTION(7, "USART2_TX"),
+ STM32_FUNCTION(8, "FDCAN2_TX"),
+ STM32_FUNCTION(9, "TIM2_CH1"),
+ STM32_FUNCTION(11, "LCD_R1"),
+ STM32_FUNCTION(14, "ETH1_PTP_AUX_TS"),
+ STM32_FUNCTION(15, "ETH3_PPS_OUT"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(5, "PA5"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOA5"),
+ STM32_FUNCTION(4, "SPI4_MOSI"),
+ STM32_FUNCTION(5, "SAI2_MCLK_B"),
+ STM32_FUNCTION(6, "SAI2_SD_B"),
+ STM32_FUNCTION(7, "USART2_RTS"),
+ STM32_FUNCTION(8, "FDCAN2_RX"),
+ STM32_FUNCTION(9, "TIM2_CH4"),
+ STM32_FUNCTION(11, "LCD_G0"),
+ STM32_FUNCTION(13, "FMC_A0"),
+ STM32_FUNCTION(14, "DCMI_D13 PSSI_D13 DCMIPP_D13"),
+ STM32_FUNCTION(15, "ETH3_RGMII_RX_CLK ETH3_RMII_REF_CLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(6, "PA6"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOA6"),
+ STM32_FUNCTION(4, "SPI4_SCK"),
+ STM32_FUNCTION(5, "SAI2_FS_B"),
+ STM32_FUNCTION(6, "MDF1_SDI6"),
+ STM32_FUNCTION(7, "USART2_CK"),
+ STM32_FUNCTION(8, "TIM13_CH1"),
+ STM32_FUNCTION(9, "TIM2_ETR"),
+ STM32_FUNCTION(11, "LCD_G4"),
+ STM32_FUNCTION(13, "FMC_NE1"),
+ STM32_FUNCTION(14, "DCMI_D12 PSSI_D12 DCMIPP_D12"),
+ STM32_FUNCTION(15, "ETH3_RGMII_TXD0 ETH3_RMII_TXD0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(7, "PA7"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOA7"),
+ STM32_FUNCTION(3, "AUDIOCLK"),
+ STM32_FUNCTION(4, "SPI6_RDY"),
+ STM32_FUNCTION(5, "PCIE_CLKREQN"),
+ STM32_FUNCTION(6, "MDF1_CCK0"),
+ STM32_FUNCTION(7, "USART1_CTS"),
+ STM32_FUNCTION(8, "TIM4_ETR"),
+ STM32_FUNCTION(9, "I2C2_SMBA"),
+ STM32_FUNCTION(10, "I2C6_SMBA"),
+ STM32_FUNCTION(11, "LCD_B5"),
+ STM32_FUNCTION(12, "I2C3_SMBA"),
+ STM32_FUNCTION(13, "I2C4_SMBA"),
+ STM32_FUNCTION(14, "DCMI_D6 PSSI_D6 DCMIPP_D6"),
+ STM32_FUNCTION(15, "ETH3_RGMII_TXD1 ETH3_RMII_TXD1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(8, "PA8"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOA8"),
+ STM32_FUNCTION(2, "LPTIM2_CH2"),
+ STM32_FUNCTION(3, "SPI7_NSS"),
+ STM32_FUNCTION(5, "SAI1_FS_B"),
+ STM32_FUNCTION(7, "USART1_CK"),
+ STM32_FUNCTION(9, "USART2_RX"),
+ STM32_FUNCTION(10, "I2C5_SCL"),
+ STM32_FUNCTION(13, "LCD_B2"),
+ STM32_FUNCTION(14, "DCMI_D4 PSSI_D4 DCMIPP_D4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(9, "PA9"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOA9"),
+ STM32_FUNCTION(4, "SPI4_NSS"),
+ STM32_FUNCTION(5, "SAI2_SCK_B"),
+ STM32_FUNCTION(7, "USART2_CTS"),
+ STM32_FUNCTION(8, "LPTIM5_ETR"),
+ STM32_FUNCTION(9, "TIM2_CH3"),
+ STM32_FUNCTION(11, "ETH1_MDC"),
+ STM32_FUNCTION(13, "LCD_G7"),
+ STM32_FUNCTION(14, "PSSI_D14 DCMIPP_D14"),
+ STM32_FUNCTION(15, "ETH3_RGMII_RXD0 ETH3_RMII_RXD0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(10, "PA10"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOA10"),
+ STM32_FUNCTION(4, "SPI4_MISO"),
+ STM32_FUNCTION(5, "SAI2_SD_B"),
+ STM32_FUNCTION(7, "USART2_RX"),
+ STM32_FUNCTION(8, "LPTIM5_IN1"),
+ STM32_FUNCTION(9, "TIM2_CH2"),
+ STM32_FUNCTION(11, "ETH1_MDIO"),
+ STM32_FUNCTION(13, "LCD_R6"),
+ STM32_FUNCTION(14, "PSSI_D15 DCMIPP_D15"),
+ STM32_FUNCTION(15, "ETH3_RGMII_RXD1 ETH3_RMII_RXD1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(11, "PA11"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOA11"),
+ STM32_FUNCTION(2, "SPI8_SCK"),
+ STM32_FUNCTION(3, "LPTIM2_CH1"),
+ STM32_FUNCTION(5, "SAI4_SD_B"),
+ STM32_FUNCTION(6, "MDF1_SDI4"),
+ STM32_FUNCTION(11, "ETH1_MII_RX_DV ETH1_RGMII_RX_CTL ETH1_RMII_CRS_DV"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(12, "PA12"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOA12"),
+ STM32_FUNCTION(3, "SPI6_MOSI"),
+ STM32_FUNCTION(5, "SAI3_FS_A"),
+ STM32_FUNCTION(8, "TIM4_CH1"),
+ STM32_FUNCTION(9, "I2C4_SCL"),
+ STM32_FUNCTION(10, "I2C6_SCL"),
+ STM32_FUNCTION(11, "ETH1_PHY_INTN"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(13, "PA13"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOA13"),
+ STM32_FUNCTION(2, "SPI8_RDY"),
+ STM32_FUNCTION(3, "I2S3_MCK"),
+ STM32_FUNCTION(4, "LPTIM2_ETR"),
+ STM32_FUNCTION(6, "MDF1_CKI3"),
+ STM32_FUNCTION(7, "USART2_CTS"),
+ STM32_FUNCTION(10, "I2C7_SMBA"),
+ STM32_FUNCTION(11, "ETH1_MII_TX_EN ETH1_RGMII_TX_CTL ETH1_RMII_TX_EN"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(14, "PA14"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOA14"),
+ STM32_FUNCTION(2, "SPI8_NSS"),
+ STM32_FUNCTION(3, "LPTIM2_CH2"),
+ STM32_FUNCTION(5, "SAI4_FS_B"),
+ STM32_FUNCTION(6, "MDF1_CCK1"),
+ STM32_FUNCTION(11, "ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(15, "PA15"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOA15"),
+ STM32_FUNCTION(3, "SPI3_MISO I2S3_SDI"),
+ STM32_FUNCTION(7, "USART2_RX"),
+ STM32_FUNCTION(10, "I2C7_SDA"),
+ STM32_FUNCTION(11, "ETH1_MII_TXD0 ETH1_RGMII_TXD0 ETH1_RMII_TXD0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(16, "PB0"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOB0"),
+ STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(7, "USART1_CK"),
+ STM32_FUNCTION(8, "TIM16_CH1"),
+ STM32_FUNCTION(9, "TIM20_CH4N"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_IO0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(17, "PB1"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOB1"),
+ STM32_FUNCTION(2, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(8, "TIM16_CH1N"),
+ STM32_FUNCTION(9, "TIM20_CH3N"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_IO1"),
+ STM32_FUNCTION(13, "FMC_NCE4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(18, "PB2"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOB2"),
+ STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"),
+ STM32_FUNCTION(6, "MDF1_CKI3"),
+ STM32_FUNCTION(7, "TIM17_BKIN"),
+ STM32_FUNCTION(8, "TIM16_BKIN"),
+ STM32_FUNCTION(9, "TIM20_CH2N"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_IO2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(19, "PB3"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOB3"),
+ STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"),
+ STM32_FUNCTION(6, "MDF1_SDI3"),
+ STM32_FUNCTION(9, "TIM20_CH3"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_IO3"),
+ STM32_FUNCTION(13, "FMC_NCE3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(20, "PB4"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOB4"),
+ STM32_FUNCTION(3, "SPI2_RDY"),
+ STM32_FUNCTION(4, "UART4_CTS"),
+ STM32_FUNCTION(5, "SAI4_FS_B"),
+ STM32_FUNCTION(6, "MDF1_SDI4"),
+ STM32_FUNCTION(7, "TIM14_CH1"),
+ STM32_FUNCTION(9, "TIM20_CH2"),
+ STM32_FUNCTION(10, "I2C2_SDA"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_IO4"),
+ STM32_FUNCTION(14, "I3C2_SDA"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(21, "PB5"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOB5"),
+ STM32_FUNCTION(3, "I2S2_MCK"),
+ STM32_FUNCTION(4, "UART4_RTS"),
+ STM32_FUNCTION(5, "SAI4_SD_B"),
+ STM32_FUNCTION(6, "MDF1_CKI4"),
+ STM32_FUNCTION(9, "TIM20_CH1"),
+ STM32_FUNCTION(10, "I2C2_SCL"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_IO5"),
+ STM32_FUNCTION(13, "FMC_AD8 FMC_D8"),
+ STM32_FUNCTION(14, "I3C2_SCL"),
+ STM32_FUNCTION(15, "SDMMC3_D123DIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(22, "PB6"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOB6"),
+ STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"),
+ STM32_FUNCTION(4, "UART4_RX"),
+ STM32_FUNCTION(5, "SAI4_SCK_B"),
+ STM32_FUNCTION(9, "TIM20_CH1N"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_IO6"),
+ STM32_FUNCTION(13, "FMC_AD9 FMC_D9"),
+ STM32_FUNCTION(15, "SDMMC3_D0DIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(23, "PB7"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOB7"),
+ STM32_FUNCTION(2, "SPI3_SCK I2S3_CK"),
+ STM32_FUNCTION(4, "UART4_TX"),
+ STM32_FUNCTION(5, "SAI4_MCLK_B"),
+ STM32_FUNCTION(9, "TIM20_ETR"),
+ STM32_FUNCTION(10, "TIM12_CH1"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_IO7"),
+ STM32_FUNCTION(13, "FMC_AD10 FMC_D10"),
+ STM32_FUNCTION(15, "SDMMC3_CDIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(24, "PB8"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOB8"),
+ STM32_FUNCTION(2, "SPI3_MOSI I2S3_SDO"),
+ STM32_FUNCTION(5, "PCIE_CLKREQN"),
+ STM32_FUNCTION(7, "USART1_TX"),
+ STM32_FUNCTION(8, "TIM17_CH1"),
+ STM32_FUNCTION(9, "TIM20_CH4"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_NCS1"),
+ STM32_FUNCTION(13, "FMC_AD12 FMC_D12"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(25, "PB9"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOB9"),
+ STM32_FUNCTION(2, "SPI3_RDY"),
+ STM32_FUNCTION(7, "USART1_RTS"),
+ STM32_FUNCTION(8, "FDCAN1_TX"),
+ STM32_FUNCTION(9, "TIM20_BKIN"),
+ STM32_FUNCTION(10, "TIM10_CH1"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_DQS"),
+ STM32_FUNCTION(12, "OCTOSPIM_P2_NCS2"),
+ STM32_FUNCTION(13, "FMC_AD13 FMC_D13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(26, "PB10"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOB10"),
+ STM32_FUNCTION(2, "SPI3_MISO I2S3_SDI"),
+ STM32_FUNCTION(7, "USART1_RX"),
+ STM32_FUNCTION(8, "TIM17_CH1N"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_CLK"),
+ STM32_FUNCTION(13, "FMC_AD15 FMC_D15"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(27, "PB11"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOB11"),
+ STM32_FUNCTION(2, "I2S3_MCK"),
+ STM32_FUNCTION(7, "USART1_CTS"),
+ STM32_FUNCTION(8, "FDCAN1_RX"),
+ STM32_FUNCTION(9, "TIM20_BKIN2"),
+ STM32_FUNCTION(10, "TIM12_CH2"),
+ STM32_FUNCTION(11, "OCTOSPIM_P2_NCLK"),
+ STM32_FUNCTION(12, "OCTOSPIM_P2_NCS2"),
+ STM32_FUNCTION(13, "FMC_AD14 FMC_D14"),
+ STM32_FUNCTION(14, "OCTOSPIM_P1_NCS2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(28, "PB12"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOB12"),
+ STM32_FUNCTION(6, "UART8_CTS"),
+ STM32_FUNCTION(8, "TIM13_CH1"),
+ STM32_FUNCTION(10, "DSI_TE"),
+ STM32_FUNCTION(11, "SDMMC3_D2"),
+ STM32_FUNCTION(12, "FMC_NWAIT"),
+ STM32_FUNCTION(15, "DCMI_D12 PSSI_D12 DCMIPP_D12"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(29, "PB13"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOB13"),
+ STM32_FUNCTION(3, "SPI7_SCK"),
+ STM32_FUNCTION(5, "SAI1_SD_B"),
+ STM32_FUNCTION(6, "UART8_RX"),
+ STM32_FUNCTION(11, "SDMMC3_CK"),
+ STM32_FUNCTION(12, "FMC_AD5 FMC_D5"),
+ STM32_FUNCTION(13, "FMC_AD0 FMC_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(30, "PB14"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOB14"),
+ STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(6, "MDF1_CKI7"),
+ STM32_FUNCTION(7, "UART9_RX"),
+ STM32_FUNCTION(10, "TIM4_CH2"),
+ STM32_FUNCTION(11, "SDMMC3_D0"),
+ STM32_FUNCTION(12, "FMC_AD7 FMC_D7"),
+ STM32_FUNCTION(13, "FMC_AD2 FMC_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(31, "PB15"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOB15"),
+ STM32_FUNCTION(2, "LPTIM1_IN2"),
+ STM32_FUNCTION(3, "SPI5_SCK"),
+ STM32_FUNCTION(4, "UART8_RTS"),
+ STM32_FUNCTION(5, "SAI2_SD_B"),
+ STM32_FUNCTION(6, "UART5_RX"),
+ STM32_FUNCTION(8, "TIM3_CH2"),
+ STM32_FUNCTION(9, "TIM5_CH1"),
+ STM32_FUNCTION(11, "ETH1_PPS_OUT"),
+ STM32_FUNCTION(13, "FMC_A18"),
+ STM32_FUNCTION(14, "LCD_R4"),
+ STM32_FUNCTION(15, "DCMI_D8 PSSI_D8 DCMIPP_D8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(32, "PC0"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOC0"),
+ STM32_FUNCTION(2, "LPTIM1_CH1"),
+ STM32_FUNCTION(4, "SPI6_SCK"),
+ STM32_FUNCTION(5, "SAI3_MCLK_B"),
+ STM32_FUNCTION(6, "USART6_TX"),
+ STM32_FUNCTION(10, "DCMI_D0 PSSI_D0 DCMIPP_D0"),
+ STM32_FUNCTION(11, "ETH2_MII_RX_CLK ETH2_RGMII_RX_CLK ETH2_RMII_REF_CLK"),
+ STM32_FUNCTION(12, "ETH1_MII_TX_CLK"),
+ STM32_FUNCTION(13, "ETH1_RGMII_GTX_CLK"),
+ STM32_FUNCTION(14, "LCD_G7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(33, "PC1"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOC1"),
+ STM32_FUNCTION(3, "SPI3_MOSI I2S3_SDO"),
+ STM32_FUNCTION(7, "USART2_TX"),
+ STM32_FUNCTION(10, "I2C7_SCL"),
+ STM32_FUNCTION(11, "ETH1_MII_TXD1 ETH1_RGMII_TXD1 ETH1_RMII_TXD1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(34, "PC2"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOC2"),
+ STM32_FUNCTION(2, "SPI8_MOSI"),
+ STM32_FUNCTION(3, "LPTIM2_IN1"),
+ STM32_FUNCTION(5, "SAI4_MCLK_B"),
+ STM32_FUNCTION(6, "MDF1_SDI3"),
+ STM32_FUNCTION(7, "USART2_RTS"),
+ STM32_FUNCTION(11, "ETH1_MII_RXD1 ETH1_RGMII_RXD1 ETH1_RMII_RXD1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(35, "PC3"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOC3"),
+ STM32_FUNCTION(2, "LPTIM1_IN2"),
+ STM32_FUNCTION(3, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(4, "SPI6_RDY"),
+ STM32_FUNCTION(7, "USART6_RTS"),
+ STM32_FUNCTION(8, "FDCAN2_TX"),
+ STM32_FUNCTION(11, "ETH2_MII_RX_DV ETH2_RGMII_RX_CTL ETH2_RMII_CRS_DV"),
+ STM32_FUNCTION(12, "ETH1_MII_RX_ER"),
+ STM32_FUNCTION(14, "LCD_G6"),
+ STM32_FUNCTION(15, "DCMI_D3 PSSI_D3 DCMIPP_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(36, "PC4"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOC4"),
+ STM32_FUNCTION(4, "SPI6_MISO"),
+ STM32_FUNCTION(5, "SAI3_FS_B"),
+ STM32_FUNCTION(11, "ETH2_MII_TX_EN ETH2_RGMII_TX_CTL ETH2_RMII_TX_EN"),
+ STM32_FUNCTION(13, "ETH1_RGMII_CLK125"),
+ STM32_FUNCTION(14, "LCD_R0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(37, "PC5"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOC5"),
+ STM32_FUNCTION(3, "SPDIFRX1_IN1"),
+ STM32_FUNCTION(6, "MDF1_SDI1"),
+ STM32_FUNCTION(9, "TIM8_CH1N"),
+ STM32_FUNCTION(10, "I2C4_SDA"),
+ STM32_FUNCTION(11, "ETH2_MDIO"),
+ STM32_FUNCTION(12, "ETH1_MII_COL"),
+ STM32_FUNCTION(13, "FMC_A25"),
+ STM32_FUNCTION(14, "ETH1_PPS_OUT"),
+ STM32_FUNCTION(15, "LCD_DE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(38, "PC6"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOC6"),
+ STM32_FUNCTION(2, "RTC_REFIN"),
+ STM32_FUNCTION(3, "SPDIFRX1_IN0"),
+ STM32_FUNCTION(6, "MDF1_CKI1"),
+ STM32_FUNCTION(9, "TIM8_CH1"),
+ STM32_FUNCTION(10, "I2C4_SCL"),
+ STM32_FUNCTION(11, "ETH2_MDC"),
+ STM32_FUNCTION(12, "ETH1_MII_CRS"),
+ STM32_FUNCTION(13, "FMC_A24"),
+ STM32_FUNCTION(14, "ETH1_PHY_INTN"),
+ STM32_FUNCTION(15, "LCD_CLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(39, "PC7"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOC7"),
+ STM32_FUNCTION(4, "SPI6_MOSI"),
+ STM32_FUNCTION(5, "SAI3_SD_B"),
+ STM32_FUNCTION(9, "TIM8_CH2N"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD0 ETH2_RGMII_TXD0 ETH2_RMII_TXD0"),
+ STM32_FUNCTION(12, "ETH1_MII_TXD2 ETH1_RGMII_TXD2"),
+ STM32_FUNCTION(14, "LCD_B4"),
+ STM32_FUNCTION(15, "DCMI_D1 PSSI_D1 DCMIPP_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(40, "PC8"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOC8"),
+ STM32_FUNCTION(2, "LPTIM1_ETR"),
+ STM32_FUNCTION(4, "SPI6_NSS"),
+ STM32_FUNCTION(5, "SAI3_SCK_B"),
+ STM32_FUNCTION(7, "USART6_CTS"),
+ STM32_FUNCTION(9, "TIM8_CH2"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD1 ETH2_RGMII_TXD1 ETH2_RMII_TXD1"),
+ STM32_FUNCTION(12, "ETH1_MII_TXD3 ETH1_RGMII_TXD3"),
+ STM32_FUNCTION(14, "LCD_B3"),
+ STM32_FUNCTION(15, "DCMI_D2 PSSI_D2 DCMIPP_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(41, "PC9"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOC9"),
+ STM32_FUNCTION(2, "MCO1"),
+ STM32_FUNCTION(3, "SPI3_MISO I2S3_SDI"),
+ STM32_FUNCTION(5, "SAI2_SCK_A"),
+ STM32_FUNCTION(8, "TIM13_CH1"),
+ STM32_FUNCTION(9, "TIM8_CH4N"),
+ STM32_FUNCTION(10, "USBH_HS_OVRCUR"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD2 ETH2_RGMII_TXD2"),
+ STM32_FUNCTION(12, "USB3DR_OVRCUR"),
+ STM32_FUNCTION(13, "FMC_A22"),
+ STM32_FUNCTION(14, "LCD_G2"),
+ STM32_FUNCTION(15, "DCMI_D7 PSSI_D7 DCMIPP_D7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(42, "PC10"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOC10"),
+ STM32_FUNCTION(3, "SPI3_MOSI I2S3_SDO"),
+ STM32_FUNCTION(8, "LPTIM4_ETR"),
+ STM32_FUNCTION(9, "TIM8_CH4"),
+ STM32_FUNCTION(10, "USBH_HS_VBUSEN"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD3 ETH2_RGMII_TXD3"),
+ STM32_FUNCTION(12, "USB3DR_VBUSEN"),
+ STM32_FUNCTION(13, "FMC_A23"),
+ STM32_FUNCTION(14, "LCD_G3"),
+ STM32_FUNCTION(15, "DCMI_D6 PSSI_D6 DCMIPP_D6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(43, "PC11"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOC11"),
+ STM32_FUNCTION(2, "LPTIM1_CH1"),
+ STM32_FUNCTION(3, "SPI5_NSS"),
+ STM32_FUNCTION(5, "SAI2_MCLK_A"),
+ STM32_FUNCTION(6, "UART5_RTS"),
+ STM32_FUNCTION(7, "USART3_RTS"),
+ STM32_FUNCTION(8, "TIM3_CH1"),
+ STM32_FUNCTION(9, "TIM5_ETR"),
+ STM32_FUNCTION(11, "ETH2_MII_RXD3 ETH2_RGMII_RXD3"),
+ STM32_FUNCTION(13, "FMC_NBL1"),
+ STM32_FUNCTION(14, "LCD_R2"),
+ STM32_FUNCTION(15, "DCMI_D10 PSSI_D10 DCMIPP_D10"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(44, "PC12"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOC12"),
+ STM32_FUNCTION(2, "LPTIM1_CH2"),
+ STM32_FUNCTION(4, "I3C3_SCL"),
+ STM32_FUNCTION(6, "MDF1_CKI2"),
+ STM32_FUNCTION(9, "TIM8_CH3"),
+ STM32_FUNCTION(10, "I2C3_SCL"),
+ STM32_FUNCTION(11, "ETH2_MII_RXD1 ETH2_RGMII_RXD1 ETH2_RMII_RXD1"),
+ STM32_FUNCTION(12, "ETH1_MII_RXD3 ETH1_RGMII_RXD3"),
+ STM32_FUNCTION(14, "LCD_G1"),
+ STM32_FUNCTION(15, "DCMI_D5 PSSI_D5 DCMIPP_D5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(45, "PC13"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOC13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(48, "PD0"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOD0"),
+ STM32_FUNCTION(1, "TRACECLK"),
+ STM32_FUNCTION(2, "HDP0"),
+ STM32_FUNCTION(3, "SPI7_RDY"),
+ STM32_FUNCTION(4, "SAI1_D2"),
+ STM32_FUNCTION(6, "SAI4_FS_A"),
+ STM32_FUNCTION(7, "UART7_RX"),
+ STM32_FUNCTION(8, "TIM15_CH2"),
+ STM32_FUNCTION(10, "SDVSEL1"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_CLK"),
+ STM32_FUNCTION(14, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(49, "PD1"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOD1"),
+ STM32_FUNCTION(2, "HDP1"),
+ STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"),
+ STM32_FUNCTION(4, "SAI1_CK2"),
+ STM32_FUNCTION(6, "SAI4_SD_A"),
+ STM32_FUNCTION(7, "UART7_RTS"),
+ STM32_FUNCTION(8, "TIM15_CH1"),
+ STM32_FUNCTION(9, "TIM1_BKIN"),
+ STM32_FUNCTION(10, "FDCAN3_RX"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_NCLK"),
+ STM32_FUNCTION(12, "OCTOSPIM_P1_NCS2"),
+ STM32_FUNCTION(13, "OCTOSPIM_P2_NCS2"),
+ STM32_FUNCTION(14, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(50, "PD2"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOD2"),
+ STM32_FUNCTION(2, "HDP2"),
+ STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"),
+ STM32_FUNCTION(4, "SAI1_CK1"),
+ STM32_FUNCTION(6, "SAI4_SCK_A"),
+ STM32_FUNCTION(7, "UART7_CTS"),
+ STM32_FUNCTION(8, "TIM15_BKIN"),
+ STM32_FUNCTION(9, "TIM1_ETR"),
+ STM32_FUNCTION(10, "FDCAN3_TX"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_DQS"),
+ STM32_FUNCTION(12, "OCTOSPIM_P1_NCS2"),
+ STM32_FUNCTION(14, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(51, "PD3"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOD3"),
+ STM32_FUNCTION(2, "SAI1_MCLK_A"),
+ STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(4, "SAI1_D1"),
+ STM32_FUNCTION(6, "SAI4_MCLK_A"),
+ STM32_FUNCTION(7, "UART7_TX"),
+ STM32_FUNCTION(8, "TIM15_CH1N"),
+ STM32_FUNCTION(9, "TIM1_BKIN2"),
+ STM32_FUNCTION(10, "SDVSEL2"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_NCS1"),
+ STM32_FUNCTION(14, "PSSI_D15 DCMIPP_D15"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(52, "PD4"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOD4"),
+ STM32_FUNCTION(1, "TRACED0"),
+ STM32_FUNCTION(2, "SPI4_MISO"),
+ STM32_FUNCTION(3, "HDP3"),
+ STM32_FUNCTION(4, "SAI1_D3"),
+ STM32_FUNCTION(5, "SAI1_SD_B"),
+ STM32_FUNCTION(9, "TIM1_CH4N"),
+ STM32_FUNCTION(10, "TIM4_CH1"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_IO0"),
+ STM32_FUNCTION(14, "PSSI_D14 DCMIPP_D14"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(53, "PD5"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOD5"),
+ STM32_FUNCTION(1, "TRACED1"),
+ STM32_FUNCTION(2, "SPI4_NSS"),
+ STM32_FUNCTION(3, "HDP4"),
+ STM32_FUNCTION(4, "SAI1_D4"),
+ STM32_FUNCTION(5, "SAI1_FS_B"),
+ STM32_FUNCTION(9, "TIM1_CH3N"),
+ STM32_FUNCTION(10, "TIM4_CH2"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_IO1"),
+ STM32_FUNCTION(14, "DCMI_D13 PSSI_D13 DCMIPP_D13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(54, "PD6"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOD6"),
+ STM32_FUNCTION(1, "TRACED2"),
+ STM32_FUNCTION(2, "SPI4_MOSI"),
+ STM32_FUNCTION(3, "HDP5"),
+ STM32_FUNCTION(5, "SAI1_SCK_B"),
+ STM32_FUNCTION(6, "MDF1_SDI2"),
+ STM32_FUNCTION(9, "TIM1_CH2N"),
+ STM32_FUNCTION(10, "TIM4_CH3"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_IO2"),
+ STM32_FUNCTION(14, "DCMI_D12 PSSI_D12 DCMIPP_D12"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(55, "PD7"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOD7"),
+ STM32_FUNCTION(1, "TRACED3"),
+ STM32_FUNCTION(2, "SPI4_SCK"),
+ STM32_FUNCTION(3, "SPI1_RDY"),
+ STM32_FUNCTION(5, "SAI1_MCLK_B"),
+ STM32_FUNCTION(6, "MDF1_CKI2"),
+ STM32_FUNCTION(9, "TIM1_CH1N"),
+ STM32_FUNCTION(10, "TIM4_CH4"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_IO3"),
+ STM32_FUNCTION(14, "DCMI_D11 PSSI_D11 DCMIPP_D11"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(56, "PD8"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOD8"),
+ STM32_FUNCTION(1, "TRACED4"),
+ STM32_FUNCTION(2, "SPI4_RDY"),
+ STM32_FUNCTION(3, "I2S1_MCK"),
+ STM32_FUNCTION(4, "SAI1_FS_A"),
+ STM32_FUNCTION(5, "UART4_CTS"),
+ STM32_FUNCTION(6, "MDF1_SDI1"),
+ STM32_FUNCTION(9, "TIM1_CH4"),
+ STM32_FUNCTION(10, "TIM4_ETR"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_IO4"),
+ STM32_FUNCTION(12, "SDMMC1_D7"),
+ STM32_FUNCTION(13, "SDMMC1_D123DIR"),
+ STM32_FUNCTION(14, "DCMI_D10 PSSI_D10 DCMIPP_D10"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(57, "PD9"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOD9"),
+ STM32_FUNCTION(1, "TRACED5"),
+ STM32_FUNCTION(2, "HDP6"),
+ STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"),
+ STM32_FUNCTION(4, "SAI1_SD_A"),
+ STM32_FUNCTION(5, "UART4_RTS"),
+ STM32_FUNCTION(6, "MDF1_CKI1"),
+ STM32_FUNCTION(9, "TIM1_CH3"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_IO5"),
+ STM32_FUNCTION(12, "SDMMC1_D6"),
+ STM32_FUNCTION(13, "SDMMC1_D0DIR"),
+ STM32_FUNCTION(14, "DCMI_D9 PSSI_D9 DCMIPP_D9"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(58, "PD10"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOD10"),
+ STM32_FUNCTION(1, "TRACED6"),
+ STM32_FUNCTION(2, "HDP7"),
+ STM32_FUNCTION(4, "SAI1_SCK_A"),
+ STM32_FUNCTION(5, "UART4_RX"),
+ STM32_FUNCTION(6, "MDF1_SDI0"),
+ STM32_FUNCTION(7, "I2C4_SDA"),
+ STM32_FUNCTION(9, "TIM1_CH2"),
+ STM32_FUNCTION(10, "TIM14_CH1"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_IO6"),
+ STM32_FUNCTION(12, "SDMMC1_D5"),
+ STM32_FUNCTION(13, "SDMMC1_CDIR"),
+ STM32_FUNCTION(14, "DCMI_D8 PSSI_D8 DCMIPP_D8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(59, "PD11"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOD11"),
+ STM32_FUNCTION(1, "TRACED7"),
+ STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
+ STM32_FUNCTION(4, "SAI1_MCLK_A"),
+ STM32_FUNCTION(5, "UART4_TX"),
+ STM32_FUNCTION(6, "MDF1_CKI0"),
+ STM32_FUNCTION(7, "I2C4_SCL"),
+ STM32_FUNCTION(9, "TIM1_CH1"),
+ STM32_FUNCTION(10, "SDVSEL1"),
+ STM32_FUNCTION(11, "OCTOSPIM_P1_IO7"),
+ STM32_FUNCTION(12, "SDMMC1_D4"),
+ STM32_FUNCTION(13, "SDMMC1_CKIN"),
+ STM32_FUNCTION(14, "DCMI_D7 PSSI_D7 DCMIPP_D7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(60, "PD12"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOD12"),
+ STM32_FUNCTION(2, "SPI7_MISO"),
+ STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"),
+ STM32_FUNCTION(4, "SPDIFRX1_IN2"),
+ STM32_FUNCTION(6, "UART8_RTS"),
+ STM32_FUNCTION(10, "TIM4_ETR"),
+ STM32_FUNCTION(11, "SDMMC3_CMD"),
+ STM32_FUNCTION(12, "FMC_AD6 FMC_D6"),
+ STM32_FUNCTION(13, "FMC_AD1 FMC_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(61, "PD13"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOD13"),
+ STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"),
+ STM32_FUNCTION(6, "MDF1_SDI7"),
+ STM32_FUNCTION(7, "UART9_TX"),
+ STM32_FUNCTION(10, "TIM4_CH4"),
+ STM32_FUNCTION(11, "SDMMC3_D1"),
+ STM32_FUNCTION(12, "FMC_AD11 FMC_D11"),
+ STM32_FUNCTION(13, "FMC_NWE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(62, "PD14"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOD14"),
+ STM32_FUNCTION(3, "I2S1_MCK"),
+ STM32_FUNCTION(8, "FDCAN1_RX"),
+ STM32_FUNCTION(9, "TIM11_CH1"),
+ STM32_FUNCTION(11, "I2C7_SDA"),
+ STM32_FUNCTION(12, "FMC_AD4 FMC_D4"),
+ STM32_FUNCTION(13, "SDMMC3_D3"),
+ STM32_FUNCTION(14, "DCMI_D1 PSSI_D1 DCMIPP_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(63, "PD15"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOD15"),
+ STM32_FUNCTION(2, "SPI1_RDY"),
+ STM32_FUNCTION(6, "DSI_TE"),
+ STM32_FUNCTION(7, "I2C5_SDA"),
+ STM32_FUNCTION(8, "FDCAN1_TX"),
+ STM32_FUNCTION(9, "TIM1_BKIN2"),
+ STM32_FUNCTION(10, "TIM5_ETR"),
+ STM32_FUNCTION(11, "I2C7_SCL"),
+ STM32_FUNCTION(12, "FMC_AD3 FMC_D3"),
+ STM32_FUNCTION(13, "SDMMC3_CKIN"),
+ STM32_FUNCTION(14, "DCMI_D0 PSSI_D0 DCMIPP_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(64, "PE0"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOE0"),
+ STM32_FUNCTION(1, "TRACED2"),
+ STM32_FUNCTION(2, "LPTIM2_CH1"),
+ STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
+ STM32_FUNCTION(4, "SPI3_RDY"),
+ STM32_FUNCTION(7, "USART3_CK"),
+ STM32_FUNCTION(11, "SDMMC1_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(65, "PE1"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOE1"),
+ STM32_FUNCTION(1, "TRACED3"),
+ STM32_FUNCTION(2, "LPTIM2_CH2"),
+ STM32_FUNCTION(3, "I2S1_MCK"),
+ STM32_FUNCTION(4, "I2S3_MCK"),
+ STM32_FUNCTION(7, "USART3_RX"),
+ STM32_FUNCTION(11, "SDMMC1_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(66, "PE2"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOE2"),
+ STM32_FUNCTION(2, "LPTIM2_ETR"),
+ STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"),
+ STM32_FUNCTION(4, "SPI3_MOSI I2S3_SDO"),
+ STM32_FUNCTION(5, "SAI1_SCK_B"),
+ STM32_FUNCTION(9, "TIM10_CH1"),
+ STM32_FUNCTION(11, "SDMMC1_CMD"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(67, "PE3"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOE3"),
+ STM32_FUNCTION(1, "TRACECLK"),
+ STM32_FUNCTION(3, "SPI1_RDY"),
+ STM32_FUNCTION(4, "SPI3_SCK I2S3_CK"),
+ STM32_FUNCTION(5, "SAI1_MCLK_B"),
+ STM32_FUNCTION(7, "USART3_TX"),
+ STM32_FUNCTION(9, "TIM11_CH1"),
+ STM32_FUNCTION(11, "SDMMC1_CK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(68, "PE4"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOE4"),
+ STM32_FUNCTION(1, "TRACED0"),
+ STM32_FUNCTION(2, "LPTIM2_IN1"),
+ STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"),
+ STM32_FUNCTION(4, "SPI3_MISO I2S3_SDI"),
+ STM32_FUNCTION(5, "SAI1_SD_B"),
+ STM32_FUNCTION(7, "USART3_CTS"),
+ STM32_FUNCTION(8, "FDCAN1_TX"),
+ STM32_FUNCTION(11, "SDMMC1_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(69, "PE5"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOE5"),
+ STM32_FUNCTION(1, "TRACED1"),
+ STM32_FUNCTION(2, "LPTIM2_IN2"),
+ STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"),
+ STM32_FUNCTION(4, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(5, "SAI1_FS_B"),
+ STM32_FUNCTION(7, "USART3_RTS"),
+ STM32_FUNCTION(8, "FDCAN1_RX"),
+ STM32_FUNCTION(11, "SDMMC1_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(70, "PE6"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOE6"),
+ STM32_FUNCTION(2, "SPI4_RDY"),
+ STM32_FUNCTION(5, "SPDIFRX1_IN2"),
+ STM32_FUNCTION(7, "USART1_TX"),
+ STM32_FUNCTION(9, "TIM1_ETR"),
+ STM32_FUNCTION(12, "FMC_AD1 FMC_D1"),
+ STM32_FUNCTION(13, "SDMMC2_D6"),
+ STM32_FUNCTION(14, "SDMMC2_D0DIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(71, "PE7"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOE7"),
+ STM32_FUNCTION(4, "SAI4_D4"),
+ STM32_FUNCTION(5, "SPDIFRX1_IN3"),
+ STM32_FUNCTION(7, "USART1_RX"),
+ STM32_FUNCTION(9, "TIM1_CH4N"),
+ STM32_FUNCTION(11, "TIM14_CH1"),
+ STM32_FUNCTION(12, "FMC_AD2 FMC_D2"),
+ STM32_FUNCTION(13, "SDMMC2_D7"),
+ STM32_FUNCTION(14, "SDMMC2_D123DIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(72, "PE8"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOE8"),
+ STM32_FUNCTION(2, "SPI4_MOSI"),
+ STM32_FUNCTION(4, "SAI4_CK1"),
+ STM32_FUNCTION(5, "SAI4_MCLK_A"),
+ STM32_FUNCTION(6, "MDF1_CKI0"),
+ STM32_FUNCTION(9, "TIM1_CH1"),
+ STM32_FUNCTION(12, "FMC_A17 FMC_ALE"),
+ STM32_FUNCTION(13, "SDMMC2_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(73, "PE9"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOE9"),
+ STM32_FUNCTION(2, "SPI4_MISO"),
+ STM32_FUNCTION(4, "SAI4_D2"),
+ STM32_FUNCTION(5, "SAI4_FS_A"),
+ STM32_FUNCTION(7, "USART1_CK"),
+ STM32_FUNCTION(9, "TIM1_CH4"),
+ STM32_FUNCTION(12, "FMC_AD0 FMC_D0"),
+ STM32_FUNCTION(13, "SDMMC2_D5"),
+ STM32_FUNCTION(14, "SDMMC2_CDIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(74, "PE10"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOE10"),
+ STM32_FUNCTION(2, "SPI4_SCK"),
+ STM32_FUNCTION(4, "SAI4_D1"),
+ STM32_FUNCTION(5, "SAI4_SD_A"),
+ STM32_FUNCTION(7, "USART1_CTS"),
+ STM32_FUNCTION(9, "TIM1_CH3"),
+ STM32_FUNCTION(11, "FMC_NE3"),
+ STM32_FUNCTION(12, "FMC_NCE2"),
+ STM32_FUNCTION(13, "SDMMC2_D4"),
+ STM32_FUNCTION(14, "SDMMC2_CKIN"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(75, "PE11"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOE11"),
+ STM32_FUNCTION(3, "SPI7_SCK"),
+ STM32_FUNCTION(4, "SAI4_D3"),
+ STM32_FUNCTION(5, "SAI1_FS_A"),
+ STM32_FUNCTION(8, "TIM15_CH2"),
+ STM32_FUNCTION(9, "TIM1_CH3N"),
+ STM32_FUNCTION(12, "FMC_A16 FMC_CLE"),
+ STM32_FUNCTION(13, "SDMMC2_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(76, "PE12"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOE12"),
+ STM32_FUNCTION(2, "SPI4_NSS"),
+ STM32_FUNCTION(4, "SAI4_CK2"),
+ STM32_FUNCTION(5, "SAI4_SCK_A"),
+ STM32_FUNCTION(6, "MDF1_SDI0"),
+ STM32_FUNCTION(7, "USART1_RTS"),
+ STM32_FUNCTION(9, "TIM1_CH2"),
+ STM32_FUNCTION(11, "FMC_NE2"),
+ STM32_FUNCTION(12, "FMC_NCE1"),
+ STM32_FUNCTION(13, "SDMMC2_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(77, "PE13"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOE13"),
+ STM32_FUNCTION(3, "SPI7_MISO"),
+ STM32_FUNCTION(5, "SAI1_SD_A"),
+ STM32_FUNCTION(8, "TIM15_CH1"),
+ STM32_FUNCTION(9, "TIM1_CH2N"),
+ STM32_FUNCTION(12, "FMC_RNB"),
+ STM32_FUNCTION(13, "SDMMC2_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(78, "PE14"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOE14"),
+ STM32_FUNCTION(3, "SPI7_NSS"),
+ STM32_FUNCTION(5, "SAI1_MCLK_A"),
+ STM32_FUNCTION(6, "MDF1_CKI6"),
+ STM32_FUNCTION(8, "TIM15_BKIN"),
+ STM32_FUNCTION(9, "TIM1_BKIN"),
+ STM32_FUNCTION(12, "FMC_NWE"),
+ STM32_FUNCTION(13, "SDMMC2_CK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(79, "PE15"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOE15"),
+ STM32_FUNCTION(3, "SPI7_MOSI"),
+ STM32_FUNCTION(5, "SAI1_SCK_A"),
+ STM32_FUNCTION(6, "MDF1_SDI6"),
+ STM32_FUNCTION(8, "TIM15_CH1N"),
+ STM32_FUNCTION(9, "TIM1_CH1N"),
+ STM32_FUNCTION(12, "FMC_NOE"),
+ STM32_FUNCTION(13, "SDMMC2_CMD"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(80, "PF0"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOF0"),
+ STM32_FUNCTION(3, "SPI3_SCK I2S3_CK"),
+ STM32_FUNCTION(8, "FDCAN2_RX"),
+ STM32_FUNCTION(9, "TIM12_CH2"),
+ STM32_FUNCTION(10, "I2C2_SDA"),
+ STM32_FUNCTION(11, "ETH1_MDC"),
+ STM32_FUNCTION(12, "ETH2_MII_CRS"),
+ STM32_FUNCTION(14, "I3C2_SDA"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(81, "PF1"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOF1"),
+ STM32_FUNCTION(2, "SPI8_MISO"),
+ STM32_FUNCTION(3, "LPTIM2_IN2"),
+ STM32_FUNCTION(5, "SAI4_SCK_B"),
+ STM32_FUNCTION(6, "MDF1_CKI4"),
+ STM32_FUNCTION(7, "USART2_CK"),
+ STM32_FUNCTION(11, "ETH1_MII_RXD0 ETH1_RGMII_RXD0 ETH1_RMII_RXD0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(82, "PF2"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOF2"),
+ STM32_FUNCTION(3, "SPI3_RDY"),
+ STM32_FUNCTION(7, "I2C4_SMBA"),
+ STM32_FUNCTION(9, "TIM12_CH1"),
+ STM32_FUNCTION(10, "I2C2_SCL"),
+ STM32_FUNCTION(11, "ETH1_MDIO"),
+ STM32_FUNCTION(12, "ETH2_MII_COL"),
+ STM32_FUNCTION(13, "FMC_NE4"),
+ STM32_FUNCTION(14, "I3C2_SCL"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(83, "PF3"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOF3"),
+ STM32_FUNCTION(4, "UART8_RX"),
+ STM32_FUNCTION(5, "SAI2_SCK_B"),
+ STM32_FUNCTION(6, "MDF1_CCK0"),
+ STM32_FUNCTION(8, "TIM3_CH4"),
+ STM32_FUNCTION(9, "TIM8_BKIN2"),
+ STM32_FUNCTION(10, "ETH1_CLK"),
+ STM32_FUNCTION(11, "ETH2_PPS_OUT"),
+ STM32_FUNCTION(13, "FMC_A20"),
+ STM32_FUNCTION(14, "LCD_R6"),
+ STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(84, "PF4"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOF4"),
+ STM32_FUNCTION(2, "RTC_OUT2"),
+ STM32_FUNCTION(3, "SPI6_NSS"),
+ STM32_FUNCTION(5, "SAI3_SCK_A"),
+ STM32_FUNCTION(7, "USART6_RX"),
+ STM32_FUNCTION(8, "TIM4_CH4"),
+ STM32_FUNCTION(9, "ETH1_MDC"),
+ STM32_FUNCTION(10, "ETH2_CLK"),
+ STM32_FUNCTION(11, "ETH2_PPS_OUT"),
+ STM32_FUNCTION(12, "ETH1_PPS_OUT"),
+ STM32_FUNCTION(14, "LCD_B7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(85, "PF5"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOF5"),
+ STM32_FUNCTION(3, "SPI6_SCK"),
+ STM32_FUNCTION(5, "SAI3_MCLK_A"),
+ STM32_FUNCTION(7, "USART6_TX"),
+ STM32_FUNCTION(8, "TIM4_CH3"),
+ STM32_FUNCTION(9, "ETH1_MDIO"),
+ STM32_FUNCTION(10, "ETH1_CLK"),
+ STM32_FUNCTION(11, "ETH2_PHY_INTN"),
+ STM32_FUNCTION(12, "ETH1_PHY_INTN"),
+ STM32_FUNCTION(14, "LCD_B6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(86, "PF6"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOF6"),
+ STM32_FUNCTION(2, "RTC_OUT2"),
+ STM32_FUNCTION(4, "SAI3_MCLK_B"),
+ STM32_FUNCTION(7, "USART6_CK"),
+ STM32_FUNCTION(8, "TIM12_CH1"),
+ STM32_FUNCTION(10, "I2C3_SMBA"),
+ STM32_FUNCTION(11, "ETH2_MII_RX_CLK ETH2_RGMII_RX_CLK ETH2_RMII_REF_CLK"),
+ STM32_FUNCTION(14, "LCD_B0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(87, "PF7"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOF7"),
+ STM32_FUNCTION(3, "SPDIFRX1_IN1"),
+ STM32_FUNCTION(4, "SPI6_SCK"),
+ STM32_FUNCTION(5, "SAI3_SD_A"),
+ STM32_FUNCTION(8, "TIM2_ETR"),
+ STM32_FUNCTION(11, "ETH2_RGMII_GTX_CLK"),
+ STM32_FUNCTION(12, "ETH2_MII_TX_CLK"),
+ STM32_FUNCTION(14, "LCD_R1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(88, "PF8"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOF8"),
+ STM32_FUNCTION(2, "RTC_REFIN"),
+ STM32_FUNCTION(4, "SAI3_SCK_B"),
+ STM32_FUNCTION(7, "USART3_RX"),
+ STM32_FUNCTION(8, "TIM12_CH2"),
+ STM32_FUNCTION(10, "ETH1_CLK"),
+ STM32_FUNCTION(11, "ETH2_RGMII_CLK125"),
+ STM32_FUNCTION(12, "ETH2_MII_RX_ER"),
+ STM32_FUNCTION(13, "ETH2_MII_RX_DV ETH2_RGMII_RX_CTL ETH2_RMII_CRS_DV"),
+ STM32_FUNCTION(14, "LCD_G0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(89, "PF9"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOF9"),
+ STM32_FUNCTION(4, "SAI3_SD_B"),
+ STM32_FUNCTION(5, "SAI2_SD_A"),
+ STM32_FUNCTION(6, "MDF1_SDI5"),
+ STM32_FUNCTION(7, "UART8_RTS"),
+ STM32_FUNCTION(8, "TIM2_CH2"),
+ STM32_FUNCTION(11, "ETH2_MII_RXD2 ETH2_RGMII_RXD2"),
+ STM32_FUNCTION(12, "ETH2_MDIO"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(90, "PF10"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOF10"),
+ STM32_FUNCTION(2, "MCO2"),
+ STM32_FUNCTION(3, "SPI3_RDY"),
+ STM32_FUNCTION(5, "SAI2_MCLK_A"),
+ STM32_FUNCTION(6, "MDF1_CKI6"),
+ STM32_FUNCTION(7, "UART8_TX"),
+ STM32_FUNCTION(8, "TIM2_CH3"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD2 ETH2_RGMII_TXD2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(91, "PF11"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOF11"),
+ STM32_FUNCTION(2, "MCO1"),
+ STM32_FUNCTION(3, "SPDIFRX1_IN0"),
+ STM32_FUNCTION(4, "SPI6_RDY"),
+ STM32_FUNCTION(5, "SAI2_SCK_A"),
+ STM32_FUNCTION(6, "MDF1_SDI6"),
+ STM32_FUNCTION(7, "UART8_RX"),
+ STM32_FUNCTION(8, "TIM2_CH4"),
+ STM32_FUNCTION(11, "ETH2_MII_TXD3 ETH2_RGMII_TXD3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(92, "PF12"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOF12"),
+ STM32_FUNCTION(1, "TRACECLK"),
+ STM32_FUNCTION(3, "SPI5_MISO"),
+ STM32_FUNCTION(4, "SPI1_MISO I2S1_SDI"),
+ STM32_FUNCTION(7, "UART9_RTS"),
+ STM32_FUNCTION(9, "TIM5_CH1"),
+ STM32_FUNCTION(14, "LCD_CLK"),
+ STM32_FUNCTION(15, "DCMI_D0 PSSI_D0 DCMIPP_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(93, "PF13"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOF13"),
+ STM32_FUNCTION(1, "TRACED0"),
+ STM32_FUNCTION(2, "HDP0"),
+ STM32_FUNCTION(3, "AUDIOCLK"),
+ STM32_FUNCTION(4, "USART6_TX"),
+ STM32_FUNCTION(5, "SPI2_NSS I2S2_WS"),
+ STM32_FUNCTION(6, "MDF1_CKI7"),
+ STM32_FUNCTION(7, "USART3_CTS"),
+ STM32_FUNCTION(8, "FDCAN3_TX"),
+ STM32_FUNCTION(9, "TIM3_CH3"),
+ STM32_FUNCTION(14, "LCD_R2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(94, "PF14"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOF14"),
+ STM32_FUNCTION(1, "TRACED1"),
+ STM32_FUNCTION(2, "HDP1"),
+ STM32_FUNCTION(4, "USART6_RX"),
+ STM32_FUNCTION(6, "MDF1_SDI7"),
+ STM32_FUNCTION(7, "USART3_RTS"),
+ STM32_FUNCTION(8, "FDCAN3_RX"),
+ STM32_FUNCTION(9, "TIM3_CH4"),
+ STM32_FUNCTION(14, "LCD_R3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(95, "PF15"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOF15"),
+ STM32_FUNCTION(1, "TRACED2"),
+ STM32_FUNCTION(2, "HDP2"),
+ STM32_FUNCTION(3, "SPI2_RDY"),
+ STM32_FUNCTION(4, "USART6_CTS"),
+ STM32_FUNCTION(5, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(7, "USART3_CK"),
+ STM32_FUNCTION(8, "TIM2_CH2"),
+ STM32_FUNCTION(9, "TIM3_ETR"),
+ STM32_FUNCTION(10, "I2C6_SMBA"),
+ STM32_FUNCTION(14, "LCD_R4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(96, "PG0"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOG0"),
+ STM32_FUNCTION(2, "LPTIM1_IN1"),
+ STM32_FUNCTION(4, "I3C3_SDA"),
+ STM32_FUNCTION(6, "MDF1_SDI2"),
+ STM32_FUNCTION(9, "TIM8_CH3N"),
+ STM32_FUNCTION(10, "I2C3_SDA"),
+ STM32_FUNCTION(11, "ETH2_MII_RXD0 ETH2_RGMII_RXD0 ETH2_RMII_RXD0"),
+ STM32_FUNCTION(12, "ETH1_MII_RXD2 ETH1_RGMII_RXD2"),
+ STM32_FUNCTION(14, "LCD_G5"),
+ STM32_FUNCTION(15, "DCMI_D4 PSSI_D4 DCMIPP_D4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(97, "PG1"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOG1"),
+ STM32_FUNCTION(2, "LPTIM1_IN1"),
+ STM32_FUNCTION(3, "I2S3_MCK"),
+ STM32_FUNCTION(4, "I3C3_SCL"),
+ STM32_FUNCTION(5, "SAI2_SD_A"),
+ STM32_FUNCTION(6, "UART5_CTS"),
+ STM32_FUNCTION(7, "USART3_CTS"),
+ STM32_FUNCTION(9, "TIM5_CH4"),
+ STM32_FUNCTION(10, "I2C3_SCL"),
+ STM32_FUNCTION(11, "ETH2_MII_RX_ER"),
+ STM32_FUNCTION(12, "ETH2_MII_RXD3 ETH2_RGMII_RXD3"),
+ STM32_FUNCTION(13, "FMC_NBL0"),
+ STM32_FUNCTION(14, "LCD_VSYNC"),
+ STM32_FUNCTION(15, "DCMI_D11 PSSI_D11 DCMIPP_D11"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(98, "PG2"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOG2"),
+ STM32_FUNCTION(2, "RTC_REFIN"),
+ STM32_FUNCTION(3, "I2S3_MCK"),
+ STM32_FUNCTION(4, "I3C3_SDA"),
+ STM32_FUNCTION(5, "SAI2_FS_A"),
+ STM32_FUNCTION(7, "USART3_CK"),
+ STM32_FUNCTION(9, "TIM5_CH3"),
+ STM32_FUNCTION(10, "I2C3_SDA"),
+ STM32_FUNCTION(11, "ETH2_MII_TX_CLK"),
+ STM32_FUNCTION(12, "ETH2_RGMII_CLK125"),
+ STM32_FUNCTION(13, "FMC_CLK"),
+ STM32_FUNCTION(14, "LCD_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(99, "PG3"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOG3"),
+ STM32_FUNCTION(2, "LPTIM1_ETR"),
+ STM32_FUNCTION(3, "SPI5_MOSI"),
+ STM32_FUNCTION(4, "UART8_TX"),
+ STM32_FUNCTION(5, "SAI2_FS_B"),
+ STM32_FUNCTION(8, "TIM3_CH3"),
+ STM32_FUNCTION(9, "TIM8_ETR"),
+ STM32_FUNCTION(10, "ETH2_CLK"),
+ STM32_FUNCTION(11, "ETH2_PHY_INTN"),
+ STM32_FUNCTION(13, "FMC_A19"),
+ STM32_FUNCTION(14, "LCD_R5"),
+ STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(100, "PG4"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOG4"),
+ STM32_FUNCTION(3, "SPI5_MISO"),
+ STM32_FUNCTION(4, "SAI3_FS_B"),
+ STM32_FUNCTION(8, "LPTIM4_IN1"),
+ STM32_FUNCTION(9, "TIM8_BKIN"),
+ STM32_FUNCTION(11, "ETH2_PPS_OUT"),
+ STM32_FUNCTION(12, "ETH2_MDC"),
+ STM32_FUNCTION(13, "FMC_A21"),
+ STM32_FUNCTION(14, "LCD_R7"),
+ STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(101, "PG5"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOG5"),
+ STM32_FUNCTION(1, "TRACED3"),
+ STM32_FUNCTION(2, "HDP3"),
+ STM32_FUNCTION(4, "USART6_RTS"),
+ STM32_FUNCTION(8, "TIM2_CH3"),
+ STM32_FUNCTION(10, "I2C6_SDA"),
+ STM32_FUNCTION(14, "LCD_R5"),
+ STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(102, "PG6"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOG6"),
+ STM32_FUNCTION(1, "TRACED4"),
+ STM32_FUNCTION(2, "HDP4"),
+ STM32_FUNCTION(3, "SPI5_SCK"),
+ STM32_FUNCTION(4, "SPI1_SCK I2S1_CK"),
+ STM32_FUNCTION(8, "TIM2_CH4"),
+ STM32_FUNCTION(10, "I2C6_SCL"),
+ STM32_FUNCTION(14, "LCD_R6"),
+ STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(103, "PG7"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOG7"),
+ STM32_FUNCTION(1, "TRACED5"),
+ STM32_FUNCTION(2, "HDP5"),
+ STM32_FUNCTION(3, "SPI5_NSS"),
+ STM32_FUNCTION(4, "SPI1_NSS I2S1_WS"),
+ STM32_FUNCTION(7, "UART9_CTS"),
+ STM32_FUNCTION(9, "TIM5_ETR"),
+ STM32_FUNCTION(14, "LCD_R7"),
+ STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(104, "PG8"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOG8"),
+ STM32_FUNCTION(1, "TRACED6"),
+ STM32_FUNCTION(2, "HDP6"),
+ STM32_FUNCTION(3, "SPI5_RDY"),
+ STM32_FUNCTION(4, "SPI1_RDY"),
+ STM32_FUNCTION(5, "USART6_CK"),
+ STM32_FUNCTION(6, "UART5_RTS"),
+ STM32_FUNCTION(7, "UART9_TX"),
+ STM32_FUNCTION(9, "TIM5_CH3"),
+ STM32_FUNCTION(14, "LCD_G2"),
+ STM32_FUNCTION(15, "DCMI_D2 PSSI_D2 DCMIPP_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(105, "PG9"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOG9"),
+ STM32_FUNCTION(1, "TRACED7"),
+ STM32_FUNCTION(6, "UART5_TX"),
+ STM32_FUNCTION(9, "TIM5_CH4"),
+ STM32_FUNCTION(14, "LCD_G3"),
+ STM32_FUNCTION(15, "DCMI_D3 PSSI_D3 DCMIPP_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(106, "PG10"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOG10"),
+ STM32_FUNCTION(1, "TRACED8"),
+ STM32_FUNCTION(2, "HDP0"),
+ STM32_FUNCTION(6, "UART5_RX"),
+ STM32_FUNCTION(9, "TIM8_CH4N"),
+ STM32_FUNCTION(14, "LCD_G4"),
+ STM32_FUNCTION(15, "DCMI_D4 PSSI_D4 DCMIPP_D4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(107, "PG11"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOG11"),
+ STM32_FUNCTION(1, "TRACED9"),
+ STM32_FUNCTION(2, "HDP1"),
+ STM32_FUNCTION(3, "SPI7_MOSI"),
+ STM32_FUNCTION(8, "FDCAN1_TX"),
+ STM32_FUNCTION(9, "TIM8_CH4"),
+ STM32_FUNCTION(14, "LCD_G5"),
+ STM32_FUNCTION(15, "DCMI_D5 PSSI_D5 DCMIPP_D5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(108, "PG12"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOG12"),
+ STM32_FUNCTION(1, "TRACED10"),
+ STM32_FUNCTION(2, "HDP2"),
+ STM32_FUNCTION(3, "SPI7_MISO"),
+ STM32_FUNCTION(8, "FDCAN1_RX"),
+ STM32_FUNCTION(9, "TIM8_CH1N"),
+ STM32_FUNCTION(14, "LCD_G6"),
+ STM32_FUNCTION(15, "DCMI_D6 PSSI_D6 DCMIPP_D6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(109, "PG13"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOG13"),
+ STM32_FUNCTION(1, "TRACED11"),
+ STM32_FUNCTION(2, "HDP3"),
+ STM32_FUNCTION(3, "SPI7_SCK"),
+ STM32_FUNCTION(6, "MDF1_CKI6"),
+ STM32_FUNCTION(9, "TIM8_CH2N"),
+ STM32_FUNCTION(10, "I2C1_SCL"),
+ STM32_FUNCTION(11, "I3C1_SCL"),
+ STM32_FUNCTION(14, "LCD_G7"),
+ STM32_FUNCTION(15, "DCMI_D7 PSSI_D7 DCMIPP_D7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(110, "PG14"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOG14"),
+ STM32_FUNCTION(1, "TRACED12"),
+ STM32_FUNCTION(2, "HDP4"),
+ STM32_FUNCTION(3, "SPI7_RDY"),
+ STM32_FUNCTION(6, "MDF1_CKI5"),
+ STM32_FUNCTION(7, "USART1_TX"),
+ STM32_FUNCTION(9, "TIM8_BKIN2"),
+ STM32_FUNCTION(14, "LCD_B1"),
+ STM32_FUNCTION(15, "DCMI_D9 PSSI_D9 DCMIPP_D9"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(111, "PG15"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOG15"),
+ STM32_FUNCTION(1, "TRACED13"),
+ STM32_FUNCTION(2, "HDP5"),
+ STM32_FUNCTION(4, "LPTIM1_CH2"),
+ STM32_FUNCTION(6, "MDF1_SDI5"),
+ STM32_FUNCTION(7, "USART1_RX"),
+ STM32_FUNCTION(9, "TIM8_ETR"),
+ STM32_FUNCTION(14, "LCD_B2"),
+ STM32_FUNCTION(15, "DCMI_D10 PSSI_D10 DCMIPP_D10"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(114, "PH2"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOH2"),
+ STM32_FUNCTION(2, "LPTIM2_CH1"),
+ STM32_FUNCTION(3, "SPI7_RDY"),
+ STM32_FUNCTION(4, "SPDIFRX1_IN3"),
+ STM32_FUNCTION(5, "SAI1_SCK_B"),
+ STM32_FUNCTION(6, "I3C3_SDA"),
+ STM32_FUNCTION(8, "TIM16_CH1"),
+ STM32_FUNCTION(9, "I2C5_SDA"),
+ STM32_FUNCTION(10, "I2C3_SDA"),
+ STM32_FUNCTION(15, "ETH3_RGMII_GTX_CLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(115, "PH3"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOH3"),
+ STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"),
+ STM32_FUNCTION(7, "UART7_RX"),
+ STM32_FUNCTION(8, "TIM17_CH1N"),
+ STM32_FUNCTION(10, "TIM5_CH3"),
+ STM32_FUNCTION(11, "I2C7_SCL"),
+ STM32_FUNCTION(15, "ETH3_RGMII_TXD3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(116, "PH4"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOH4"),
+ STM32_FUNCTION(7, "UART7_TX"),
+ STM32_FUNCTION(8, "TIM17_BKIN"),
+ STM32_FUNCTION(10, "TIM5_CH2"),
+ STM32_FUNCTION(11, "LCD_R0"),
+ STM32_FUNCTION(12, "USB3DR_OVRCUR"),
+ STM32_FUNCTION(13, "USBH_HS_OVRCUR"),
+ STM32_FUNCTION(14, "ETH1_PTP_AUX_TS"),
+ STM32_FUNCTION(15, "ETH3_PPS_OUT"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(117, "PH5"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOH5"),
+ STM32_FUNCTION(5, "SAI2_FS_A"),
+ STM32_FUNCTION(7, "UART8_CTS"),
+ STM32_FUNCTION(8, "TIM2_CH1"),
+ STM32_FUNCTION(9, "UART7_RX"),
+ STM32_FUNCTION(11, "LCD_G1"),
+ STM32_FUNCTION(12, "USB3DR_VBUSEN"),
+ STM32_FUNCTION(13, "USBH_HS_VBUSEN"),
+ STM32_FUNCTION(14, "ETH2_PTP_AUX_TS"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(118, "PH6"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOH6"),
+ STM32_FUNCTION(2, "LPTIM2_IN2"),
+ STM32_FUNCTION(5, "SAI1_MCLK_B"),
+ STM32_FUNCTION(6, "I3C3_SCL"),
+ STM32_FUNCTION(8, "TIM16_CH1N"),
+ STM32_FUNCTION(9, "I2C5_SCL"),
+ STM32_FUNCTION(10, "I2C3_SCL"),
+ STM32_FUNCTION(11, "I2C1_SMBA"),
+ STM32_FUNCTION(15, "ETH3_RGMII_TXD2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(119, "PH7"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOH7"),
+ STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"),
+ STM32_FUNCTION(5, "UART4_TX"),
+ STM32_FUNCTION(7, "UART7_RTS"),
+ STM32_FUNCTION(8, "TIM17_CH1"),
+ STM32_FUNCTION(10, "TIM5_CH4"),
+ STM32_FUNCTION(11, "I2C7_SDA"),
+ STM32_FUNCTION(15, "ETH3_RGMII_RXD2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(120, "PH8"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOH8"),
+ STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"),
+ STM32_FUNCTION(4, "SPDIFRX1_IN3"),
+ STM32_FUNCTION(5, "UART4_RX"),
+ STM32_FUNCTION(7, "UART7_CTS"),
+ STM32_FUNCTION(10, "TIM5_CH1"),
+ STM32_FUNCTION(11, "I2C3_SMBA"),
+ STM32_FUNCTION(12, "I2C5_SMBA"),
+ STM32_FUNCTION(15, "ETH3_RGMII_RXD3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(121, "PH9"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOH9"),
+ STM32_FUNCTION(4, "SPI6_NSS"),
+ STM32_FUNCTION(5, "SAI3_MCLK_A"),
+ STM32_FUNCTION(7, "USART6_RX"),
+ STM32_FUNCTION(8, "TIM15_CH1N"),
+ STM32_FUNCTION(11, "ETH1_RGMII_CLK125"),
+ STM32_FUNCTION(12, "ETH1_MII_RX_ER"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(122, "PH10"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOH10"),
+ STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
+ STM32_FUNCTION(4, "SPI6_MOSI"),
+ STM32_FUNCTION(5, "SAI3_SCK_A"),
+ STM32_FUNCTION(8, "TIM15_CH1"),
+ STM32_FUNCTION(10, "ETH2_MDC"),
+ STM32_FUNCTION(11, "ETH1_MII_TXD2 ETH1_RGMII_TXD2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(123, "PH11"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOH11"),
+ STM32_FUNCTION(4, "SPI6_MISO"),
+ STM32_FUNCTION(5, "SAI3_FS_A"),
+ STM32_FUNCTION(8, "TIM15_CH2"),
+ STM32_FUNCTION(10, "ETH2_MDIO"),
+ STM32_FUNCTION(11, "ETH1_MII_TXD3 ETH1_RGMII_TXD3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(124, "PH12"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOH12"),
+ STM32_FUNCTION(3, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(4, "SPI6_MISO"),
+ STM32_FUNCTION(9, "TIM10_CH1"),
+ STM32_FUNCTION(11, "ETH1_MII_RXD2 ETH1_RGMII_RXD2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(125, "PH13"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOH13"),
+ STM32_FUNCTION(3, "SPI3_SCK I2S3_CK"),
+ STM32_FUNCTION(4, "SPI6_MOSI"),
+ STM32_FUNCTION(8, "TIM15_BKIN"),
+ STM32_FUNCTION(9, "TIM11_CH1"),
+ STM32_FUNCTION(11, "ETH1_MII_RXD3 ETH1_RGMII_RXD3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(128, "PI0"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOI0"),
+ STM32_FUNCTION(1, "TRACED14"),
+ STM32_FUNCTION(2, "HDP6"),
+ STM32_FUNCTION(4, "LPTIM1_IN1"),
+ STM32_FUNCTION(5, "SAI4_MCLK_B"),
+ STM32_FUNCTION(7, "USART1_CK"),
+ STM32_FUNCTION(9, "TIM8_BKIN"),
+ STM32_FUNCTION(14, "LCD_B3"),
+ STM32_FUNCTION(15, "DCMI_D11 PSSI_D11 DCMIPP_D11"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(129, "PI1"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOI1"),
+ STM32_FUNCTION(1, "TRACED15"),
+ STM32_FUNCTION(2, "HDP7"),
+ STM32_FUNCTION(3, "SPI7_NSS"),
+ STM32_FUNCTION(6, "MDF1_SDI6"),
+ STM32_FUNCTION(9, "TIM8_CH3N"),
+ STM32_FUNCTION(10, "I2C1_SDA"),
+ STM32_FUNCTION(11, "I3C1_SDA"),
+ STM32_FUNCTION(14, "LCD_B4"),
+ STM32_FUNCTION(15, "DCMI_D8 PSSI_D8 DCMIPP_D8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(130, "PI2"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOI2"),
+ STM32_FUNCTION(4, "LPTIM1_ETR"),
+ STM32_FUNCTION(5, "SAI4_SCK_B"),
+ STM32_FUNCTION(7, "USART1_RTS"),
+ STM32_FUNCTION(9, "TIM8_CH1"),
+ STM32_FUNCTION(14, "LCD_B5"),
+ STM32_FUNCTION(15, "DCMI_D13 PSSI_D13 DCMIPP_D13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(131, "PI3"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOI3"),
+ STM32_FUNCTION(4, "LPTIM1_IN2"),
+ STM32_FUNCTION(5, "SAI4_SD_B"),
+ STM32_FUNCTION(7, "USART1_CTS"),
+ STM32_FUNCTION(9, "TIM8_CH2"),
+ STM32_FUNCTION(14, "LCD_B6"),
+ STM32_FUNCTION(15, "PSSI_D14 DCMIPP_D14"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(132, "PI4"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOI4"),
+ STM32_FUNCTION(4, "LPTIM1_CH1"),
+ STM32_FUNCTION(5, "SAI4_FS_B"),
+ STM32_FUNCTION(9, "TIM8_CH3"),
+ STM32_FUNCTION(14, "LCD_B7"),
+ STM32_FUNCTION(15, "PSSI_D15 DCMIPP_D15"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(133, "PI5"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOI5"),
+ STM32_FUNCTION(3, "SPI5_MOSI"),
+ STM32_FUNCTION(4, "SPI1_MOSI I2S1_SDO"),
+ STM32_FUNCTION(6, "UART5_CTS"),
+ STM32_FUNCTION(7, "UART9_RX"),
+ STM32_FUNCTION(9, "TIM5_CH2"),
+ STM32_FUNCTION(14, "LCD_DE"),
+ STM32_FUNCTION(15, "DCMI_D1 PSSI_D1 DCMIPP_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(134, "PI6"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOI6"),
+ STM32_FUNCTION(2, "MCO1"),
+ STM32_FUNCTION(7, "USART3_TX"),
+ STM32_FUNCTION(8, "TIM2_ETR"),
+ STM32_FUNCTION(9, "TIM3_CH1"),
+ STM32_FUNCTION(14, "LCD_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(135, "PI7"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOI7"),
+ STM32_FUNCTION(7, "USART3_RX"),
+ STM32_FUNCTION(8, "TIM2_CH1"),
+ STM32_FUNCTION(9, "TIM3_CH2"),
+ STM32_FUNCTION(14, "LCD_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(136, "PI8"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOI8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(137, "PI9"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOI9"),
+ STM32_FUNCTION(2, "SPI7_MOSI"),
+ STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"),
+ STM32_FUNCTION(5, "FDCAN2_TX"),
+ STM32_FUNCTION(7, "UART9_CTS"),
+ STM32_FUNCTION(9, "TIM16_BKIN"),
+ STM32_FUNCTION(10, "SDVSEL2"),
+ STM32_FUNCTION(11, "FMC_NWAIT"),
+ STM32_FUNCTION(13, "DSI_TE"),
+ STM32_FUNCTION(14, "LCD_B0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(138, "PI10"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOI10"),
+ STM32_FUNCTION(2, "SAI1_SCK_A"),
+ STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
+ STM32_FUNCTION(4, "SPDIFRX1_IN0"),
+ STM32_FUNCTION(5, "FDCAN2_RX"),
+ STM32_FUNCTION(6, "MDF1_CCK0"),
+ STM32_FUNCTION(9, "TIM4_CH1"),
+ STM32_FUNCTION(10, "SDVSEL1"),
+ STM32_FUNCTION(13, "FMC_AD12 FMC_D12"),
+ STM32_FUNCTION(14, "DSI_TE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(139, "PI11"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOI11"),
+ STM32_FUNCTION(3, "I2S2_MCK"),
+ STM32_FUNCTION(6, "UART8_TX"),
+ STM32_FUNCTION(7, "UART9_RTS"),
+ STM32_FUNCTION(10, "TIM4_CH3"),
+ STM32_FUNCTION(11, "SDMMC3_D3"),
+ STM32_FUNCTION(12, "FMC_AD15 FMC_D15"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(140, "PI12"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOI12"),
+ STM32_FUNCTION(3, "SPI4_NSS"),
+ STM32_FUNCTION(8, "FDCAN3_RX"),
+ STM32_FUNCTION(9, "TIM11_CH1"),
+ STM32_FUNCTION(13, "FMC_A2"),
+ STM32_FUNCTION(14, "LCD_G0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(141, "PI13"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOI13"),
+ STM32_FUNCTION(3, "SPI4_MOSI"),
+ STM32_FUNCTION(5, "FDCAN2_RX"),
+ STM32_FUNCTION(9, "TIM10_CH1"),
+ STM32_FUNCTION(13, "FMC_A3"),
+ STM32_FUNCTION(14, "LCD_G1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(142, "PI14"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOI14"),
+ STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"),
+ STM32_FUNCTION(6, "MDF1_SDI1"),
+ STM32_FUNCTION(8, "TIM20_CH3"),
+ STM32_FUNCTION(9, "TIM1_CH3N"),
+ STM32_FUNCTION(11, "FMC_NWAIT"),
+ STM32_FUNCTION(13, "FMC_AD10 FMC_D10"),
+ STM32_FUNCTION(14, "DCMI_D4 PSSI_D4 DCMIPP_D4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(143, "PI15"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOI15"),
+ STM32_FUNCTION(3, "I2S2_MCK"),
+ STM32_FUNCTION(4, "UART4_RX"),
+ STM32_FUNCTION(6, "MDF1_CKI2"),
+ STM32_FUNCTION(8, "TIM20_BKIN2"),
+ STM32_FUNCTION(9, "TIM1_BKIN2"),
+ STM32_FUNCTION(10, "SDVSEL1"),
+ STM32_FUNCTION(11, "SDMMC3_CDIR"),
+ STM32_FUNCTION(14, "DCMI_D9 PSSI_D9 DCMIPP_D9"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(144, "PJ0"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOJ0"),
+ STM32_FUNCTION(3, "SPI5_MOSI"),
+ STM32_FUNCTION(5, "PCIE_CLKREQN"),
+ STM32_FUNCTION(6, "SAI4_D2"),
+ STM32_FUNCTION(7, "USART6_CTS"),
+ STM32_FUNCTION(10, "USBH_HS_VBUSEN"),
+ STM32_FUNCTION(12, "ETH2_PTP_AUX_TS"),
+ STM32_FUNCTION(13, "FMC_A11"),
+ STM32_FUNCTION(14, "ETH3_PPS_OUT"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(145, "PJ1"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOJ1"),
+ STM32_FUNCTION(7, "USART6_RX"),
+ STM32_FUNCTION(9, "TIM8_CH1N"),
+ STM32_FUNCTION(10, "I2C1_SCL"),
+ STM32_FUNCTION(11, "I3C1_SCL"),
+ STM32_FUNCTION(13, "FMC_A7"),
+ STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(146, "PJ2"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOJ2"),
+ STM32_FUNCTION(5, "SAI2_SD_B"),
+ STM32_FUNCTION(7, "UART9_RTS"),
+ STM32_FUNCTION(9, "TIM8_CH4N"),
+ STM32_FUNCTION(10, "USBH_HS_OVRCUR"),
+ STM32_FUNCTION(13, "FMC_A14"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(147, "PJ3"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOJ3"),
+ STM32_FUNCTION(3, "SPI5_NSS"),
+ STM32_FUNCTION(4, "SAI2_FS_A"),
+ STM32_FUNCTION(6, "SAI4_D1"),
+ STM32_FUNCTION(7, "USART6_RTS"),
+ STM32_FUNCTION(9, "TIM8_CH3"),
+ STM32_FUNCTION(13, "FMC_A10"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(148, "PJ4"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOJ4"),
+ STM32_FUNCTION(4, "SAI2_FS_B"),
+ STM32_FUNCTION(6, "MDF1_CCK1"),
+ STM32_FUNCTION(7, "USART6_CK"),
+ STM32_FUNCTION(9, "TIM8_CH4"),
+ STM32_FUNCTION(10, "I2C2_SMBA"),
+ STM32_FUNCTION(11, "I2C5_SMBA"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(149, "PJ5"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOJ5"),
+ STM32_FUNCTION(3, "SPI5_MISO"),
+ STM32_FUNCTION(4, "SAI2_SCK_B"),
+ STM32_FUNCTION(6, "SAI4_CK1"),
+ STM32_FUNCTION(7, "USART6_TX"),
+ STM32_FUNCTION(9, "TIM8_CH1"),
+ STM32_FUNCTION(13, "FMC_A8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(150, "PJ6"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOJ6"),
+ STM32_FUNCTION(3, "SPI7_MOSI"),
+ STM32_FUNCTION(5, "SAI4_SD_A"),
+ STM32_FUNCTION(7, "USART2_CK"),
+ STM32_FUNCTION(8, "TIM20_CH1N"),
+ STM32_FUNCTION(9, "TIM1_CH1"),
+ STM32_FUNCTION(10, "I2C6_SMBA"),
+ STM32_FUNCTION(14, "DCMI_D7 PSSI_D7 DCMIPP_D7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(151, "PJ7"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOJ7"),
+ STM32_FUNCTION(3, "SPI5_MISO"),
+ STM32_FUNCTION(5, "SAI2_MCLK_B"),
+ STM32_FUNCTION(6, "SAI4_D3"),
+ STM32_FUNCTION(7, "USART6_CK"),
+ STM32_FUNCTION(9, "TIM8_CH2N"),
+ STM32_FUNCTION(10, "I2C1_SMBA"),
+ STM32_FUNCTION(13, "FMC_A12"),
+ STM32_FUNCTION(15, "DCMI_D0 PSSI_D0 DCMIPP_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(152, "PJ8"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOJ8"),
+ STM32_FUNCTION(3, "SPI5_SCK"),
+ STM32_FUNCTION(6, "SAI4_CK2"),
+ STM32_FUNCTION(7, "USART6_RX"),
+ STM32_FUNCTION(9, "TIM8_CH2"),
+ STM32_FUNCTION(13, "FMC_A9"),
+ STM32_FUNCTION(15, "PSSI_D14 DCMIPP_D14"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(153, "PJ9"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOJ9"),
+ STM32_FUNCTION(3, "SPI4_RDY"),
+ STM32_FUNCTION(8, "TIM12_CH1"),
+ STM32_FUNCTION(9, "TIM8_BKIN"),
+ STM32_FUNCTION(13, "FMC_A5"),
+ STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(154, "PJ10"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOJ10"),
+ STM32_FUNCTION(8, "TIM12_CH2"),
+ STM32_FUNCTION(9, "TIM8_ETR"),
+ STM32_FUNCTION(10, "I2C1_SDA"),
+ STM32_FUNCTION(11, "I3C1_SDA"),
+ STM32_FUNCTION(13, "FMC_A6"),
+ STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(155, "PJ11"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOJ11"),
+ STM32_FUNCTION(3, "SPI5_RDY"),
+ STM32_FUNCTION(4, "SAI2_SCK_A"),
+ STM32_FUNCTION(6, "SAI4_D4"),
+ STM32_FUNCTION(7, "UART9_CTS"),
+ STM32_FUNCTION(9, "TIM8_CH3N"),
+ STM32_FUNCTION(13, "FMC_A13"),
+ STM32_FUNCTION(15, "DCMI_D12 PSSI_D12 DCMIPP_D12"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(156, "PJ12"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOJ12"),
+ STM32_FUNCTION(4, "SAI2_SD_A"),
+ STM32_FUNCTION(7, "UART9_RX"),
+ STM32_FUNCTION(8, "FDCAN1_TX"),
+ STM32_FUNCTION(9, "TIM8_BKIN2"),
+ STM32_FUNCTION(10, "I2C2_SCL"),
+ STM32_FUNCTION(11, "I3C2_SCL"),
+ STM32_FUNCTION(13, "FMC_A15"),
+ STM32_FUNCTION(15, "DCMI_D13 PSSI_D13 DCMIPP_D13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(157, "PJ13"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOJ13"),
+ STM32_FUNCTION(4, "SAI2_MCLK_A"),
+ STM32_FUNCTION(7, "UART9_TX"),
+ STM32_FUNCTION(8, "FDCAN1_RX"),
+ STM32_FUNCTION(9, "TIM10_CH1"),
+ STM32_FUNCTION(10, "I2C2_SDA"),
+ STM32_FUNCTION(11, "I3C2_SDA"),
+ STM32_FUNCTION(15, "PSSI_D15 DCMIPP_D15"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(158, "PJ14"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOJ14"),
+ STM32_FUNCTION(3, "SPI4_SCK"),
+ STM32_FUNCTION(8, "FDCAN3_TX"),
+ STM32_FUNCTION(13, "FMC_A1"),
+ STM32_FUNCTION(14, "LCD_R0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(159, "PJ15"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOJ15"),
+ STM32_FUNCTION(1, "TRACED7"),
+ STM32_FUNCTION(2, "HDP7"),
+ STM32_FUNCTION(3, "SPI4_MISO"),
+ STM32_FUNCTION(5, "FDCAN2_TX"),
+ STM32_FUNCTION(9, "TIM11_CH1"),
+ STM32_FUNCTION(13, "FMC_A4"),
+ STM32_FUNCTION(14, "LCD_R1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(160, "PK0"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOK0"),
+ STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"),
+ STM32_FUNCTION(4, "SPDIFRX1_IN2"),
+ STM32_FUNCTION(6, "MDF1_CCK0"),
+ STM32_FUNCTION(8, "TIM20_ETR"),
+ STM32_FUNCTION(9, "TIM1_ETR"),
+ STM32_FUNCTION(11, "SDMMC3_D123DIR"),
+ STM32_FUNCTION(13, "FMC_AD11 FMC_D11"),
+ STM32_FUNCTION(14, "DCMI_D11 PSSI_D11 DCMIPP_D11"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(161, "PK1"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOK1"),
+ STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"),
+ STM32_FUNCTION(6, "MDF1_SDI2"),
+ STM32_FUNCTION(8, "TIM20_BKIN"),
+ STM32_FUNCTION(9, "TIM1_BKIN"),
+ STM32_FUNCTION(10, "SDVSEL2"),
+ STM32_FUNCTION(11, "SDMMC3_D0DIR"),
+ STM32_FUNCTION(13, "FMC_AD13 FMC_D13"),
+ STM32_FUNCTION(14, "DCMI_D10 PSSI_D10 DCMIPP_D10"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(162, "PK2"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOK2"),
+ STM32_FUNCTION(3, "SPI7_NSS"),
+ STM32_FUNCTION(5, "SAI4_SCK_A"),
+ STM32_FUNCTION(7, "USART1_RTS"),
+ STM32_FUNCTION(8, "TIM20_CH2"),
+ STM32_FUNCTION(9, "TIM1_CH2N"),
+ STM32_FUNCTION(10, "I2C6_SDA"),
+ STM32_FUNCTION(13, "FMC_NCE3"),
+ STM32_FUNCTION(14, "DCMI_D6 PSSI_D6 DCMIPP_D6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(163, "PK3"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOK3"),
+ STM32_FUNCTION(3, "SPI7_RDY"),
+ STM32_FUNCTION(6, "MDF1_CKI1"),
+ STM32_FUNCTION(8, "TIM20_CH3N"),
+ STM32_FUNCTION(9, "TIM1_CH3"),
+ STM32_FUNCTION(13, "FMC_AD8 FMC_D8"),
+ STM32_FUNCTION(14, "DCMI_D3 PSSI_D3 DCMIPP_D3"),
+ STM32_FUNCTION(15, "FMC_NCE4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(164, "PK4"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOK4"),
+ STM32_FUNCTION(3, "SPI7_MISO"),
+ STM32_FUNCTION(4, "UART4_TX"),
+ STM32_FUNCTION(5, "SAI4_FS_A"),
+ STM32_FUNCTION(8, "TIM20_CH1"),
+ STM32_FUNCTION(9, "TIM1_CH1N"),
+ STM32_FUNCTION(11, "SDMMC3_CKIN"),
+ STM32_FUNCTION(13, "FMC_AD9 FMC_D9"),
+ STM32_FUNCTION(14, "DCMI_D8 PSSI_D8 DCMIPP_D8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(165, "PK5"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOK5"),
+ STM32_FUNCTION(3, "SPI2_RDY"),
+ STM32_FUNCTION(6, "MDF1_CKI0"),
+ STM32_FUNCTION(7, "USART1_TX"),
+ STM32_FUNCTION(8, "TIM20_CH4N"),
+ STM32_FUNCTION(9, "TIM1_CH4"),
+ STM32_FUNCTION(11, "I2C5_SCL"),
+ STM32_FUNCTION(13, "FMC_AD5 FMC_D5"),
+ STM32_FUNCTION(14, "DCMI_D1 PSSI_D1 DCMIPP_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(166, "PK6"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOK6"),
+ STM32_FUNCTION(3, "SPI7_SCK"),
+ STM32_FUNCTION(5, "SAI4_MCLK_A"),
+ STM32_FUNCTION(7, "USART1_CTS"),
+ STM32_FUNCTION(8, "TIM20_CH2N"),
+ STM32_FUNCTION(9, "TIM1_CH2"),
+ STM32_FUNCTION(10, "I2C6_SCL"),
+ STM32_FUNCTION(12, "FMC_AD14 FMC_D14"),
+ STM32_FUNCTION(13, "FMC_AD7 FMC_D7"),
+ STM32_FUNCTION(14, "DCMI_D5 PSSI_D5 DCMIPP_D5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(167, "PK7"),
+ STM32MP_PKG_AI,
+ STM32_FUNCTION(0, "GPIOK7"),
+ STM32_FUNCTION(6, "MDF1_SDI0"),
+ STM32_FUNCTION(7, "USART1_RX"),
+ STM32_FUNCTION(8, "TIM20_CH4"),
+ STM32_FUNCTION(9, "TIM1_CH4N"),
+ STM32_FUNCTION(11, "I2C5_SDA"),
+ STM32_FUNCTION(12, "FMC_NCE4"),
+ STM32_FUNCTION(13, "FMC_AD6 FMC_D6"),
+ STM32_FUNCTION(14, "DCMI_D2 PSSI_D2 DCMIPP_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+};
+
+static const struct stm32_desc_pin stm32mp257_z_pins[] = {
+ STM32_PIN_PKG(
+ PINCTRL_PIN(400, "PZ0"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOZ0"),
+ STM32_FUNCTION(3, "LPTIM3_IN1"),
+ STM32_FUNCTION(4, "SPI8_MOSI"),
+ STM32_FUNCTION(5, "TIM8_CH1"),
+ STM32_FUNCTION(7, "LPUART1_TX"),
+ STM32_FUNCTION(8, "LPTIM5_OUT"),
+ STM32_FUNCTION(9, "I2C8_SDA"),
+ STM32_FUNCTION(11, "LPTIM3_CH2"),
+ STM32_FUNCTION(12, "I3C4_SDA"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(401, "PZ1"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOZ1"),
+ STM32_FUNCTION(3, "LPTIM3_CH1"),
+ STM32_FUNCTION(4, "SPI8_MISO"),
+ STM32_FUNCTION(5, "TIM8_CH2"),
+ STM32_FUNCTION(7, "LPUART1_RX"),
+ STM32_FUNCTION(8, "LPTIM5_ETR"),
+ STM32_FUNCTION(9, "I2C8_SCL"),
+ STM32_FUNCTION(10, "I2C8_SMBA"),
+ STM32_FUNCTION(12, "I3C4_SCL"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(402, "PZ2"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOZ2"),
+ STM32_FUNCTION(3, "LPTIM3_CH1"),
+ STM32_FUNCTION(4, "SPI8_SCK"),
+ STM32_FUNCTION(6, "ADF1_CCK0"),
+ STM32_FUNCTION(7, "LPUART1_RTS"),
+ STM32_FUNCTION(8, "LPTIM4_ETR"),
+ STM32_FUNCTION(9, "I2C8_SCL"),
+ STM32_FUNCTION(12, "I3C4_SCL"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(403, "PZ3"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOZ3"),
+ STM32_FUNCTION(1, "DBTRGI"),
+ STM32_FUNCTION(2, "DBTRGO"),
+ STM32_FUNCTION(3, "LPTIM3_ETR"),
+ STM32_FUNCTION(4, "SPI8_NSS"),
+ STM32_FUNCTION(5, "MDF1_SDI5"),
+ STM32_FUNCTION(6, "ADF1_SDI0"),
+ STM32_FUNCTION(7, "LPUART1_CTS"),
+ STM32_FUNCTION(8, "LPTIM4_IN1"),
+ STM32_FUNCTION(9, "I2C8_SDA"),
+ STM32_FUNCTION(11, "LPTIM4_CH2"),
+ STM32_FUNCTION(12, "I3C4_SDA"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(404, "PZ4"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOZ4"),
+ STM32_FUNCTION(1, "DBTRGI"),
+ STM32_FUNCTION(2, "DBTRGO"),
+ STM32_FUNCTION(3, "MCO2"),
+ STM32_FUNCTION(4, "SPI8_RDY"),
+ STM32_FUNCTION(5, "MDF1_CCK1"),
+ STM32_FUNCTION(6, "ADF1_CCK1"),
+ STM32_FUNCTION(7, "LPUART1_RX"),
+ STM32_FUNCTION(8, "LPTIM4_CH1"),
+ STM32_FUNCTION(9, "I2C8_SCL"),
+ STM32_FUNCTION(12, "I3C4_SCL"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(405, "PZ5"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOZ5"),
+ STM32_FUNCTION(2, "MCO1"),
+ STM32_FUNCTION(3, "LPTIM3_ETR"),
+ STM32_FUNCTION(4, "SPI8_SCK"),
+ STM32_FUNCTION(6, "ADF1_CCK0"),
+ STM32_FUNCTION(7, "LPUART1_RTS"),
+ STM32_FUNCTION(8, "LPTIM5_IN1"),
+ STM32_FUNCTION(11, "LPTIM4_CH2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(406, "PZ6"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOZ6"),
+ STM32_FUNCTION(1, "DBTRGI"),
+ STM32_FUNCTION(2, "DBTRGO"),
+ STM32_FUNCTION(4, "SPI8_NSS"),
+ STM32_FUNCTION(5, "TIM8_CH3"),
+ STM32_FUNCTION(6, "ADF1_SDI0"),
+ STM32_FUNCTION(7, "LPUART1_CTS"),
+ STM32_FUNCTION(8, "LPTIM5_OUT"),
+ STM32_FUNCTION(11, "LPTIM4_CH2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(407, "PZ7"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOZ7"),
+ STM32_FUNCTION(4, "SPI8_MOSI"),
+ STM32_FUNCTION(5, "MDF1_CCK1"),
+ STM32_FUNCTION(6, "ADF1_CCK1"),
+ STM32_FUNCTION(7, "LPUART1_TX"),
+ STM32_FUNCTION(8, "LPTIM5_IN1"),
+ STM32_FUNCTION(11, "LPTIM3_CH2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(408, "PZ8"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOZ8"),
+ STM32_FUNCTION(3, "LPTIM3_IN1"),
+ STM32_FUNCTION(4, "SPI8_MISO"),
+ STM32_FUNCTION(5, "MDF1_SDI5"),
+ STM32_FUNCTION(6, "ADF1_SDI0"),
+ STM32_FUNCTION(7, "LPUART1_RX"),
+ STM32_FUNCTION(8, "LPTIM4_CH1"),
+ STM32_FUNCTION(9, "I2C8_SMBA"),
+ STM32_FUNCTION(10, "LPTIM5_ETR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN_PKG(
+ PINCTRL_PIN(409, "PZ9"),
+ STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
+ STM32_FUNCTION(0, "GPIOZ9"),
+ STM32_FUNCTION(2, "MCO2"),
+ STM32_FUNCTION(4, "SPI8_RDY"),
+ STM32_FUNCTION(5, "MDF1_CKI5"),
+ STM32_FUNCTION(7, "LPUART1_TX"),
+ STM32_FUNCTION(8, "LPTIM4_ETR"),
+ STM32_FUNCTION(9, "I2C8_SDA"),
+ STM32_FUNCTION(11, "LPTIM3_CH2"),
+ STM32_FUNCTION(12, "I3C4_SDA"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+};
+
+static struct stm32_pinctrl_match_data stm32mp257_match_data = {
+ .pins = stm32mp257_pins,
+ .npins = ARRAY_SIZE(stm32mp257_pins),
+};
+
+static struct stm32_pinctrl_match_data stm32mp257_z_match_data = {
+ .pins = stm32mp257_z_pins,
+ .npins = ARRAY_SIZE(stm32mp257_z_pins),
+};
+
+static const struct of_device_id stm32mp257_pctrl_match[] = {
+ {
+ .compatible = "st,stm32mp257-pinctrl",
+ .data = &stm32mp257_match_data,
+ },
+ {
+ .compatible = "st,stm32mp257-z-pinctrl",
+ .data = &stm32mp257_z_match_data,
+ },
+ { }
+};
+
+static const struct dev_pm_ops stm32_pinctrl_dev_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, stm32_pinctrl_resume)
+};
+
+static struct platform_driver stm32mp257_pinctrl_driver = {
+ .probe = stm32_pctl_probe,
+ .driver = {
+ .name = "stm32mp257-pinctrl",
+ .of_match_table = stm32mp257_pctrl_match,
+ .pm = &stm32_pinctrl_dev_pm_ops,
+ },
+};
+
+static int __init stm32mp257_pinctrl_init(void)
+{
+ return platform_driver_register(&stm32mp257_pinctrl_driver);
+}
+arch_initcall(stm32mp257_pinctrl_init);
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 03/11] dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon
2023-05-29 16:20 [PATCH 00/11] Add STM32MP25 support Alexandre Torgue
2023-05-29 16:20 ` [PATCH 01/11] dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages Alexandre Torgue
2023-05-29 16:20 ` [PATCH 02/11] pinctrl: stm32: add stm32mp257 pinctrl support Alexandre Torgue
@ 2023-05-29 16:20 ` Alexandre Torgue
[not found] ` <d35fdc37-a793-3109-1474-065dffb03069@linaro.org>
2023-06-02 13:14 ` Krzysztof Kozlowski
2023-05-29 16:20 ` [PATCH 04/11] dt-bindings: stm32: add st,stm32mp25 compatibles to the stm32 family Alexandre Torgue
` (8 subsequent siblings)
11 siblings, 2 replies; 28+ messages in thread
From: Alexandre Torgue @ 2023-05-29 16:20 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc
Cc: linux-arm-kernel, devicetree, Alexandre Torgue, linux-stm32,
linux-kernel, linux-gpio
From: Patrick Delaunay <patrick.delaunay@foss.st.com>
Add the new syscon compatible for STM32MP25 syscfg = "st,stm32mp25-syscfg".
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
index ad8e51aa01b0..9ed5b121cea9 100644
--- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
@@ -16,6 +16,7 @@ properties:
- items:
- enum:
- st,stm32mp157-syscfg
+ - st,stm32mp25-syscfg
- st,stm32mp151-pwr-mcu
- st,stm32-syscfg
- st,stm32-power-config
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 04/11] dt-bindings: stm32: add st,stm32mp25 compatibles to the stm32 family
2023-05-29 16:20 [PATCH 00/11] Add STM32MP25 support Alexandre Torgue
` (2 preceding siblings ...)
2023-05-29 16:20 ` [PATCH 03/11] dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon Alexandre Torgue
@ 2023-05-29 16:20 ` Alexandre Torgue
2023-05-29 18:05 ` Conor Dooley
2023-05-29 16:20 ` [PATCH 05/11] arm64: introduce STM32 family on Armv8 architecture Alexandre Torgue
` (7 subsequent siblings)
11 siblings, 1 reply; 28+ messages in thread
From: Alexandre Torgue @ 2023-05-29 16:20 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc
Cc: linux-arm-kernel, devicetree, Alexandre Torgue, linux-stm32,
linux-kernel, linux-gpio
STM32 family is extended by the addition of the STM32MP25 SoCs. It is composed
of 4 SoCs: STM32MP251, STM32MP253, STM32MP255 and STM32MP257.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
index 4af5b8f4f803..7d7ca33d2e61 100644
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -161,6 +161,15 @@ properties:
- const: phytec,phycore-stm32mp157c-som
- const: st,stm32mp157
+ - items:
+ - const: st,stm32mp251
+ - items:
+ - const: st,stm32mp253
+ - items:
+ - const: st,stm32mp255
+ - items:
+ - const: st,stm32mp257
+
additionalProperties: true
...
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 05/11] arm64: introduce STM32 family on Armv8 architecture
2023-05-29 16:20 [PATCH 00/11] Add STM32MP25 support Alexandre Torgue
` (3 preceding siblings ...)
2023-05-29 16:20 ` [PATCH 04/11] dt-bindings: stm32: add st,stm32mp25 compatibles to the stm32 family Alexandre Torgue
@ 2023-05-29 16:20 ` Alexandre Torgue
2023-05-29 16:20 ` [PATCH 06/11] arm64: dts: st: introduce stm32mp25 SoCs family Alexandre Torgue
` (6 subsequent siblings)
11 siblings, 0 replies; 28+ messages in thread
From: Alexandre Torgue @ 2023-05-29 16:20 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc
Cc: linux-arm-kernel, devicetree, Alexandre Torgue, linux-stm32,
linux-kernel, linux-gpio
Add a dedicated ARCH_STM32 for STM32 SoCs config. First STM32 Armv8 SoC
family is the STM32MP25 which is composed of STM32MP251, STM32MP253,
STM32MP255, STM32MP257 SoCs.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 89a0b13b058d..b1818d100d88 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -277,6 +277,20 @@ config ARCH_INTEL_SOCFPGA
Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform,
Agilex and eASIC N5X.
+config ARCH_STM32
+ bool "STMicroelectronics STM32 SoC Family"
+ select GPIOLIB
+ select PINCTRL
+ select PINCTRL_STM32MP257
+ select ARM_SMC_MBOX
+ select ARM_SCMI_PROTOCOL
+ select COMMON_CLK_SCMI
+ help
+ This enables support for ARMv8 based STMicroelectronics
+ STM32 family, including:
+ - STM32MP25:
+ - STM32MP251, STM32MP253, STM32MP255 and STM32MP257.
+
config ARCH_SYNQUACER
bool "Socionext SynQuacer SoC Family"
select IRQ_FASTEOI_HIERARCHY_HANDLERS
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 06/11] arm64: dts: st: introduce stm32mp25 SoCs family
2023-05-29 16:20 [PATCH 00/11] Add STM32MP25 support Alexandre Torgue
` (4 preceding siblings ...)
2023-05-29 16:20 ` [PATCH 05/11] arm64: introduce STM32 family on Armv8 architecture Alexandre Torgue
@ 2023-05-29 16:20 ` Alexandre Torgue
2023-05-29 16:20 ` [PATCH 07/11] arm64: dts: st: introduce stm32mp25 pinctrl files Alexandre Torgue
` (5 subsequent siblings)
11 siblings, 0 replies; 28+ messages in thread
From: Alexandre Torgue @ 2023-05-29 16:20 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc
Cc: linux-arm-kernel, devicetree, Alexandre Torgue, linux-stm32,
linux-kernel, linux-gpio
STM32MP25 family is composed of 4 SoCs defined as following:
-STM32MP251: common part composed of 1*Cortex-A35, common peripherals like
SDMMC, UART, SPI, I2C, PCIe, USB3, parallel and DSI display, 1*ETH ...
-STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD and
LVDS display.
-STM32MP255: STM32MP253 + GPU/AI and video encode/decode.
-STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports).
A second diversity layer exists for security features/ A35 frequency:
-STM32MP25xY, "Y" gives information:
-Y = A means A35@1.2GHz + no cryp IP and no secure boot.
-Y = C means A35@1.2GHz + cryp IP and secure boot.
-Y = D means A35@1.5GHz + no cryp IP and no secure boot.
-Y = F means A35@1.5GHz + cryp IP and secure boot.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
new file mode 100644
index 000000000000..5268a4321841
--- /dev/null
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -0,0 +1,279 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a35";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a35-pmu";
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ interrupt-parent = <&intc>;
+ };
+
+ clocks {
+ ck_flexgen_08: ck-flexgen-08 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+
+ ck_flexgen_51: ck-flexgen-51 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+
+ ck_icn_ls_mcu: ck-icn-ls-mcu {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ scmi {
+ compatible = "linaro,scmi-optee";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ linaro,optee-channel-id = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_reset: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+ };
+
+ intc: interrupt-controller@4ac00000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ interrupt-controller;
+ reg = <0x0 0x4ac10000 0x0 0x1000>,
+ <0x0 0x4ac20000 0x0 0x2000>,
+ <0x0 0x4ac40000 0x0 0x2000>,
+ <0x0 0x4ac60000 0x0 0x2000>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ always-on;
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges = <0x0 0x0 0x0 0x80000000>;
+
+ rifsc: rifsc-bus@42080000 {
+ compatible = "simple-bus";
+ reg = <0x42080000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usart2: serial@400e0000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x400e0000 0x400>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ck_flexgen_08>;
+ status = "disabled";
+ };
+ };
+
+ syscfg: syscon@44230000 {
+ compatible = "st,stm32mp25-syscfg", "syscon";
+ reg = <0x44230000 0x10000>;
+ };
+
+ pinctrl: pinctrl@44240000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp257-pinctrl";
+ ranges = <0 0x44240000 0xa0400>;
+ pins-are-numbered;
+
+ gpioa: gpio@44240000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOA";
+ status = "disabled";
+ };
+
+ gpiob: gpio@44250000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x10000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOB";
+ status = "disabled";
+ };
+
+ gpioc: gpio@44260000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x20000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOC";
+ status = "disabled";
+ };
+
+ gpiod: gpio@44270000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x30000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOD";
+ status = "disabled";
+ };
+
+ gpioe: gpio@44280000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOE";
+ status = "disabled";
+ };
+
+ gpiof: gpio@44290000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x50000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOF";
+ status = "disabled";
+ };
+
+ gpiog: gpio@442a0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x60000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOG";
+ status = "disabled";
+ };
+
+ gpioh: gpio@442b0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x70000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOH";
+ status = "disabled";
+ };
+
+ gpioi: gpio@442c0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x80000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOI";
+ status = "disabled";
+ };
+
+ gpioj: gpio@442d0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x90000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOJ";
+ status = "disabled";
+ };
+
+ gpiok: gpio@442e0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0xa0000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOK";
+ status = "disabled";
+ };
+ };
+
+ pinctrl_z: pinctrl@46200000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp257-z-pinctrl";
+ ranges = <0 0x46200000 0x400>;
+ pins-are-numbered;
+
+ gpioz: gpio@46200000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOZ";
+ st,bank-ioport = <11>;
+ status = "disabled";
+ };
+
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi
new file mode 100644
index 000000000000..af48e82efe8a
--- /dev/null
+++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include "stm32mp251.dtsi"
+
+/ {
+ cpus {
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a35";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ };
+ };
+
+ arm-pmu {
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi
new file mode 100644
index 000000000000..e6fa596211f5
--- /dev/null
+++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include "stm32mp253.dtsi"
+
+/ {
+};
diff --git a/arch/arm64/boot/dts/st/stm32mp257.dtsi b/arch/arm64/boot/dts/st/stm32mp257.dtsi
new file mode 100644
index 000000000000..5c5000d3d9db
--- /dev/null
+++ b/arch/arm64/boot/dts/st/stm32mp257.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include "stm32mp255.dtsi"
+
+/ {
+};
diff --git a/arch/arm64/boot/dts/st/stm32mp25xc.dtsi b/arch/arm64/boot/dts/st/stm32mp25xc.dtsi
new file mode 100644
index 000000000000..5e83a6926485
--- /dev/null
+++ b/arch/arm64/boot/dts/st/stm32mp25xc.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+};
diff --git a/arch/arm64/boot/dts/st/stm32mp25xf.dtsi b/arch/arm64/boot/dts/st/stm32mp25xf.dtsi
new file mode 100644
index 000000000000..5e83a6926485
--- /dev/null
+++ b/arch/arm64/boot/dts/st/stm32mp25xf.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 07/11] arm64: dts: st: introduce stm32mp25 pinctrl files
2023-05-29 16:20 [PATCH 00/11] Add STM32MP25 support Alexandre Torgue
` (5 preceding siblings ...)
2023-05-29 16:20 ` [PATCH 06/11] arm64: dts: st: introduce stm32mp25 SoCs family Alexandre Torgue
@ 2023-05-29 16:20 ` Alexandre Torgue
2023-05-29 16:20 ` [PATCH 08/11] dt-bindings: stm32: document stm32mp257f-ev1 board Alexandre Torgue
` (4 subsequent siblings)
11 siblings, 0 replies; 28+ messages in thread
From: Alexandre Torgue @ 2023-05-29 16:20 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc
Cc: linux-arm-kernel, devicetree, Alexandre Torgue, linux-stm32,
linux-kernel, linux-gpio
Three packages exist for stm32mp25 dies. As ball-out is different between
them, this patch covers those differences by introducing dedicated pinctrl
dtsi files. Each dtsi pinctrl package file describes the package ball-out
through gpio-ranges.
Available packages are:
STM32MP25xAI: 18*18/FCBGA 172 ios
STM32MP25xAK: 14*14/FCBGA 144 ios
STM32MP25xAL: 10*10/TFBGA 144 ios
It includes also the common file used for pin groups definition.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
new file mode 100644
index 000000000000..5bd27767fbf5
--- /dev/null
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
diff --git a/arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi
new file mode 100644
index 000000000000..abdbc7aebc7f
--- /dev/null
+++ b/arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AI>;
+
+ gpioa: gpio@44240000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@44250000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@44260000 {
+ status = "okay";
+ ngpios = <14>;
+ gpio-ranges = <&pinctrl 0 32 14>;
+ };
+
+ gpiod: gpio@44270000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@44280000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@44290000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@442a0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@442b0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 2 114 12>;
+ };
+
+ gpioi: gpio@442c0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ gpioj: gpio@442d0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 144 16>;
+ };
+
+ gpiok: gpio@442e0000 {
+ status = "okay";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl 0 160 8>;
+ };
+};
+
+&pinctrl_z {
+ gpioz: gpio@46200000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl_z 0 400 10>;
+ };
+};
diff --git a/arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi
new file mode 100644
index 000000000000..2e0d4d349d14
--- /dev/null
+++ b/arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AK>;
+
+ gpioa: gpio@44240000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@44250000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@44260000 {
+ status = "okay";
+ ngpios = <14>;
+ gpio-ranges = <&pinctrl 0 32 14>;
+ };
+
+ gpiod: gpio@44270000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@44280000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@44290000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@442a0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@442b0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 2 114 12>;
+ };
+
+ gpioi: gpio@442c0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 0 128 12>;
+ };
+};
+
+&pinctrl_z {
+ gpioz: gpio@46200000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl_z 0 400 10>;
+ };
+};
diff --git a/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi
new file mode 100644
index 000000000000..2406e972554c
--- /dev/null
+++ b/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AL>;
+
+ gpioa: gpio@44240000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@44250000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@44260000 {
+ status = "okay";
+ ngpios = <14>;
+ gpio-ranges = <&pinctrl 0 32 14>;
+ };
+
+ gpiod: gpio@44270000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@44280000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@44290000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@442a0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@442b0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 2 114 12>;
+ };
+
+ gpioi: gpio@442c0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 0 128 12>;
+ };
+};
+
+&pinctrl_z {
+ gpioz: gpio@46200000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl_z 0 400 10>;
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 08/11] dt-bindings: stm32: document stm32mp257f-ev1 board
2023-05-29 16:20 [PATCH 00/11] Add STM32MP25 support Alexandre Torgue
` (6 preceding siblings ...)
2023-05-29 16:20 ` [PATCH 07/11] arm64: dts: st: introduce stm32mp25 pinctrl files Alexandre Torgue
@ 2023-05-29 16:20 ` Alexandre Torgue
2023-05-29 18:06 ` Conor Dooley
2023-05-29 16:20 ` [PATCH 09/11] arm64: dts: st: add stm32mp257f-ev1 board support Alexandre Torgue
` (3 subsequent siblings)
11 siblings, 1 reply; 28+ messages in thread
From: Alexandre Torgue @ 2023-05-29 16:20 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc
Cc: linux-arm-kernel, devicetree, Alexandre Torgue, linux-stm32,
linux-kernel, linux-gpio
Add new entry for stm32mp257f-ev1 board.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
index 7d7ca33d2e61..e5b929a52646 100644
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -167,7 +167,10 @@ properties:
- const: st,stm32mp253
- items:
- const: st,stm32mp255
- - items:
+ - description: ST STM32MP257 based Boards
+ items:
+ - enum:
+ - st,stm32mp257f-ev1
- const: st,stm32mp257
additionalProperties: true
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 09/11] arm64: dts: st: add stm32mp257f-ev1 board support
2023-05-29 16:20 [PATCH 00/11] Add STM32MP25 support Alexandre Torgue
` (7 preceding siblings ...)
2023-05-29 16:20 ` [PATCH 08/11] dt-bindings: stm32: document stm32mp257f-ev1 board Alexandre Torgue
@ 2023-05-29 16:20 ` Alexandre Torgue
2023-05-29 16:20 ` [PATCH 10/11] arm64: defconfig: enable ARCH_STM32 and STM32 serial driver Alexandre Torgue
` (2 subsequent siblings)
11 siblings, 0 replies; 28+ messages in thread
From: Alexandre Torgue @ 2023-05-29 16:20 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc
Cc: linux-arm-kernel, devicetree, Alexandre Torgue, linux-stm32,
linux-kernel, linux-gpio
Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI SoC,
with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC,
SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 7b107fa7414b..30dd6347a929 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -27,6 +27,7 @@ subdir-y += renesas
subdir-y += rockchip
subdir-y += socionext
subdir-y += sprd
+subdir-y += st
subdir-y += synaptics
subdir-y += tesla
subdir-y += ti
diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makefile
new file mode 100644
index 000000000000..881fe1296c58
--- /dev/null
+++ b/arch/arm64/boot/dts/st/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+dtb-$(CONFIG_ARCH_STM32) += stm32mp257f-ev1.dtb
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index 5bd27767fbf5..d34a1d5e79c0 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -5,3 +5,34 @@
*/
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+&pinctrl {
+ usart2_pins_a: usart2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_idle_pins_a: usart2-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_sleep_pins_a: usart2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
new file mode 100644
index 000000000000..39b4726cc098
--- /dev/null
+++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp257.dtsi"
+#include "stm32mp25xf.dtsi"
+#include "stm32mp25-pinctrl.dtsi"
+#include "stm32mp25xxai-pinctrl.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board";
+ compatible = "st,stm32mp257f-ev1", "st,stm32mp257";
+
+ aliases {
+ serial0 = &usart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x1 0x0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ fw@80000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x80000000 0x0 0x4000000>;
+ no-map;
+ };
+ };
+};
+
+&usart2 {
+ pinctrl-names = "default", "idle", "sleep";
+ pinctrl-0 = <&usart2_pins_a>;
+ pinctrl-1 = <&usart2_idle_pins_a>;
+ pinctrl-2 = <&usart2_sleep_pins_a>;
+ status = "okay";
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 10/11] arm64: defconfig: enable ARCH_STM32 and STM32 serial driver
2023-05-29 16:20 [PATCH 00/11] Add STM32MP25 support Alexandre Torgue
` (8 preceding siblings ...)
2023-05-29 16:20 ` [PATCH 09/11] arm64: dts: st: add stm32mp257f-ev1 board support Alexandre Torgue
@ 2023-05-29 16:20 ` Alexandre Torgue
2023-05-29 16:20 ` [PATCH 11/11] MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE Alexandre Torgue
2023-05-30 12:39 ` [PATCH 00/11] Add STM32MP25 support Linus Walleij
11 siblings, 0 replies; 28+ messages in thread
From: Alexandre Torgue @ 2023-05-29 16:20 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc
Cc: linux-arm-kernel, devicetree, Alexandre Torgue, linux-stm32,
linux-kernel, linux-gpio
Allow a basic boot on STM32MP257 SoC.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index a24609e14d50..2e0b4ffcb2ce 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -58,6 +58,7 @@ CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARCH_SEATTLE=y
CONFIG_ARCH_INTEL_SOCFPGA=y
+CONFIG_ARCH_STM32=y
CONFIG_ARCH_SYNQUACER=y
CONFIG_ARCH_TEGRA=y
CONFIG_ARCH_TESLA_FSD=y
@@ -461,6 +462,8 @@ CONFIG_SERIAL_FSL_LPUART=y
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
CONFIG_SERIAL_FSL_LINFLEXUART=y
CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
+CONFIG_SERIAL_STM32=y
+CONFIG_SERIAL_STM32_CONSOLE=y
CONFIG_SERIAL_MVEBU_UART=y
CONFIG_SERIAL_OWL=y
CONFIG_SERIAL_DEV_BUS=y
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 11/11] MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE
2023-05-29 16:20 [PATCH 00/11] Add STM32MP25 support Alexandre Torgue
` (9 preceding siblings ...)
2023-05-29 16:20 ` [PATCH 10/11] arm64: defconfig: enable ARCH_STM32 and STM32 serial driver Alexandre Torgue
@ 2023-05-29 16:20 ` Alexandre Torgue
2023-05-30 12:39 ` [PATCH 00/11] Add STM32MP25 support Linus Walleij
11 siblings, 0 replies; 28+ messages in thread
From: Alexandre Torgue @ 2023-05-29 16:20 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc
Cc: linux-arm-kernel, devicetree, Alexandre Torgue, linux-stm32,
linux-kernel, linux-gpio
STM32 SoCs based on Armv8 have been added to the STM32 family. Those new
SoCs are maintained as legacy STM32 MPU.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index 7e0b87d5aa2e..06759396e220 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2849,6 +2849,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git stm32-nex
F: arch/arm/boot/dts/stm32*
F: arch/arm/mach-stm32/
F: drivers/clocksource/armv7m_systick.c
+F: arch/arm64/boot/dts/st/
N: stm32
N: stm
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 01/11] dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages
2023-05-29 16:20 ` [PATCH 01/11] dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages Alexandre Torgue
@ 2023-05-29 18:00 ` Conor Dooley
0 siblings, 0 replies; 28+ messages in thread
From: Conor Dooley @ 2023-05-29 18:00 UTC (permalink / raw)
To: Alexandre Torgue
Cc: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc,
linux-arm-kernel, devicetree, linux-stm32, linux-kernel,
linux-gpio
[-- Attachment #1: Type: text/plain, Size: 1823 bytes --]
On Mon, May 29, 2023 at 06:20:24PM +0200, Alexandre Torgue wrote:
> Add support for st,stm32mp257-pinctrl and st,stm32mp257-z-pinctrl.
> Add packages AI, AK and AL (values : 0x100, 0x400 and 0x800)
>
> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
> index 1ab0f8dde477..2120ef71a78d 100644
> --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
> @@ -27,6 +27,8 @@ properties:
> - st,stm32mp135-pinctrl
> - st,stm32mp157-pinctrl
> - st,stm32mp157-z-pinctrl
> + - st,stm32mp257-pinctrl
> + - st,stm32mp257-z-pinctrl
>
> '#address-cells':
> const: 1
> @@ -56,7 +58,7 @@ properties:
> Indicates the SOC package used.
> More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
> $ref: /schemas/types.yaml#/definitions/uint32
> - enum: [1, 2, 4, 8]
> + enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800]
>
> patternProperties:
> '^gpio@[0-9a-f]*$':
> diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h
> index e6fb8ada3f4d..28ad0235086a 100644
> --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h
> +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h
> @@ -37,6 +37,9 @@
> #define STM32MP_PKG_AB 0x2
> #define STM32MP_PKG_AC 0x4
> #define STM32MP_PKG_AD 0x8
> +#define STM32MP_PKG_AI 0x100
> +#define STM32MP_PKG_AK 0x400
> +#define STM32MP_PKG_AL 0x800
>
> #endif /* _DT_BINDINGS_STM32_PINFUNC_H */
>
> --
> 2.17.1
>
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 02/11] pinctrl: stm32: add stm32mp257 pinctrl support
2023-05-29 16:20 ` [PATCH 02/11] pinctrl: stm32: add stm32mp257 pinctrl support Alexandre Torgue
@ 2023-05-29 18:04 ` Conor Dooley
2023-05-30 8:38 ` Alexandre TORGUE
0 siblings, 1 reply; 28+ messages in thread
From: Conor Dooley @ 2023-05-29 18:04 UTC (permalink / raw)
To: Alexandre Torgue
Cc: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc,
linux-arm-kernel, devicetree, linux-stm32, linux-kernel,
linux-gpio
[-- Attachment #1: Type: text/plain, Size: 640 bytes --]
On Mon, May 29, 2023 at 06:20:25PM +0200, Alexandre Torgue wrote:
> Add stm32mp257 pinctrl support.
> diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h
> index e0c31c4c8bca..5e5de92ddd58 100644
> --- a/drivers/pinctrl/stm32/pinctrl-stm32.h
> +++ b/drivers/pinctrl/stm32/pinctrl-stm32.h
> @@ -24,6 +24,9 @@
> #define STM32MP_PKG_AB BIT(1)
> #define STM32MP_PKG_AC BIT(2)
> #define STM32MP_PKG_AD BIT(3)
> +#define STM32MP_PKG_AI BIT(8)
> +#define STM32MP_PKG_AK BIT(10)
> +#define STM32MP_PKG_AL BIT(11)
Mainly out of curiosity, why have you go duplicate defines for these?
Cheers,
Conor.
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 04/11] dt-bindings: stm32: add st,stm32mp25 compatibles to the stm32 family
2023-05-29 16:20 ` [PATCH 04/11] dt-bindings: stm32: add st,stm32mp25 compatibles to the stm32 family Alexandre Torgue
@ 2023-05-29 18:05 ` Conor Dooley
2023-05-30 8:39 ` Alexandre TORGUE
0 siblings, 1 reply; 28+ messages in thread
From: Conor Dooley @ 2023-05-29 18:05 UTC (permalink / raw)
To: Alexandre Torgue
Cc: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc,
linux-arm-kernel, devicetree, linux-stm32, linux-kernel,
linux-gpio
[-- Attachment #1: Type: text/plain, Size: 1187 bytes --]
On Mon, May 29, 2023 at 06:20:27PM +0200, Alexandre Torgue wrote:
> STM32 family is extended by the addition of the STM32MP25 SoCs. It is composed
> of 4 SoCs: STM32MP251, STM32MP253, STM32MP255 and STM32MP257.
>
> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
>
> diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
> index 4af5b8f4f803..7d7ca33d2e61 100644
> --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
> +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
> @@ -161,6 +161,15 @@ properties:
> - const: phytec,phycore-stm32mp157c-som
> - const: st,stm32mp157
>
> + - items:
> + - const: st,stm32mp251
> + - items:
> + - const: st,stm32mp253
> + - items:
> + - const: st,stm32mp255
> + - items:
> + - const: st,stm32mp257
I assume the slightly odd format is just to avoid churn when adding
the board compatibles.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
> +
> additionalProperties: true
>
> ...
> --
> 2.17.1
>
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 08/11] dt-bindings: stm32: document stm32mp257f-ev1 board
2023-05-29 16:20 ` [PATCH 08/11] dt-bindings: stm32: document stm32mp257f-ev1 board Alexandre Torgue
@ 2023-05-29 18:06 ` Conor Dooley
0 siblings, 0 replies; 28+ messages in thread
From: Conor Dooley @ 2023-05-29 18:06 UTC (permalink / raw)
To: Alexandre Torgue
Cc: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc,
linux-arm-kernel, devicetree, linux-stm32, linux-kernel,
linux-gpio
[-- Attachment #1: Type: text/plain, Size: 258 bytes --]
On Mon, May 29, 2023 at 06:20:31PM +0200, Alexandre Torgue wrote:
> Add new entry for stm32mp257f-ev1 board.
>
> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 02/11] pinctrl: stm32: add stm32mp257 pinctrl support
2023-05-29 18:04 ` Conor Dooley
@ 2023-05-30 8:38 ` Alexandre TORGUE
2023-05-30 8:56 ` Conor Dooley
0 siblings, 1 reply; 28+ messages in thread
From: Alexandre TORGUE @ 2023-05-30 8:38 UTC (permalink / raw)
To: Conor Dooley
Cc: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc,
linux-arm-kernel, devicetree, linux-stm32, linux-kernel,
linux-gpio
Hi Conor
On 5/29/23 20:04, Conor Dooley wrote:
> On Mon, May 29, 2023 at 06:20:25PM +0200, Alexandre Torgue wrote:
>> Add stm32mp257 pinctrl support.
>> diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h
>> index e0c31c4c8bca..5e5de92ddd58 100644
>> --- a/drivers/pinctrl/stm32/pinctrl-stm32.h
>> +++ b/drivers/pinctrl/stm32/pinctrl-stm32.h
>> @@ -24,6 +24,9 @@
>> #define STM32MP_PKG_AB BIT(1)
>> #define STM32MP_PKG_AC BIT(2)
>> #define STM32MP_PKG_AD BIT(3)
>> +#define STM32MP_PKG_AI BIT(8)
>> +#define STM32MP_PKG_AK BIT(10)
>> +#define STM32MP_PKG_AL BIT(11)
>
> Mainly out of curiosity, why have you go duplicate defines for these?
Mainly to fit with available packages for various STM32 MPU. Currently
MP1 SoCs are available with packages AB/AC/AD and MP2 series with
AI/AK/AL but in the future we could have package AB/AC/AD/AI available
for a particular SoC and then I need to anticipate this case.
Cheers
Alex
>
> Cheers,
> Conor.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 04/11] dt-bindings: stm32: add st,stm32mp25 compatibles to the stm32 family
2023-05-29 18:05 ` Conor Dooley
@ 2023-05-30 8:39 ` Alexandre TORGUE
[not found] ` <25d61668-0b79-8565-0de8-dad7e80e3798@linaro.org>
2023-06-02 13:13 ` Krzysztof Kozlowski
0 siblings, 2 replies; 28+ messages in thread
From: Alexandre TORGUE @ 2023-05-30 8:39 UTC (permalink / raw)
To: Conor Dooley
Cc: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc,
linux-arm-kernel, devicetree, linux-stm32, linux-kernel,
linux-gpio
Hi Conor
On 5/29/23 20:05, Conor Dooley wrote:
> On Mon, May 29, 2023 at 06:20:27PM +0200, Alexandre Torgue wrote:
>> STM32 family is extended by the addition of the STM32MP25 SoCs. It is composed
>> of 4 SoCs: STM32MP251, STM32MP253, STM32MP255 and STM32MP257.
>>
>> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
>>
>> diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
>> index 4af5b8f4f803..7d7ca33d2e61 100644
>> --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
>> +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
>> @@ -161,6 +161,15 @@ properties:
>> - const: phytec,phycore-stm32mp157c-som
>> - const: st,stm32mp157
>>
>> + - items:
>> + - const: st,stm32mp251
>> + - items:
>> + - const: st,stm32mp253
>> + - items:
>> + - const: st,stm32mp255
>> + - items:
>> + - const: st,stm32mp257
>
> I assume the slightly odd format is just to avoid churn when adding
> the board compatibles.
Yes, exactly.
Alex
>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> Thanks,
> Conor.
>
>> +
>> additionalProperties: true
>>
>> ...
>> --
>> 2.17.1
>>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 02/11] pinctrl: stm32: add stm32mp257 pinctrl support
2023-05-30 8:38 ` Alexandre TORGUE
@ 2023-05-30 8:56 ` Conor Dooley
2023-05-30 12:08 ` Alexandre TORGUE
0 siblings, 1 reply; 28+ messages in thread
From: Conor Dooley @ 2023-05-30 8:56 UTC (permalink / raw)
To: Alexandre TORGUE
Cc: Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Conor Dooley,
Linus Walleij, Catalin Marinas, Will Deacon, Arnd Bergmann,
Olof Johansson, soc, linux-arm-kernel, devicetree, linux-stm32,
linux-kernel, linux-gpio
[-- Attachment #1: Type: text/plain, Size: 1294 bytes --]
On Tue, May 30, 2023 at 10:38:30AM +0200, Alexandre TORGUE wrote:
> Hi Conor
>
> On 5/29/23 20:04, Conor Dooley wrote:
> > On Mon, May 29, 2023 at 06:20:25PM +0200, Alexandre Torgue wrote:
> > > Add stm32mp257 pinctrl support.
> > > diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h
> > > index e0c31c4c8bca..5e5de92ddd58 100644
> > > --- a/drivers/pinctrl/stm32/pinctrl-stm32.h
> > > +++ b/drivers/pinctrl/stm32/pinctrl-stm32.h
> > > @@ -24,6 +24,9 @@
> > > #define STM32MP_PKG_AB BIT(1)
> > > #define STM32MP_PKG_AC BIT(2)
> > > #define STM32MP_PKG_AD BIT(3)
> > > +#define STM32MP_PKG_AI BIT(8)
> > > +#define STM32MP_PKG_AK BIT(10)
> > > +#define STM32MP_PKG_AL BIT(11)
> >
> > Mainly out of curiosity, why have you go duplicate defines for these?
>
> Mainly to fit with available packages for various STM32 MPU. Currently MP1
> SoCs are available with packages AB/AC/AD and MP2 series with AI/AK/AL but
> in the future we could have package AB/AC/AD/AI available for a particular
> SoC and then I need to anticipate this case.
Sorry, what I meant was "why have you got defines for these in this
header, when there is an existing set in
include/dt-bindings/pinctrl/stm32-pinfunc.h?".
Cheers,
Conor.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 02/11] pinctrl: stm32: add stm32mp257 pinctrl support
2023-05-30 8:56 ` Conor Dooley
@ 2023-05-30 12:08 ` Alexandre TORGUE
0 siblings, 0 replies; 28+ messages in thread
From: Alexandre TORGUE @ 2023-05-30 12:08 UTC (permalink / raw)
To: Conor Dooley
Cc: Conor Dooley, robh+dt, krzysztof.kozlowski+dt, Conor Dooley,
Linus Walleij, Catalin Marinas, Will Deacon, Arnd Bergmann,
Olof Johansson, soc, linux-arm-kernel, devicetree, linux-stm32,
linux-kernel, linux-gpio
On 5/30/23 10:56, Conor Dooley wrote:
> On Tue, May 30, 2023 at 10:38:30AM +0200, Alexandre TORGUE wrote:
>> Hi Conor
>>
>> On 5/29/23 20:04, Conor Dooley wrote:
>>> On Mon, May 29, 2023 at 06:20:25PM +0200, Alexandre Torgue wrote:
>>>> Add stm32mp257 pinctrl support.
>>>> diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h
>>>> index e0c31c4c8bca..5e5de92ddd58 100644
>>>> --- a/drivers/pinctrl/stm32/pinctrl-stm32.h
>>>> +++ b/drivers/pinctrl/stm32/pinctrl-stm32.h
>>>> @@ -24,6 +24,9 @@
>>>> #define STM32MP_PKG_AB BIT(1)
>>>> #define STM32MP_PKG_AC BIT(2)
>>>> #define STM32MP_PKG_AD BIT(3)
>>>> +#define STM32MP_PKG_AI BIT(8)
>>>> +#define STM32MP_PKG_AK BIT(10)
>>>> +#define STM32MP_PKG_AL BIT(11)
>>>
>>> Mainly out of curiosity, why have you go duplicate defines for these?
>>
>> Mainly to fit with available packages for various STM32 MPU. Currently MP1
>> SoCs are available with packages AB/AC/AD and MP2 series with AI/AK/AL but
>> in the future we could have package AB/AC/AD/AI available for a particular
>> SoC and then I need to anticipate this case.
>
> Sorry, what I meant was "why have you got defines for these in this
> header, when there is an existing set in
> include/dt-bindings/pinctrl/stm32-pinfunc.h?".
Ok, I see. To be honest I do it as we did in the past for STM32 MCU and
MP1 products. We had this discussion maybe 5 or 6 years ago about the
fact to include or not the "dt-bindings" file in the stm32 drivers. I
don't remember exactly the rational behind our choice. It is something
that we could improve for all our STM32 products. Sorry for this
imprecise answer.
Alex
>
> Cheers,
> Conor.
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 00/11] Add STM32MP25 support
2023-05-29 16:20 [PATCH 00/11] Add STM32MP25 support Alexandre Torgue
` (10 preceding siblings ...)
2023-05-29 16:20 ` [PATCH 11/11] MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE Alexandre Torgue
@ 2023-05-30 12:39 ` Linus Walleij
2023-05-30 13:32 ` Alexandre TORGUE
11 siblings, 1 reply; 28+ messages in thread
From: Linus Walleij @ 2023-05-30 12:39 UTC (permalink / raw)
To: Alexandre Torgue
Cc: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Catalin Marinas,
Will Deacon, Arnd Bergmann, Olof Johansson, soc,
linux-arm-kernel, devicetree, linux-stm32, linux-kernel,
linux-gpio
On Mon, May 29, 2023 at 6:20 PM Alexandre Torgue
<alexandre.torgue@foss.st.com> wrote:
> Alexandre Torgue (10):
> dt-bindings: pinctrl: stm32: support for stm32mp257 and additional
> packages
> pinctrl: stm32: add stm32mp257 pinctrl support
Can patch 1 & 2 be applied to the pinctrl tree separately?
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 00/11] Add STM32MP25 support
2023-05-30 12:39 ` [PATCH 00/11] Add STM32MP25 support Linus Walleij
@ 2023-05-30 13:32 ` Alexandre TORGUE
0 siblings, 0 replies; 28+ messages in thread
From: Alexandre TORGUE @ 2023-05-30 13:32 UTC (permalink / raw)
To: Linus Walleij
Cc: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Catalin Marinas,
Will Deacon, Arnd Bergmann, Olof Johansson, soc,
linux-arm-kernel, devicetree, linux-stm32, linux-kernel,
linux-gpio
Hi Linus
On 5/30/23 14:39, Linus Walleij wrote:
> On Mon, May 29, 2023 at 6:20 PM Alexandre Torgue
> <alexandre.torgue@foss.st.com> wrote:
>
>> Alexandre Torgue (10):
>> dt-bindings: pinctrl: stm32: support for stm32mp257 and additional
>> packages
>> pinctrl: stm32: add stm32mp257 pinctrl support
>
> Can patch 1 & 2 be applied to the pinctrl tree separately?
Yes please. I'll take others directly in my platform tree.
Thanks
Alex
> Yours,
> Linus Walleij
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 03/11] dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon
[not found] ` <d35fdc37-a793-3109-1474-065dffb03069@linaro.org>
@ 2023-06-02 12:24 ` Alexandre TORGUE
0 siblings, 0 replies; 28+ messages in thread
From: Alexandre TORGUE @ 2023-06-02 12:24 UTC (permalink / raw)
To: Krzysztof Kozlowski, robh+dt, krzysztof.kozlowski+dt,
Conor Dooley, Linus Walleij, Catalin Marinas, Will Deacon,
Arnd Bergmann, Olof Johansson, soc
Cc: linux-arm-kernel, devicetree, linux-stm32, linux-kernel, linux-gpio
Hi Krzysztof
On 5/31/23 20:48, Krzysztof Kozlowski wrote:
> On 29/05/2023 18:20, Alexandre Torgue wrote:
>> From: Patrick Delaunay <patrick.delaunay@foss.st.com>
>>
>> Add the new syscon compatible for STM32MP25 syscfg = "st,stm32mp25-syscfg".
>>
>> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
>> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
>>
>> diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
>> index ad8e51aa01b0..9ed5b121cea9 100644
>> --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
>> +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
>> @@ -16,6 +16,7 @@ properties:
>> - items:
>> - enum:
>> - st,stm32mp157-syscfg
>> + - st,stm32mp25-syscfg
>
> You should rather keep some (alphabetical?) order.
I agree, I'll fix it in V2.
Alex
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 04/11] dt-bindings: stm32: add st,stm32mp25 compatibles to the stm32 family
[not found] ` <25d61668-0b79-8565-0de8-dad7e80e3798@linaro.org>
@ 2023-06-02 12:26 ` Alexandre TORGUE
0 siblings, 0 replies; 28+ messages in thread
From: Alexandre TORGUE @ 2023-06-02 12:26 UTC (permalink / raw)
To: Krzysztof Kozlowski, Conor Dooley
Cc: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc,
linux-arm-kernel, devicetree, linux-stm32, linux-kernel,
linux-gpio
Hi Krzysztof
On 5/31/23 20:47, Krzysztof Kozlowski wrote:
> On 30/05/2023 10:39, Alexandre TORGUE wrote:
>> Hi Conor
>>
>> On 5/29/23 20:05, Conor Dooley wrote:
>>> On Mon, May 29, 2023 at 06:20:27PM +0200, Alexandre Torgue wrote:
>>>> STM32 family is extended by the addition of the STM32MP25 SoCs. It is composed
>>>> of 4 SoCs: STM32MP251, STM32MP253, STM32MP255 and STM32MP257.
>>>>
>>>> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
>>>> index 4af5b8f4f803..7d7ca33d2e61 100644
>>>> --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
>>>> +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
>>>> @@ -161,6 +161,15 @@ properties:
>>>> - const: phytec,phycore-stm32mp157c-som
>>>> - const: st,stm32mp157
>>>>
>>>> + - items:
>>>> + - const: st,stm32mp251
>>>> + - items:
>>>> + - const: st,stm32mp253
>>>> + - items:
>>>> + - const: st,stm32mp255
>>>> + - items:
>>>> + - const: st,stm32mp257
>>>
>>> I assume the slightly odd format is just to avoid churn when adding
>>> the board compatibles.
>>
>> Yes, exactly.
>>
>
> I don't get it. How are you going to extend it? Or rather - what are you
> documenting here? If these are SoCs, then this is not valid. We do not
> allow these alone.
>
> No, please drop it.
Ok. I will drop it in V2 and update binding patch which defines the
STM32 EV1 board.
Thanks
Alex
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 04/11] dt-bindings: stm32: add st,stm32mp25 compatibles to the stm32 family
2023-05-30 8:39 ` Alexandre TORGUE
[not found] ` <25d61668-0b79-8565-0de8-dad7e80e3798@linaro.org>
@ 2023-06-02 13:13 ` Krzysztof Kozlowski
1 sibling, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-02 13:13 UTC (permalink / raw)
To: Alexandre TORGUE, Conor Dooley
Cc: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc,
linux-arm-kernel, devicetree, linux-stm32, linux-kernel,
linux-gpio
On 30/05/2023 10:39, Alexandre TORGUE wrote:
> Hi Conor
>
> On 5/29/23 20:05, Conor Dooley wrote:
>> On Mon, May 29, 2023 at 06:20:27PM +0200, Alexandre Torgue wrote:
>>> STM32 family is extended by the addition of the STM32MP25 SoCs. It is composed
>>> of 4 SoCs: STM32MP251, STM32MP253, STM32MP255 and STM32MP257.
>>>
>>> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
>>> index 4af5b8f4f803..7d7ca33d2e61 100644
>>> --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
>>> @@ -161,6 +161,15 @@ properties:
>>> - const: phytec,phycore-stm32mp157c-som
>>> - const: st,stm32mp157
>>>
>>> + - items:
>>> + - const: st,stm32mp251
>>> + - items:
>>> + - const: st,stm32mp253
>>> + - items:
>>> + - const: st,stm32mp255
>>> + - items:
>>> + - const: st,stm32mp257
>>
>> I assume the slightly odd format is just to avoid churn when adding
>> the board compatibles.
>
> Yes, exactly.
>
I don't get it. How are you going to extend it? Or rather - what are you
documenting here? If these are SoCs, then this is not valid. We do not
allow these alone.
No, please drop it.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 03/11] dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon
2023-05-29 16:20 ` [PATCH 03/11] dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon Alexandre Torgue
[not found] ` <d35fdc37-a793-3109-1474-065dffb03069@linaro.org>
@ 2023-06-02 13:14 ` Krzysztof Kozlowski
1 sibling, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-02 13:14 UTC (permalink / raw)
To: Alexandre Torgue, robh+dt, krzysztof.kozlowski+dt, Conor Dooley,
Linus Walleij, Catalin Marinas, Will Deacon, Arnd Bergmann,
Olof Johansson, soc
Cc: linux-arm-kernel, devicetree, linux-stm32, linux-kernel, linux-gpio
Resending as my previous email probably got lost. If you got it twice,
apologies.
On 29/05/2023 18:20, Alexandre Torgue wrote:
> From: Patrick Delaunay <patrick.delaunay@foss.st.com>
>
> Add the new syscon compatible for STM32MP25 syscfg = "st,stm32mp25-syscfg".
>
> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
>
> diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
> index ad8e51aa01b0..9ed5b121cea9 100644
> --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
> +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
> @@ -16,6 +16,7 @@ properties:
> - items:
> - enum:
> - st,stm32mp157-syscfg
> + - st,stm32mp25-syscfg
You should rather keep some (alphabetical?) order.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 00/11] Add STM32MP25 support
2023-05-29 16:01 Alexandre Torgue
@ 2023-05-29 16:27 ` Alexandre TORGUE
0 siblings, 0 replies; 28+ messages in thread
From: Alexandre TORGUE @ 2023-05-29 16:27 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc
Cc: linux-arm-kernel, devicetree, linux-stm32, linux-kernel, linux-gpio
Hi,
Please drop this mail, my mail server has crashed. The full series has
been resend.
Alex
On 5/29/23 18:01, Alexandre Torgue wrote:
> I'm pleased to announce extension of the STM32 MPU family with the addition of
> the STM32MP25 Armv8 based SoCs.
>
> STM32MP25 family is composed of 4 SoCs defined as following:
>
> -STM32MP251: common part composed of 1*Cortex-A35, common peripherals like
> SDMMC, UART, SPI, I2C, PCIe, USB3, parallel and DSI display, 1*ETH ...
>
> -STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD and
> LVDS display.
>
> -STM32MP255: STM32MP253 + GPU/AI and video encode/decode.
> -STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports).
>
> A second diversity layer exists for security features/ A35 frequency:
> -STM32MP25xY, "Y" gives information:
> -Y = A means A35@1.2GHz + no cryp IP and no secure boot.
> -Y = C means A35@1.2GHz + cryp IP and secure boot.
> -Y = D means A35@1.5GHz + no cryp IP and no secure boot.
> -Y = F means A35@1.5GHz + cryp IP and secure boot.
>
> This series adds the STM32MP257F EV1 board support. This board embeds a
> STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA,
> 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...
>
> Thanks
> Alex
>
> Alexandre Torgue (10):
> dt-bindings: pinctrl: stm32: support for stm32mp257 and additional
> packages
> pinctrl: stm32: add stm32mp257 pinctrl support
> dt-bindings: stm32: add st,stm32mp25 compatibles to the stm32 family
> arm64: introduce STM32 family on Armv8 architecture
> arm64: dts: st: introduce stm32mp25 SoCs family
> arm64: dts: st: introduce stm32mp25 pinctrl files
> dt-bindings: stm32: document stm32mp257f-ev1 board
> arm64: dts: st: add stm32mp257f-ev1 board support
> arm64: defconfig: enable ARCH_STM32 and STM32 serial driver
> MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE
>
> Patrick Delaunay (1):
> dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon
>
> .../bindings/arm/stm32/st,stm32-syscon.yaml | 1 +
> .../devicetree/bindings/arm/stm32/stm32.yaml | 12 +
> .../bindings/pinctrl/st,stm32-pinctrl.yaml | 4 +-
> MAINTAINERS | 1 +
> arch/arm64/Kconfig.platforms | 14 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/st/Makefile | 2 +
> arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 38 +
> arch/arm64/boot/dts/st/stm32mp251.dtsi | 279 ++
> arch/arm64/boot/dts/st/stm32mp253.dtsi | 23 +
> arch/arm64/boot/dts/st/stm32mp255.dtsi | 9 +
> arch/arm64/boot/dts/st/stm32mp257.dtsi | 9 +
> arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 50 +
> arch/arm64/boot/dts/st/stm32mp25xc.dtsi | 8 +
> arch/arm64/boot/dts/st/stm32mp25xf.dtsi | 8 +
> .../boot/dts/st/stm32mp25xxai-pinctrl.dtsi | 83 +
> .../boot/dts/st/stm32mp25xxak-pinctrl.dtsi | 71 +
> .../boot/dts/st/stm32mp25xxal-pinctrl.dtsi | 71 +
> arch/arm64/configs/defconfig | 3 +
> drivers/pinctrl/stm32/Kconfig | 6 +
> drivers/pinctrl/stm32/Makefile | 1 +
> drivers/pinctrl/stm32/pinctrl-stm32.h | 3 +
> drivers/pinctrl/stm32/pinctrl-stm32mp257.c | 2581 +++++++++++++++++
> include/dt-bindings/pinctrl/stm32-pinfunc.h | 3 +
> 24 files changed, 3280 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm64/boot/dts/st/Makefile
> create mode 100644 arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
> create mode 100644 arch/arm64/boot/dts/st/stm32mp251.dtsi
> create mode 100644 arch/arm64/boot/dts/st/stm32mp253.dtsi
> create mode 100644 arch/arm64/boot/dts/st/stm32mp255.dtsi
> create mode 100644 arch/arm64/boot/dts/st/stm32mp257.dtsi
> create mode 100644 arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
> create mode 100644 arch/arm64/boot/dts/st/stm32mp25xc.dtsi
> create mode 100644 arch/arm64/boot/dts/st/stm32mp25xf.dtsi
> create mode 100644 arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi
> create mode 100644 arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi
> create mode 100644 arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi
> create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32mp257.c
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 00/11] Add STM32MP25 support
@ 2023-05-29 16:01 Alexandre Torgue
2023-05-29 16:27 ` Alexandre TORGUE
0 siblings, 1 reply; 28+ messages in thread
From: Alexandre Torgue @ 2023-05-29 16:01 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, Conor Dooley, Linus Walleij,
Catalin Marinas, Will Deacon, Arnd Bergmann, Olof Johansson, soc
Cc: linux-arm-kernel, devicetree, Alexandre Torgue, linux-stm32,
linux-kernel, linux-gpio
I'm pleased to announce extension of the STM32 MPU family with the addition of
the STM32MP25 Armv8 based SoCs.
STM32MP25 family is composed of 4 SoCs defined as following:
-STM32MP251: common part composed of 1*Cortex-A35, common peripherals like
SDMMC, UART, SPI, I2C, PCIe, USB3, parallel and DSI display, 1*ETH ...
-STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD and
LVDS display.
-STM32MP255: STM32MP253 + GPU/AI and video encode/decode.
-STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports).
A second diversity layer exists for security features/ A35 frequency:
-STM32MP25xY, "Y" gives information:
-Y = A means A35@1.2GHz + no cryp IP and no secure boot.
-Y = C means A35@1.2GHz + cryp IP and secure boot.
-Y = D means A35@1.5GHz + no cryp IP and no secure boot.
-Y = F means A35@1.5GHz + cryp IP and secure boot.
This series adds the STM32MP257F EV1 board support. This board embeds a
STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA,
1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...
Thanks
Alex
Alexandre Torgue (10):
dt-bindings: pinctrl: stm32: support for stm32mp257 and additional
packages
pinctrl: stm32: add stm32mp257 pinctrl support
dt-bindings: stm32: add st,stm32mp25 compatibles to the stm32 family
arm64: introduce STM32 family on Armv8 architecture
arm64: dts: st: introduce stm32mp25 SoCs family
arm64: dts: st: introduce stm32mp25 pinctrl files
dt-bindings: stm32: document stm32mp257f-ev1 board
arm64: dts: st: add stm32mp257f-ev1 board support
arm64: defconfig: enable ARCH_STM32 and STM32 serial driver
MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE
Patrick Delaunay (1):
dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon
.../bindings/arm/stm32/st,stm32-syscon.yaml | 1 +
.../devicetree/bindings/arm/stm32/stm32.yaml | 12 +
.../bindings/pinctrl/st,stm32-pinctrl.yaml | 4 +-
MAINTAINERS | 1 +
arch/arm64/Kconfig.platforms | 14 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/st/Makefile | 2 +
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 38 +
arch/arm64/boot/dts/st/stm32mp251.dtsi | 279 ++
arch/arm64/boot/dts/st/stm32mp253.dtsi | 23 +
arch/arm64/boot/dts/st/stm32mp255.dtsi | 9 +
arch/arm64/boot/dts/st/stm32mp257.dtsi | 9 +
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 50 +
arch/arm64/boot/dts/st/stm32mp25xc.dtsi | 8 +
arch/arm64/boot/dts/st/stm32mp25xf.dtsi | 8 +
.../boot/dts/st/stm32mp25xxai-pinctrl.dtsi | 83 +
.../boot/dts/st/stm32mp25xxak-pinctrl.dtsi | 71 +
.../boot/dts/st/stm32mp25xxal-pinctrl.dtsi | 71 +
arch/arm64/configs/defconfig | 3 +
drivers/pinctrl/stm32/Kconfig | 6 +
drivers/pinctrl/stm32/Makefile | 1 +
drivers/pinctrl/stm32/pinctrl-stm32.h | 3 +
drivers/pinctrl/stm32/pinctrl-stm32mp257.c | 2581 +++++++++++++++++
include/dt-bindings/pinctrl/stm32-pinfunc.h | 3 +
24 files changed, 3280 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/st/Makefile
create mode 100644 arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp251.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp253.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp255.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp257.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
create mode 100644 arch/arm64/boot/dts/st/stm32mp25xc.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp25xf.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi
create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32mp257.c
--
2.17.1
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2023-06-02 13:14 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-29 16:20 [PATCH 00/11] Add STM32MP25 support Alexandre Torgue
2023-05-29 16:20 ` [PATCH 01/11] dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages Alexandre Torgue
2023-05-29 18:00 ` Conor Dooley
2023-05-29 16:20 ` [PATCH 02/11] pinctrl: stm32: add stm32mp257 pinctrl support Alexandre Torgue
2023-05-29 18:04 ` Conor Dooley
2023-05-30 8:38 ` Alexandre TORGUE
2023-05-30 8:56 ` Conor Dooley
2023-05-30 12:08 ` Alexandre TORGUE
2023-05-29 16:20 ` [PATCH 03/11] dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon Alexandre Torgue
[not found] ` <d35fdc37-a793-3109-1474-065dffb03069@linaro.org>
2023-06-02 12:24 ` Alexandre TORGUE
2023-06-02 13:14 ` Krzysztof Kozlowski
2023-05-29 16:20 ` [PATCH 04/11] dt-bindings: stm32: add st,stm32mp25 compatibles to the stm32 family Alexandre Torgue
2023-05-29 18:05 ` Conor Dooley
2023-05-30 8:39 ` Alexandre TORGUE
[not found] ` <25d61668-0b79-8565-0de8-dad7e80e3798@linaro.org>
2023-06-02 12:26 ` Alexandre TORGUE
2023-06-02 13:13 ` Krzysztof Kozlowski
2023-05-29 16:20 ` [PATCH 05/11] arm64: introduce STM32 family on Armv8 architecture Alexandre Torgue
2023-05-29 16:20 ` [PATCH 06/11] arm64: dts: st: introduce stm32mp25 SoCs family Alexandre Torgue
2023-05-29 16:20 ` [PATCH 07/11] arm64: dts: st: introduce stm32mp25 pinctrl files Alexandre Torgue
2023-05-29 16:20 ` [PATCH 08/11] dt-bindings: stm32: document stm32mp257f-ev1 board Alexandre Torgue
2023-05-29 18:06 ` Conor Dooley
2023-05-29 16:20 ` [PATCH 09/11] arm64: dts: st: add stm32mp257f-ev1 board support Alexandre Torgue
2023-05-29 16:20 ` [PATCH 10/11] arm64: defconfig: enable ARCH_STM32 and STM32 serial driver Alexandre Torgue
2023-05-29 16:20 ` [PATCH 11/11] MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE Alexandre Torgue
2023-05-30 12:39 ` [PATCH 00/11] Add STM32MP25 support Linus Walleij
2023-05-30 13:32 ` Alexandre TORGUE
-- strict thread matches above, loose matches on Subject: below --
2023-05-29 16:01 Alexandre Torgue
2023-05-29 16:27 ` Alexandre TORGUE
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