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X-CSE-ConnectionGUID: pNjzk4eXTSSVd+EE9ISQhg== X-CSE-MsgGUID: xKDuxmsPSK60Uth0ervh2Q== X-IronPort-AV: E=McAfee;i="6600,9927,11035"; a="11478923" X-IronPort-AV: E=Sophos;i="6.07,181,1708416000"; d="scan'208";a="11478923" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Apr 2024 07:48:09 -0700 X-CSE-ConnectionGUID: H55LyW5ASaqr4vhL9J0MYQ== X-CSE-MsgGUID: +963A5O0TASYUpMZv+tuJQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,181,1708416000"; d="scan'208";a="23821308" Received: from dtorrice-mobl1.ger.corp.intel.com (HELO localhost) ([10.252.41.202]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Apr 2024 07:47:59 -0700 From: Jani Nikula To: Peter Zijlstra , Andrzej Hajda Cc: Mark Rutland , linux-ia64@vger.kernel.org, linux-sh@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, sparclinux@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, linux-hexagon@vger.kernel.org, linux-snps-arc@lists.infradead.org, intel-gfx@lists.freedesktop.org, linux-xtensa@linux-xtensa.org, Arnd Bergmann , Boqun Feng , linux-m68k@lists.linux-m68k.org, openrisc@lists.librecores.org, loongarch@lists.linux.dev, Rodrigo Vivi , Andy Shevchenko , linux-arm-kernel@lists.infradead.org, linux-parisc@vger.kernel.org, linux-mips@vger.kernel.org, linux-alpha@vger.kernel.org, Andrew Morton , linuxppc-dev@lists.ozlabs.org Subject: Re: [Intel-gfx] [PATCH v5 0/7] Introduce __xchg, non-atomic xchg In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20230118153529.57695-1-andrzej.hajda@intel.com> <17f40b7c-f98d-789d-fa19-12ec077b756a@intel.com> Date: Fri, 05 Apr 2024 17:47:56 +0300 Message-ID: <87r0fjc1cz.fsf@intel.com> Precedence: bulk X-Mailing-List: sparclinux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Mon, 27 Feb 2023, Peter Zijlstra wrote: > On Thu, Feb 23, 2023 at 10:24:19PM +0100, Andrzej Hajda wrote: >> On 22.02.2023 18:04, Peter Zijlstra wrote: >> > On Wed, Jan 18, 2023 at 04:35:22PM +0100, Andrzej Hajda wrote: >> > >> > > Andrzej Hajda (7): >> > > arch: rename all internal names __xchg to __arch_xchg >> > > linux/include: add non-atomic version of xchg >> > > arch/*/uprobes: simplify arch_uretprobe_hijack_return_addr >> > > llist: simplify __llist_del_all >> > > io_uring: use __xchg if possible >> > > qed: use __xchg if possible >> > > drm/i915/gt: use __xchg instead of internal helper >> > >> > Nothing crazy in here I suppose, I somewhat wonder why you went through >> > the trouble, but meh. >> >> If you are asking why I have proposed this patchset, then the answer is >> simple, 1st I've tried to find a way to move internal i915 helper to core >> (see patch 7). >> Then I was looking for possible other users of this helper. And apparently >> there are many of them, patches 3-7 shows some. >> >> >> > >> > You want me to take this through te locking tree (for the next cycle, >> > not this one) where I normally take atomic things or does someone else >> > want this? >> >> If you could take it I will be happy. > > OK, I'll go queue it in tip/locking/core after -rc1. Thanks! Is this where the series fell between the cracks, or was there some follow-up that I missed? I think this would still be useful. Andrzej, would you mind rebasing and resending if there are no objections? BR, Jani. -- Jani Nikula, Intel