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[2003:cb:c703:1f00:7816:2307:5967:2228]) by smtp.gmail.com with ESMTPSA id m34-20020a05600c3b2200b003df5be8987esm14091432wms.20.2023.02.27.05.31.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Feb 2023 05:31:38 -0800 (PST) Message-ID: <9ed766a6-cf06-535d-3337-ea6ff25c2362@redhat.com> Date: Mon, 27 Feb 2023 14:31:37 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.2 Content-Language: en-US To: Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, Andrew Morton , Hugh Dickins , John Hubbard , Jason Gunthorpe , Mike Rapoport , Yang Shi , Vlastimil Babka , Nadav Amit , Andrea Arcangeli , Peter Xu , linux-mm@kvack.org, x86@kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-mips@vger.kernel.org, openrisc@lists.librecores.org, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, linux-xtensa@linux-xtensa.org, Michal Simek References: <20230113171026.582290-1-david@redhat.com> <20230113171026.582290-12-david@redhat.com> From: David Hildenbrand Organization: Red Hat Subject: Re: [PATCH mm-unstable v1 11/26] microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: sparclinux@vger.kernel.org On 26.02.23 21:13, Geert Uytterhoeven wrote: > Hi David, Hi Geert, > > On Fri, Jan 13, 2023 at 6:16 PM David Hildenbrand wrote: >> Let's support __HAVE_ARCH_PTE_SWP_EXCLUSIVE by stealing one bit >> from the type. Generic MM currently only uses 5 bits for the type >> (MAX_SWAPFILES_SHIFT), so the stolen bit is effectively unused. >> >> The shift by 2 when converting between PTE and arch-specific swap entry >> makes the swap PTE layout a little bit harder to decipher. >> >> While at it, drop the comment from paulus---copy-and-paste leftover >> from powerpc where we actually have _PAGE_HASHPTE---and mask the type in >> __swp_entry_to_pte() as well. >> >> Cc: Michal Simek >> Signed-off-by: David Hildenbrand > > Thanks for your patch, which is now commit b5c88f21531c3457 > ("microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE") in > Right, it went upstream, so we can only fixup. >> arch/m68k/include/asm/mcf_pgtable.h | 4 +-- > > What is this m68k change doing here? > Sorry for not noticing this earlier. Thanks for the late review, still valuable :) That hunk should have gone into the previous patch, looks like I messed that up when reworking. > > Furthermore, several things below look strange to me... > >> arch/microblaze/include/asm/pgtable.h | 45 +++++++++++++++++++++------ >> 2 files changed, 37 insertions(+), 12 deletions(-) >> >> diff --git a/arch/m68k/include/asm/mcf_pgtable.h b/arch/m68k/include/asm/mcf_pgtable.h >> index 3f8f4d0e66dd..e573d7b649f7 100644 >> --- a/arch/m68k/include/asm/mcf_pgtable.h >> +++ b/arch/m68k/include/asm/mcf_pgtable.h >> @@ -46,8 +46,8 @@ >> #define _CACHEMASK040 (~0x060) >> #define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */ >> >> -/* We borrow bit 7 to store the exclusive marker in swap PTEs. */ >> -#define _PAGE_SWP_EXCLUSIVE 0x080 >> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */ >> +#define _PAGE_SWP_EXCLUSIVE CF_PAGE_NOCACHE > > CF_PAGE_NOCACHE is 0x80, so this is still bit 7, thus the new comment > is wrong? You're right, it's still bit 7 (and we use LSB-0 bit numbering in that file). I'll send a fixup. > >> >> /* >> * Externally used page protection values. >> diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h >> index 42f5988e998b..7e3de54bf426 100644 >> --- a/arch/microblaze/include/asm/pgtable.h >> +++ b/arch/microblaze/include/asm/pgtable.h >> @@ -131,10 +131,10 @@ extern pte_t *va_to_pte(unsigned long address); >> * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB >> * miss handler. Bit 27 is PAGE_USER, thus selecting the correct >> * zone. >> - * - PRESENT *must* be in the bottom two bits because swap cache >> - * entries use the top 30 bits. Because 4xx doesn't support SMP >> - * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30 >> - * is cleared in the TLB miss handler before the TLB entry is loaded. >> + * - PRESENT *must* be in the bottom two bits because swap PTEs use the top >> + * 30 bits. Because 4xx doesn't support SMP anyway, M is irrelevant so we >> + * borrow it for PAGE_PRESENT. Bit 30 is cleared in the TLB miss handler >> + * before the TLB entry is loaded. > > So the PowerPC 4xx comment is still here? I only dropped the comment above __swp_type(). I guess you mean that we could also drop the "Because 4xx doesn't support SMP anyway, M is irrelevant so we borrow it for PAGE_PRESENT." sentence, correct? Not sure about the "Bit 30 is cleared in the TLB miss handler" comment, if that can similarly be dropped. > >> * - All other bits of the PTE are loaded into TLBLO without >> * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for >> * software PTE bits. We actually use bits 21, 24, 25, and >> @@ -155,6 +155,9 @@ extern pte_t *va_to_pte(unsigned long address); >> #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ >> #define _PMD_PRESENT PAGE_MASK >> >> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */ >> +#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY > > _PAGE_DIRTY is 0x80, so this is also bit 7, thus the new comment is > wrong? In the example, I use MSB-0 bit numbering (which I determined to be correct in microblaze context eventually, but I got confused a couple a times because it's very inconsistent). That should be MSB-0 bit 24. Thanks! -- Thanks, David / dhildenb