From: <gregkh@linuxfoundation.org>
To: kirill.shutemov@linux.intel.com, dave.hansen@intel.com,
gregkh@linuxfoundation.org, kai.huang@linux.intel.com,
mingo@kernel.org, peterz@infradead.org, tglx@linutronix.de,
thomas.lendacky@amd.com, torvalds@linux-foundation.org
Cc: <stable@vger.kernel.org>, <stable-commits@vger.kernel.org>
Subject: Patch "x86/cpufeatures: Add Intel PCONFIG cpufeature" has been added to the 4.15-stable tree
Date: Mon, 19 Mar 2018 11:03:33 +0100 [thread overview]
Message-ID: <15214538134978@kroah.com> (raw)
This is a note to let you know that I've just added the patch titled
x86/cpufeatures: Add Intel PCONFIG cpufeature
to the 4.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
x86-cpufeatures-add-intel-pconfig-cpufeature.patch
and it can be found in the queue-4.15 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From 7958b2246fadf54b7ff820a2a5a2c5ca1554716f Mon Sep 17 00:00:00 2001
From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Date: Mon, 5 Mar 2018 19:25:51 +0300
Subject: x86/cpufeatures: Add Intel PCONFIG cpufeature
From: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
commit 7958b2246fadf54b7ff820a2a5a2c5ca1554716f upstream.
CPUID.0x7.0x0:EDX[18] indicates whether Intel CPU support PCONFIG instruction.
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: Kai Huang <kai.huang@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: linux-mm@kvack.org
Link: http://lkml.kernel.org/r/20180305162610.37510-4-kirill.shutemov@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -327,6 +327,7 @@
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
+#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
Patches currently in stable-queue which might be from kirill.shutemov@linux.intel.com are
queue-4.15/x86-cpufeatures-add-intel-pconfig-cpufeature.patch
queue-4.15/x86-cpufeatures-add-intel-total-memory-encryption-cpufeature.patch
reply other threads:[~2018-03-19 10:05 UTC|newest]
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