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Peter Anvin" , Huang Rui , Janakarajan Natarajan , Jan Beulich , Jiaxun Yang , Jiri Olsa , Josh Poimboeuf , Linus Torvalds , Luwei Kang , =?UTF-8?Q?Martin_Li=c5=a1ka?= , Matt Fleming , Michael Petlan , Namhyung Kim , Paolo Bonzini , Pawan Gupta , Suravee Suthikulpanit , Thomas Gleixner , Tom Lendacky , x86@kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20200214201805.13830-1-kim.phillips@amd.com> <20200218112035.GB14449@zn.tnic> Message-ID: <15f0ff78-1a94-cfa7-297b-c226cb98d10f@amd.com> Date: Tue, 18 Feb 2020 15:35:25 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 In-Reply-To: <20200218112035.GB14449@zn.tnic> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SN4PR0501CA0109.namprd05.prod.outlook.com (2603:10b6:803:42::26) To SN6PR12MB2845.namprd12.prod.outlook.com (2603:10b6:805:75::33) MIME-Version: 1.0 Received: from [10.236.136.247] (165.204.77.1) by SN4PR0501CA0109.namprd05.prod.outlook.com (2603:10b6:803:42::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2750.6 via Frontend Transport; Tue, 18 Feb 2020 21:35:26 +0000 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 7153cd2c-2d87-485b-86f5-08d7b4ba78a9 X-MS-TrafficTypeDiagnostic: SN6PR12MB2686:|SN6PR12MB2686: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-Forefront-PRVS: 031763BCAF X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(4636009)(396003)(39860400002)(376002)(346002)(136003)(366004)(189003)(199004)(8676002)(8936002)(44832011)(54906003)(7416002)(81156014)(81166006)(316002)(2616005)(16576012)(956004)(53546011)(16526019)(52116002)(478600001)(6486002)(31696002)(31686004)(4326008)(2906002)(6916009)(5660300002)(66946007)(36756003)(26005)(66556008)(66476007)(86362001)(186003);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2686;H:SN6PR12MB2845.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +i2dtM1MxwOUZMgoEPv/42q5KqfrL9OclwexdNROaZ+5m2ACfSpY9IE604I5h39jeqUUJeOnMFxsnWTvhoaGoN5m7Amsy3O350OJEQRo2c8LVt6VPbshzeWVgy/uTDFSnPHcP46hltA2UifZL4uULy4HZ1vHV9gD+Y060gI2cX9wg9gwCSJ3YUM63q7ThUv8LNkM8XPhQt1bap6iTZzh78r/sW/Of5OhTijDHXcDhwxPnitts+nx3t3Qp8cyyBlVgB1bavyqIFnJIAb93b6SrPKFNsgYfj0c3EYp3pCFBg0m6WS/OuCMITyrK+2HeHiN5pdMKIm4flBLkZ3AmHoIxH70UE1wYDREEF8PzBgYswovncoPuGBo1CGkL2vge5iNRer/ECV4Bikp3qDUwzyAASoFVT6VBeGPBc4KL8VvrabHbaqClCVRhW7y81pA5ptO X-MS-Exchange-AntiSpam-MessageData: fye5WnUlqkJLsCP6L5HQ0LQ3XJetH/laujszLhnGwwY4+sYbG78nODhJfZ7/1m/v71fe6D5c4pcqFDYlfGpX/ZusQ+WFrfYXtGNl6Sx5NiDJnSPpG3kOEye8eZ0KSW+qrXkQMREQ7toCqDicXQbbWg== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7153cd2c-2d87-485b-86f5-08d7b4ba78a9 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2020 21:35:29.1239 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: wpMHILqZW6UW1fSIXBSnSCJH+ZKJajfAzQogdGlLZ61H4QqmDTklXNHZ92BK9PoDrUFg2GBSBDK2bL1y8BbHtQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2686 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Hi Borislav, On 2/18/20 5:20 AM, Borislav Petkov wrote: > On Fri, Feb 14, 2020 at 02:18:05PM -0600, Kim Phillips wrote: >> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h >> index f3327cb56edf..8979d6fcc79c 100644 >> --- a/arch/x86/include/asm/cpufeatures.h >> +++ b/arch/x86/include/asm/cpufeatures.h >> @@ -404,5 +404,6 @@ >> #define X86_BUG_SWAPGS X86_BUG(21) /* CPU is affected by speculation through SWAPGS */ >> #define X86_BUG_TAA X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */ >> #define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */ >> +#define X86_BUG_IRPERF X86_BUG(24) /* CPU is affected by Instructions Retired counter Erratum 1054 */ > > Do you need this bug flag at all? > > If the only reason for its existence is to check it before setting > the MSR bit enabling IRPERF, then you don't need it. Or is there any > particular reason why it should show in /proc/cpuinfo? > > IOW, does this work too? Yes, that works quite nicely, and saves us a bug bit. The only reason to have it show in /proc/cpuinfo is for userspace, but they can check for a nonzero count prior to using, instead. Let me know if you'd like me to send a v4, or if you will just apply this version of yours. Thanks, Kim