From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09F62C76186 for ; Wed, 24 Jul 2019 19:30:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D14C021951 for ; Wed, 24 Jul 2019 19:30:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1563996610; bh=uBgELbhUqCeoKuc7FME1hWiKsVaU7eEsxO07pSIDEA8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=giecsUD4QfQysugSLBIO3RRBI1ACTxCQiaedklVnwqvOgRVn4aNrHD8Ej5ks5EQ85 z3xxBhTtoL+JnMDxrbSK21Zv4l53s8HA+pOCQ37SSHR9icG5TvJnOlCG0oJS+1l0nL DeUaMselsOckItSDXldjuH1O8Epkg1+k+Z2wDnRw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388256AbfGXTaF (ORCPT ); Wed, 24 Jul 2019 15:30:05 -0400 Received: from mail.kernel.org ([198.145.29.99]:49896 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388259AbfGXTaE (ORCPT ); Wed, 24 Jul 2019 15:30:04 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 948C6218EA; Wed, 24 Jul 2019 19:30:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1563996604; bh=uBgELbhUqCeoKuc7FME1hWiKsVaU7eEsxO07pSIDEA8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=11Nz0t3gsDgQUQY5MaifKvUgeC69ypbUfZzI8QI5kevU6OeR48aUi0XG/khrYhW4x nDrQ2U9wamNTAQReyF8swCXkxwg5rOmW2dqJAguzKBi19wHb1PklgGxvbRzlApuQP2 5jG/F7nR3cjv3RDKsuqAkCkj4IiSeAnmTEi+vUgY= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Icenowy Zheng , Ondrej Jirman , "David S. Miller" , Sasha Levin Subject: [PATCH 5.2 153/413] net: stmmac: sun8i: force select external PHY when no internal one Date: Wed, 24 Jul 2019 21:17:24 +0200 Message-Id: <20190724191745.962993931@linuxfoundation.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190724191735.096702571@linuxfoundation.org> References: <20190724191735.096702571@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org [ Upstream commit 0fec7e72ae1391bb2d7527efb54fe6ae88acabce ] The PHY selection bit also exists on SoCs without an internal PHY; if it's set to 1 (internal PHY, default value) then the MAC will not make use of any PHY on such SoCs. This problem appears when adapting for H6, which has no real internal PHY (the "internal PHY" on H6 is not on-die, but on a co-packaged AC200 chip, connected via RMII interface at GPIO bank A). Force the PHY selection bit to 0 when the SOC doesn't have an internal PHY, to address the problem of a wrong default value. Signed-off-by: Icenowy Zheng Signed-off-by: Ondrej Jirman Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index a69c34f605b1..98a15ba8be9f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -884,6 +884,11 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) * address. No need to mask it again. */ reg |= 1 << H3_EPHY_ADDR_SHIFT; + } else { + /* For SoCs without internal PHY the PHY selection bit should be + * set to 0 (external PHY). + */ + reg &= ~H3_EPHY_SELECT; } if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { -- 2.20.1