From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEE42C76186 for ; Wed, 24 Jul 2019 19:39:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B3D1122AED for ; Wed, 24 Jul 2019 19:39:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1563997198; bh=wLasL/pUJqvVePSzj70gWRxbCi16JyQ7xzLGqc936FE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=NLIORJ4DQmcnb1LGi1nR1vijMS5U+97Qso8U/S1lIk/4P0Azikn/oJalPcxXX7nxL rFzlYYUJ4i8Q7oBJ9MuhXB2An7c5IQ/tVZ56xsrhDYyZq9D0tDIpMy6PMQjlmrsrFL 6t89TfvGgf55VDrH3WXkpFdAu4gkI/1DAplJiBRI= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389704AbfGXTj5 (ORCPT ); Wed, 24 Jul 2019 15:39:57 -0400 Received: from mail.kernel.org ([198.145.29.99]:41038 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388525AbfGXTj4 (ORCPT ); Wed, 24 Jul 2019 15:39:56 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 893A620665; Wed, 24 Jul 2019 19:39:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1563997196; bh=wLasL/pUJqvVePSzj70gWRxbCi16JyQ7xzLGqc936FE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IIcAgPZgY+RYwCqTTTb6WHz3gDXg64pcDb3/SMS4qgPk1K2aWEcfIevgc7FKAz89c DtnhNEhp8BAqok8+RltdaFHBFxRkzSqRi7qYik826jFu+WI2clriHp2PvJ45oRBtK6 ZiAFoe3QZ729c9WGC9poFpZLf9U3d0wUxAjhkZfA= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Kim Phillips , "Peter Zijlstra (Intel)" , Alexander Shishkin , Arnaldo Carvalho de Melo , Borislav Petkov , Gary Hook , "H. Peter Anvin" , Janakarajan Natarajan , Jiri Olsa , Linus Torvalds , Martin Liska , Namhyung Kim , Pu Wen , Stephane Eranian , Suravee Suthikulpanit , Thomas Gleixner , Vince Weaver , Ingo Molnar Subject: [PATCH 5.2 355/413] perf/x86/amd/uncore: Do not set ThreadMask and SliceMask for non-L3 PMCs Date: Wed, 24 Jul 2019 21:20:46 +0200 Message-Id: <20190724191801.113101726@linuxfoundation.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190724191735.096702571@linuxfoundation.org> References: <20190724191735.096702571@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Kim Phillips commit 16f4641166b10e199f0d7b68c2c5f004fef0bda3 upstream. The following commit: d7cbbe49a930 ("perf/x86/amd/uncore: Set ThreadMask and SliceMask for L3 Cache perf events") enables L3 PMC events for all threads and slices by writing 1's in 'ChL3PmcCfg' (L3 PMC PERF_CTL) register fields. Those bitfields overlap with high order event select bits in the Data Fabric PMC control register, however. So when a user requests raw Data Fabric events (-e amd_df/event=0xYYY/), the two highest order bits get inadvertently set, changing the counter select to events that don't exist, and for which no counts are read. This patch changes the logic to write the L3 masks only when dealing with L3 PMC counters. AMD Family 16h and below Northbridge (NB) counters were not affected. Signed-off-by: Kim Phillips Signed-off-by: Peter Zijlstra (Intel) Cc: Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Borislav Petkov Cc: Gary Hook Cc: H. Peter Anvin Cc: Janakarajan Natarajan Cc: Jiri Olsa Cc: Linus Torvalds Cc: Martin Liska Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Pu Wen Cc: Stephane Eranian Cc: Suravee Suthikulpanit Cc: Thomas Gleixner Cc: Vince Weaver Fixes: d7cbbe49a930 ("perf/x86/amd/uncore: Set ThreadMask and SliceMask for L3 Cache perf events") Link: https://lkml.kernel.org/r/20190628215906.4276-1-kim.phillips@amd.com Signed-off-by: Ingo Molnar Signed-off-by: Greg Kroah-Hartman --- arch/x86/events/amd/uncore.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -206,7 +206,7 @@ static int amd_uncore_event_init(struct * SliceMask and ThreadMask need to be set for certain L3 events in * Family 17h. For other events, the two fields do not affect the count. */ - if (l3_mask) + if (l3_mask && is_llc_event(event)) hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK); if (event->cpu < 0)