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Wed, 31 Jul 2019 22:20:13 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id r13sm98686393pfr.25.2019.07.31.22.20.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Jul 2019 22:20:12 -0700 (PDT) Date: Thu, 1 Aug 2019 10:50:11 +0530 From: Viresh Kumar To: Mark Rutland Cc: stable@vger.kernel.org, Julien Thierry , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: Re: [PATCH v4.4 V2 24/43] arm64: Add skeleton to harden the branch predictor against aliasing attacks Message-ID: <20190801052011.2hrei36v4zntyfn5@vireshk-i7> References: <4349161f0ed572bbc6bff64bad94aa96d07b27ff.1562908075.git.viresh.kumar@linaro.org> <20190731164556.GI39768@lakrids.cambridge.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190731164556.GI39768@lakrids.cambridge.arm.com> User-Agent: NeoMutt/20180716-391-311a52 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On 31-07-19, 17:45, Mark Rutland wrote: > On Fri, Jul 12, 2019 at 10:58:12AM +0530, Viresh Kumar wrote: > > From: Will Deacon > > > > commit 0f15adbb2861ce6f75ccfc5a92b19eae0ef327d0 upstream. > > > > Aliasing attacks against CPU branch predictors can allow an attacker to > > redirect speculative control flow on some CPUs and potentially divulge > > information from one context to another. > > > > This patch adds initial skeleton code behind a new Kconfig option to > > enable implementation-specific mitigations against these attacks for > > CPUs that are affected. > > > > Co-developed-by: Marc Zyngier > > Signed-off-by: Will Deacon > > Signed-off-by: Catalin Marinas > > [ v4.4: Changes made according to 4.4 codebase ] > > Signed-off-by: Viresh Kumar > > [...] > > > /* id_aa64pfr0 */ > > +#define ID_AA64PFR0_CSV2_SHIFT 56 > > Note: CSV3 is bits 63-60, > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > index 474b34243521..040a42d79990 100644 > > --- a/arch/arm64/kernel/cpufeature.c > > +++ b/arch/arm64/kernel/cpufeature.c > > @@ -83,7 +83,8 @@ static struct arm64_ftr_bits ftr_id_aa64isar0[] = { > > }; > > > > static struct arm64_ftr_bits ftr_id_aa64pfr0[] = { > > - ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0), > > + ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), > > + ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 28, 0), > > This line should be: > > ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 24, 0), > > ... as it was in the v4.9 backbort, making it cover bits 55:32. As in > this patch, it covers 59:32, overlapping with CSV2. Fixed thanks. > We also need to cater for bits 63:60. In the v4.9 backport, the meltdown > bits were applied first, so nothing special was necessary. > > What's the plan w.r.t. meltdown mitigations and v4.4? I haven't started looking at meltdown patches yet and so that will be done at a later point of time, if at all done by me. I have been asked to backport both Spectre and Meltdown though to 4.4. -- viresh