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[81.83.0.216]) by smtp.gmail.com with ESMTPSA id i53sm2682361eda.33.2019.09.11.02.14.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2019 02:14:04 -0700 (PDT) From: Koen Vandeputte To: linux-mips@linux-mips.org Cc: Koen Vandeputte , Felix Fietkau , Gabor Juhos , James Hogan , Paul Burton , Ralf Baechle , stable@vger.kernel.org Subject: [PATCH] MIPS: ath79: Fix potentially missed IRQ handling during dispatch Date: Wed, 11 Sep 2019 11:13:28 +0200 Message-Id: <20190911091328.32043-1-koen.vandeputte@ncentric.com> X-Mailer: git-send-email 2.17.1 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org If both interrupts are set in the current implementation only the 1st will be handled and the 2nd will be skipped due to the "if else" condition. Fix this by using the same approach as done for QCA955x just below it. Fixes: fce5cc6e0ddc ("MIPS: ath79: add IRQ handling code for AR934X") Signed-off-by: Koen Vandeputte CC: Felix Fietkau CC: Gabor Juhos CC: James Hogan CC: Paul Burton CC: Ralf Baechle CC: stable@vger.kernel.org # v3.2+ --- NOTE! The file irq.c got deleted in commit 51fa4f8912c0 ("MIPS: ath79: drop legacy IRQ code") which was included in 5.0-RC2. Therefore, the patch below was crafted on tree: linux-stable branch: linux-4.19.y arch/mips/ath79/irq.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c index 2dfff1f19004..372431660cc7 100644 --- a/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c @@ -32,15 +32,21 @@ static void ar934x_ip2_irq_dispatch(struct irq_desc *desc) u32 status; status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS); + status &= AR934X_PCIE_WMAC_INT_PCIE_ALL | AR934X_PCIE_WMAC_INT_WMAC_ALL; + + if (status == 0) { + spurious_interrupt(); + return; + } if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) { ath79_ddr_wb_flush(3); - generic_handle_irq(ATH79_IP2_IRQ(0)); - } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) { + generic_handle_irq(ATH79_IP2_IRQ(0));); + } + + if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) { ath79_ddr_wb_flush(4); generic_handle_irq(ATH79_IP2_IRQ(1)); - } else { - spurious_interrupt(); } } -- 2.17.1