From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A299ECE58E for ; Thu, 10 Oct 2019 08:51:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6962421D71 for ; Thu, 10 Oct 2019 08:51:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1570697471; bh=heI1w7nY6McwTvjkvsOTZmwnaKryPkblh2fn31KdwDI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=CfIN1h1SYdXjiEnHSLqF+WhzaFYTE2XjUrQhxhYIlVRGa1C3m5GmNsus+7+94ocIg 9oGIxtSA/eMeO1nEUGHt0MVOPke0ewyga++ym1XOY2jak1nWMCr77BJ89icgGqWbzl YaVgUGN3XgWyW9N98KX/tHmqCETV93dDirf7+t8c= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390084AbfJJIvK (ORCPT ); Thu, 10 Oct 2019 04:51:10 -0400 Received: from mail.kernel.org ([198.145.29.99]:58438 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390075AbfJJIvG (ORCPT ); Thu, 10 Oct 2019 04:51:06 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5C4B620679; Thu, 10 Oct 2019 08:51:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1570697465; bh=heI1w7nY6McwTvjkvsOTZmwnaKryPkblh2fn31KdwDI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c7P8GNIHfW5r6Zhq0cNHzb2M0ybqOpwxgimysyeKk0bEoDUpn6P/GPOOh5YPzxAbr AIR55CrM0/V5IKv1Ya3laeucuoZICtEQ1ahZrTNtZZx963arQX061vGs0BldXHzpmg IkNuKKNBLKUUAwBsDnbO8BriLC4B3f2xiWZWeh28= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Fabrice Gasnier , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Thierry Reding , Sasha Levin Subject: [PATCH 4.14 38/61] pwm: stm32-lp: Add check in case requested period cannot be achieved Date: Thu, 10 Oct 2019 10:37:03 +0200 Message-Id: <20191010083514.363248246@linuxfoundation.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191010083449.500442342@linuxfoundation.org> References: <20191010083449.500442342@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Fabrice Gasnier [ Upstream commit c91e3234c6035baf5a79763cb4fcd5d23ce75c2b ] LPTimer can use a 32KHz clock for counting. It depends on clock tree configuration. In such a case, PWM output frequency range is limited. Although unlikely, nothing prevents user from requesting a PWM frequency above counting clock (32KHz for instance): - This causes (prd - 1) = 0xffff to be written in ARR register later in the apply() routine. This results in badly configured PWM period (and also duty_cycle). Add a check to report an error is such a case. Signed-off-by: Fabrice Gasnier Reviewed-by: Uwe Kleine-König Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- drivers/pwm/pwm-stm32-lp.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c index 9793b296108ff..3f2e4ef695d75 100644 --- a/drivers/pwm/pwm-stm32-lp.c +++ b/drivers/pwm/pwm-stm32-lp.c @@ -59,6 +59,12 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, /* Calculate the period and prescaler value */ div = (unsigned long long)clk_get_rate(priv->clk) * state->period; do_div(div, NSEC_PER_SEC); + if (!div) { + /* Clock is too slow to achieve requested period. */ + dev_dbg(priv->chip.dev, "Can't reach %u ns\n", state->period); + return -EINVAL; + } + prd = div; while (div > STM32_LPTIM_MAX_ARR) { presc++; -- 2.20.1