From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A003C43331 for ; Mon, 11 Nov 2019 18:31:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2FC3E2173B for ; Mon, 11 Nov 2019 18:31:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1573497072; bh=RJg+NpvpsDYYNN2voNdfNoMG1zjJq7mpF5ZJMNMGIcQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=gg3TPeU2/2FIs6vA1uslwwdrS2MqCWW64iTw9IC26RjXmDAFXRzI4zdiVHkKMjh9S 3nKZOosN5OAZ6AqUTTDtXUUxjWjLEyO8NQIAmTO0qTJsTaj6pr67xRDCzeNboYkGH1 gj9xXpKjG4ZTxxR/MupzadWUNsRuoMf5xgeaKJxQ= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727568AbfKKSbL (ORCPT ); Mon, 11 Nov 2019 13:31:11 -0500 Received: from mail.kernel.org ([198.145.29.99]:47692 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727559AbfKKSbL (ORCPT ); Mon, 11 Nov 2019 13:31:11 -0500 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A4F4221783; Mon, 11 Nov 2019 18:31:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1573497070; bh=RJg+NpvpsDYYNN2voNdfNoMG1zjJq7mpF5ZJMNMGIcQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MYwuQmVJOZVpVBizKOuQIS/yulijKj6DjrSi5YtRiaDIYhIC7w70vNtBSk78l/Fmj i+vwbfrfqdVkLgLwpJ4qrIUEAVGUZhUq7uZCmeHEDIS5wPFQf5v+eQkEnetlXHn7Yv iQ3EISoxmVz+fLDJeyzC1HDMR1eAqRg5Gpq94LFI= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Kim Phillips , "Peter Zijlstra (Intel)" , Alexander Shishkin , Arnaldo Carvalho de Melo , Arnaldo Carvalho de Melo , Borislav Petkov , "H. Peter Anvin" , Jiri Olsa , Linus Torvalds , Mark Rutland , Namhyung Kim , Stephane Eranian , Thomas Gleixner , Vince Weaver , Ingo Molnar , Sasha Levin Subject: [PATCH 4.4 34/43] perf/x86/amd/ibs: Fix reading of the IBS OpData register and thus precise RIP validity Date: Mon, 11 Nov 2019 19:28:48 +0100 Message-Id: <20191111181324.929853900@linuxfoundation.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191111181246.772983347@linuxfoundation.org> References: <20191111181246.772983347@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Kim Phillips [ Upstream commit 317b96bb14303c7998dbcd5bc606bd8038fdd4b4 ] The loop that reads all the IBS MSRs into *buf stopped one MSR short of reading the IbsOpData register, which contains the RipInvalid status bit. Fix the offset_max assignment so the MSR gets read, so the RIP invalid evaluation is based on what the IBS h/w output, instead of what was left in memory. Signed-off-by: Kim Phillips Signed-off-by: Peter Zijlstra (Intel) Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Arnaldo Carvalho de Melo Cc: Borislav Petkov Cc: H. Peter Anvin Cc: Jiri Olsa Cc: Linus Torvalds Cc: Mark Rutland Cc: Namhyung Kim Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Fixes: d47e8238cd76 ("perf/x86-ibs: Take instruction pointer from ibs sample") Link: https://lkml.kernel.org/r/20191023150955.30292-1-kim.phillips@amd.com Signed-off-by: Ingo Molnar Signed-off-by: Sasha Levin --- arch/x86/kernel/cpu/perf_event_amd_ibs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/x86/kernel/cpu/perf_event_amd_ibs.c +++ b/arch/x86/kernel/cpu/perf_event_amd_ibs.c @@ -555,7 +555,7 @@ static int perf_ibs_handle_irq(struct pe if (event->attr.sample_type & PERF_SAMPLE_RAW) offset_max = perf_ibs->offset_max; else if (check_rip) - offset_max = 2; + offset_max = 3; else offset_max = 1; do {