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[157.230.128.187]) by smtp.gmail.com with ESMTPSA id 124sm5593686ywn.76.2020.01.13.07.47.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2020 07:47:40 -0800 (PST) Received: by 42.do-not-panic.com (Postfix, from userid 1000) id 7BDDC4018C; Mon, 13 Jan 2020 15:47:39 +0000 (UTC) Date: Mon, 13 Jan 2020 15:47:39 +0000 From: Luis Chamberlain To: Jari Ruusu Cc: Borislav Petkov , Fenghua Yu , Linus Torvalds , johannes.berg@intel.com, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: Fix built-in early-load Intel microcode alignment Message-ID: <20200113154739.GB11244@42.do-not-panic.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On Sun, Jan 12, 2020 at 03:00:53PM +0200, Jari Ruusu wrote: > Intel Software Developer's Manual, volume 3, chapter 9.11.6 says: > "Note that the microcode update must be aligned on a 16-byte > boundary and the size of the microcode update must be 1-KByte > granular" > > When early-load Intel microcode is loaded from initramfs, > userspace tool 'iucode_tool' has already 16-byte aligned those > microcode bits in that initramfs image. Image that was created > something like this: > > iucode_tool --write-earlyfw=FOO.cpio microcode-files... > > However, when early-load Intel microcode is loaded from built-in > firmware BLOB using CONFIG_EXTRA_FIRMWARE= kernel config option, > that 16-byte alignment is not guaranteed. Thanks for the patch! So what happens with you use the built-in firmware loader for the Intel microcode at this time? I am surprised this issue wasn't reported earlier, so thanks for picking it up, but to be complete such a change requires a bit more information. What exactly happens now? > Fix this by forcing all built-in firmware BLOBs to 16-byte > alignment. That's a huge stretch, see below. > Signed-off-by: Jari Ruusu > > --- a/drivers/base/firmware_loader/builtin/Makefile > +++ b/drivers/base/firmware_loader/builtin/Makefile > @@ -17,7 +17,7 @@ > filechk_fwbin = \ > echo "/* Generated by $(src)/Makefile */" ;\ > echo " .section .rodata" ;\ > - echo " .p2align $(ASM_ALIGN)" ;\ > + echo " .p2align 4" ;\ You are forcing 16 byte alignment to *all* built-in firmware, and some architectures may have a different requirement. If things used to work with ASM_ALIGN which is a construct only used for this code, but your change fixes it with Intel microcode loading -- it however *may* break things for other built-in firmware used. In particular if you note above it used to align things to 2^3 so 8 bytes if on CONFIG_64BIT, otherwise things get aligned to 2^2 so 4 bytes. So I'd like to determine first if we really need this. Then if so, either add a new global config option, and worst comes to worst figure out a way to do it per driver. I don't think we'd need it per driver. If set as a global new config option, we can use the same logic and allow an architecture override if the user / architecture kconfig configures it such: config ARCH_DEFAULT_FIRMWARE_ALIGNMENT string "Default architecture firmware aligmnent" "4" if 64BIT "3" if !64BIT config FIRMWARE_BUILTIN_ALIGN string "Built in firmware aligment requirement" default ARCH_DEFAULT_FIRMWARE_ALIGNMENT if !ARCH_CUSTOM_FIRMWARE_ALIGNMENT default ARCH_CUSTOM_FIRMWARE_ALIGNMENT_VAL if ARCH_CUSTOM_FIRMWARE_ALIGNMENT Some good description goes here Or something like that. Luis