From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE924C33CB1 for ; Tue, 14 Jan 2020 10:09:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A651B24677 for ; Tue, 14 Jan 2020 10:09:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1578996584; bh=S149emDsIbFFVWoWLMxxfD7hllL66UfhYl6+QGNZYZM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=RjR0ppJ12WY+4FzeQQEyoxYmgASPclb/CpHFQ1DhHwonGjA9fnXxPPzEyjaB9l3mS 76+MW+MYSBMuL6fRKBt9QVgJult7XtMzgrsOyy2U2je6zm1/VL4jEd3K7AlG0FJ5BB bl2TaUcbgyWSsK2znoP/mVHdst8Pi7yppIJN4p8o= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731398AbgANKJn (ORCPT ); Tue, 14 Jan 2020 05:09:43 -0500 Received: from mail.kernel.org ([198.145.29.99]:42848 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729629AbgANKJm (ORCPT ); Tue, 14 Jan 2020 05:09:42 -0500 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A9B6720678; Tue, 14 Jan 2020 10:09:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1578996582; bh=S149emDsIbFFVWoWLMxxfD7hllL66UfhYl6+QGNZYZM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vsqYYS3AWlOL8OLTResHNwddAHYXWgg+lEoCDTzSNZ970aWG/zJEMes8d4BoYypd7 Z0ZSWyBD8jYqpekyP1yZgHp1G+8paEbr43wzNAYLIj1wWBEDv5W6Rso944j6a2RCSF cWzp7CrNvsFRjTraIBGFc+gK8Cd9l3PhILZHtDwY= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Dmytro Fil , Ian Abbott Subject: [PATCH 4.14 20/39] staging: comedi: adv_pci1710: fix AI channels 16-31 for PCI-1713 Date: Tue, 14 Jan 2020 11:01:54 +0100 Message-Id: <20200114094343.563407396@linuxfoundation.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200114094336.210038037@linuxfoundation.org> References: <20200114094336.210038037@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Ian Abbott commit a9d3a9cedc1330c720e0ddde1978a8e7771da5ab upstream. The Advantech PCI-1713 has 32 analog input channels, but an incorrect bit-mask in the definition of the `PCI171X_MUX_CHANH(x)` and PCI171X_MUX_CHANL(x)` macros is causing channels 16 to 31 to be aliases of channels 0 to 15. Change the bit-mask value from 0xf to 0xff to fix it. Note that the channel numbers will have been range checked already, so the bit-mask isn't really needed. Fixes: 92c65e5553ed ("staging: comedi: adv_pci1710: define the mux control register bits") Reported-by: Dmytro Fil Cc: # v4.5+ Signed-off-by: Ian Abbott Link: https://lore.kernel.org/r/20191227170054.32051-1-abbotti@mev.co.uk Signed-off-by: Greg Kroah-Hartman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/adv_pci1710.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/drivers/staging/comedi/drivers/adv_pci1710.c +++ b/drivers/staging/comedi/drivers/adv_pci1710.c @@ -45,8 +45,8 @@ #define PCI171X_RANGE_UNI BIT(4) #define PCI171X_RANGE_GAIN(x) (((x) & 0x7) << 0) #define PCI171X_MUX_REG 0x04 /* W: A/D multiplexor control */ -#define PCI171X_MUX_CHANH(x) (((x) & 0xf) << 8) -#define PCI171X_MUX_CHANL(x) (((x) & 0xf) << 0) +#define PCI171X_MUX_CHANH(x) (((x) & 0xff) << 8) +#define PCI171X_MUX_CHANL(x) (((x) & 0xff) << 0) #define PCI171X_MUX_CHAN(x) (PCI171X_MUX_CHANH(x) | PCI171X_MUX_CHANL(x)) #define PCI171X_STATUS_REG 0x06 /* R: status register */ #define PCI171X_STATUS_IRQ BIT(11) /* 1=IRQ occurred */