From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84A73C352A3 for ; Mon, 10 Feb 2020 12:38:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 53F3F20733 for ; Mon, 10 Feb 2020 12:38:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1581338312; bh=Q4PnS2JzjpPbL/HeiLoeHjWVwjFTej7Ww8+17hOs4Wc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=TKsHzvN+rMCx0V//gj76ivUiy7mdt44MJFIIHytPZR86ZxDlqbALhXaWQDyBzgsfn wsnMRd3OmYDdXlYsJw8lAKT8TABX7hmLhNHrzViDHHzhFzMVrvvbAvxU02hFZTIaVz N5n9dsoMXMF8JkuMtgV2v/1lpc2dZ+Eh3RJPrQrU= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728546AbgBJMia (ORCPT ); Mon, 10 Feb 2020 07:38:30 -0500 Received: from mail.kernel.org ([198.145.29.99]:34024 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727698AbgBJMi3 (ORCPT ); Mon, 10 Feb 2020 07:38:29 -0500 Received: from localhost (unknown [209.37.97.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2AC2D20838; Mon, 10 Feb 2020 12:38:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1581338309; bh=Q4PnS2JzjpPbL/HeiLoeHjWVwjFTej7Ww8+17hOs4Wc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=r3m0UgddzQZJ2/wruTud7hCdaJDLM8xOi0ceHqYV4iZeANxdCvt7TZ6I1ccgdHIrU nAo0wcCFwYmJc+diB1C6VG6PHX6omw5Dld3R0F4Xzp3kRmCWu0w7+1SUN+Dy087qQK MSiv+J7/XDQF08mzKQHeP0kradu3LA8HD/nbIkMo= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Jonathan Hunter , Stephen Warren , Thierry Reding Subject: [PATCH 5.4 230/309] clk: tegra: Mark fuse clock as critical Date: Mon, 10 Feb 2020 04:33:06 -0800 Message-Id: <20200210122428.629151015@linuxfoundation.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200210122406.106356946@linuxfoundation.org> References: <20200210122406.106356946@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Stephen Warren commit bf83b96f87ae2abb1e535306ea53608e8de5dfbb upstream. For a little over a year, U-Boot on Tegra124 has configured the flow controller to perform automatic RAM re-repair on off->on power transitions of the CPU rail[1]. This is mandatory for correct operation of Tegra124. However, RAM re-repair relies on certain clocks, which the kernel must enable and leave running. The fuse clock is one of those clocks. Mark this clock as critical so that LP1 power mode (system suspend) operates correctly. [1] 3cc7942a4ae5 ARM: tegra: implement RAM repair Reported-by: Jonathan Hunter Cc: stable@vger.kernel.org Signed-off-by: Stephen Warren Signed-off-by: Thierry Reding Signed-off-by: Greg Kroah-Hartman --- drivers/clk/tegra/clk-tegra-periph.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -785,7 +785,11 @@ static struct tegra_periph_init_data gat GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0), GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0), GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0), - GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0), + /* + * Critical for RAM re-repair operation, which must occur on resume + * from LP1 system suspend and as part of CCPLEX cluster switching. + */ + GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, CLK_IS_CRITICAL), GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0), GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0), GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),