From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03556C433F1 for ; Mon, 20 Jul 2020 16:26:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D71272070A for ; Mon, 20 Jul 2020 16:26:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1595262366; bh=Qg6TVuwJkgK/nqLQ+vyedbQ43HGyb3v9UlsWhO8FsWY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=ViH6p21ztrvtCm5z2HZyRIwn2GFX3DP7zINbXjRwCsToAmEzsb5R+e3HFIAvcXiM0 uCaxFpbVnvV1Mnt+3u4wHUdPoeTmFZ8cmNNFUQtooL3BlLU4/cNnGOoLOWCtMQrRxr SYepLJiRnljMCDRJiqqhn/LSPDRA4o0YAhV+/0Uk= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732433AbgGTQAm (ORCPT ); Mon, 20 Jul 2020 12:00:42 -0400 Received: from mail.kernel.org ([198.145.29.99]:33798 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732431AbgGTQAm (ORCPT ); Mon, 20 Jul 2020 12:00:42 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id D7C6B22CAF; Mon, 20 Jul 2020 16:00:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1595260841; bh=Qg6TVuwJkgK/nqLQ+vyedbQ43HGyb3v9UlsWhO8FsWY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SgMKHaeQd/3dT3ZchNBUFz03gigJ1xx5UUx59+wgCwm1T9wq3ChNkm1eJovpQokIF p8b89Ioc5pbAb12fDkIAk77ZG9bJADg5QjADrPR5Iqc0bJGieGmT8P9RXB0r6sFErU 7lblwQP1Q1/PdWKa7t/xo6/9WRUptA5OnlwI4UyQ= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Krzysztof Kozlowski , Dinh Nguyen , Sasha Levin Subject: [PATCH 5.4 115/215] ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema Date: Mon, 20 Jul 2020 17:36:37 +0200 Message-Id: <20200720152825.670637440@linuxfoundation.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200720152820.122442056@linuxfoundation.org> References: <20200720152820.122442056@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Krzysztof Kozlowski [ Upstream commit d7adfe5ffed9faa05f8926223086b101e14f700d ] Fix dtschema validator warnings like: l2-cache@fffff000: $nodename:0: 'l2-cache@fffff000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Fixes: 475dc86d08de ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC") Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen Signed-off-by: Sasha Levin --- arch/arm/boot/dts/socfpga.dtsi | 2 +- arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 4f3993cc02279..4510308972209 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -710,7 +710,7 @@ ocram-ecc@ffd08144 { }; }; - L2: l2-cache@fffef000 { + L2: cache-controller@fffef000 { compatible = "arm,pl310-cache"; reg = <0xfffef000 0x1000>; interrupts = <0 38 0x04>; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 2a86e72d97918..906bfb580e9e7 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -636,7 +636,7 @@ sdr: sdr@ffcfb100 { reg = <0xffcfb100 0x80>; }; - L2: l2-cache@fffff000 { + L2: cache-controller@fffff000 { compatible = "arm,pl310-cache"; reg = <0xfffff000 0x1000>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; -- 2.25.1