Hi!

> [ Upstream commit 071995c877a8646209d55ff8edddd2b054e7424c ]
> 
> Fix a bug where driver did not verify Hardware pin capabilities for
> PTP functions.
> 
> Fixes: ee7f12205abc ("net/mlx5e: Implement 1PPS support")
> Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com>
> Reviewed-by: Ariel Levkovich <lariel@mellanox.com>
> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
> Signed-off-by: Sasha Levin <sashal@kernel.org>

> +
>  static int mlx5_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
>  			   enum ptp_pin_function func, unsigned int chan)
>  {
> -	return (func == PTP_PF_PHYSYNC) ? -EOPNOTSUPP : 0;
> +	struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock,
> +						ptp_info);
> +
> +	switch (func) {
> +	case PTP_PF_NONE:
> +		return 0;
> +	case PTP_PF_EXTTS:
> +		return !(clock->pps_info.pin_caps[pin] &
> +			 MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_IN);
> +	case PTP_PF_PEROUT:
> +		return !(clock->pps_info.pin_caps[pin] &
> +			 MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_OUT);
> +	default:
> +		return -EOPNOTSUPP;
> +	}
> +
> +	return -EOPNOTSUPP;
>  }

The last return statement is unreachable code. I'm not sure if it will
provoke any warnings, but it looks ugly.

Signed-off-by: Pavel Machek (CIP) <pavel@denx.de>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
index 2d55b7c22c03..a804f92ccf23 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
@@ -431,8 +431,6 @@ static int mlx5_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
 	default:
 		return -EOPNOTSUPP;
 	}
-
-	return -EOPNOTSUPP;
 }
 
 static const struct ptp_clock_info mlx5_ptp_clock_info = {


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