From: gregkh@linuxfoundation.org
To: linux-kernel@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
stable@vger.kernel.org, Nadeem Athani <nadeem@cadence.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Sasha Levin <sashal@kernel.org>
Subject: [PATCH 5.10 43/49] PCI: cadence: Retrain Link to work around Gen2 training defect
Date: Wed, 10 Mar 2021 14:23:54 +0100 [thread overview]
Message-ID: <20210310132323.306156698@linuxfoundation.org> (raw)
In-Reply-To: <20210310132321.948258062@linuxfoundation.org>
From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
From: Nadeem Athani <nadeem@cadence.com>
[ Upstream commit 4740b969aaf58adeca6829947a3ad8da423976cf ]
Cadence controller will not initiate autonomous speed change if strapped
as Gen2. The Retrain Link bit is set as quirk to enable this speed change.
Link: https://lore.kernel.org/r/20210209144622.26683-3-nadeem@cadence.com
Signed-off-by: Nadeem Athani <nadeem@cadence.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/pci/controller/cadence/pci-j721e.c | 3 +
.../controller/cadence/pcie-cadence-host.c | 81 ++++++++++++++-----
drivers/pci/controller/cadence/pcie-cadence.h | 11 ++-
3 files changed, 76 insertions(+), 19 deletions(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 586b9d69fa5e..d34ca0fda0f6 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -63,6 +63,7 @@ enum j721e_pcie_mode {
struct j721e_pcie_data {
enum j721e_pcie_mode mode;
+ bool quirk_retrain_flag;
};
static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
@@ -270,6 +271,7 @@ static struct pci_ops cdns_ti_pcie_host_ops = {
static const struct j721e_pcie_data j721e_pcie_rc_data = {
.mode = PCI_MODE_RC,
+ .quirk_retrain_flag = true,
};
static const struct j721e_pcie_data j721e_pcie_ep_data = {
@@ -378,6 +380,7 @@ static int j721e_pcie_probe(struct platform_device *pdev)
bridge->ops = &cdns_ti_pcie_host_ops;
rc = pci_host_bridge_priv(bridge);
+ rc->quirk_retrain_flag = data->quirk_retrain_flag;
cdns_pcie = &rc->pcie;
cdns_pcie->dev = dev;
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 1cb7cfc75d6e..73dcf8cf98fb 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -77,6 +77,68 @@ static struct pci_ops cdns_pcie_host_ops = {
.write = pci_generic_config_write,
};
+static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie)
+{
+ struct device *dev = pcie->dev;
+ int retries;
+
+ /* Check if the link is up or not */
+ for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
+ if (cdns_pcie_link_up(pcie)) {
+ dev_info(dev, "Link up\n");
+ return 0;
+ }
+ usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int cdns_pcie_retrain(struct cdns_pcie *pcie)
+{
+ u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
+ u16 lnk_stat, lnk_ctl;
+ int ret = 0;
+
+ /*
+ * Set retrain bit if current speed is 2.5 GB/s,
+ * but the PCIe root port support is > 2.5 GB/s.
+ */
+
+ lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off +
+ PCI_EXP_LNKCAP));
+ if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
+ return ret;
+
+ lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA);
+ if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
+ lnk_ctl = cdns_pcie_rp_readw(pcie,
+ pcie_cap_off + PCI_EXP_LNKCTL);
+ lnk_ctl |= PCI_EXP_LNKCTL_RL;
+ cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL,
+ lnk_ctl);
+
+ ret = cdns_pcie_host_wait_for_link(pcie);
+ }
+ return ret;
+}
+
+static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc)
+{
+ struct cdns_pcie *pcie = &rc->pcie;
+ int ret;
+
+ ret = cdns_pcie_host_wait_for_link(pcie);
+
+ /*
+ * Retrain link for Gen2 training defect
+ * if quirk flag is set.
+ */
+ if (!ret && rc->quirk_retrain_flag)
+ ret = cdns_pcie_retrain(pcie);
+
+ return ret;
+}
static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
{
@@ -399,23 +461,6 @@ static int cdns_pcie_host_init(struct device *dev,
return cdns_pcie_host_init_address_translation(rc);
}
-static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie)
-{
- struct device *dev = pcie->dev;
- int retries;
-
- /* Check if the link is up or not */
- for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
- if (cdns_pcie_link_up(pcie)) {
- dev_info(dev, "Link up\n");
- return 0;
- }
- usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
- }
-
- return -ETIMEDOUT;
-}
-
int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
{
struct device *dev = rc->pcie.dev;
@@ -458,7 +503,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
return ret;
}
- ret = cdns_pcie_host_wait_for_link(pcie);
+ ret = cdns_pcie_host_start_link(rc);
if (ret)
dev_dbg(dev, "PCIe link never came up\n");
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index feed1e3038f4..6705a5fedfbb 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -119,7 +119,7 @@
* Root Port Registers (PCI configuration space for the root port function)
*/
#define CDNS_PCIE_RP_BASE 0x00200000
-
+#define CDNS_PCIE_RP_CAP_OFFSET 0xc0
/*
* Address Translation Registers
@@ -290,6 +290,7 @@ struct cdns_pcie {
* @device_id: PCI device ID
* @avail_ib_bar: Satus of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or
* available
+ * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2
*/
struct cdns_pcie_rc {
struct cdns_pcie pcie;
@@ -298,6 +299,7 @@ struct cdns_pcie_rc {
u32 vendor_id;
u32 device_id;
bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB];
+ bool quirk_retrain_flag;
};
/**
@@ -413,6 +415,13 @@ static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie,
cdns_pcie_write_sz(addr, 0x2, value);
}
+static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg)
+{
+ void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
+
+ return cdns_pcie_read_sz(addr, 0x2);
+}
+
/* Endpoint Function register access */
static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn,
u32 reg, u8 value)
--
2.30.1
next prev parent reply other threads:[~2021-03-10 13:26 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-10 13:23 [PATCH 5.10 00/49] 5.10.23-rc1 review gregkh
2021-03-10 13:23 ` [PATCH 5.10 01/49] ACPICA: Fix race in generic_serial_bus (I2C) and GPIO op_region parameter handling gregkh
2021-03-10 13:23 ` [PATCH 5.10 02/49] [PATCH v2] ASoC: SOF: Intel: broadwell: fix mutual exclusion with catpt driver gregkh
2021-03-10 13:23 ` [PATCH 5.10 03/49] nvme-pci: mark Kingston SKC2000 as not supporting the deepest power state gregkh
2021-03-10 13:23 ` [PATCH 5.10 04/49] parisc: Enable -mlong-calls gcc option with CONFIG_COMPILE_TEST gregkh
2021-03-10 13:23 ` [PATCH 5.10 05/49] arm64: Make CPU_BIG_ENDIAN depend on ld.bfd or ld.lld 13.0.0+ gregkh
2021-03-10 13:23 ` [PATCH 5.10 06/49] btrfs: export and rename qgroup_reserve_meta gregkh
2021-03-10 13:23 ` [PATCH 5.10 07/49] btrfs: dont flush from btrfs_delayed_inode_reserve_metadata gregkh
2021-03-10 13:23 ` [PATCH 5.10 08/49] iommu/amd: Fix sleeping in atomic in increase_address_space() gregkh
2021-03-10 13:23 ` [PATCH 5.10 09/49] ASoC: intel: sof_rt5682: Add quirk for Dooly gregkh
2021-03-10 13:23 ` [PATCH 5.10 10/49] Bluetooth: btqca: Add valid le states quirk gregkh
2021-03-10 13:23 ` [PATCH 5.10 11/49] mwifiex: pcie: skip cancel_work_sync() on reset failure path gregkh
2021-03-10 13:23 ` [PATCH 5.10 12/49] ASoC: Intel: sof_sdw: add quirk for new TigerLake-SDCA device gregkh
2021-03-10 13:23 ` [PATCH 5.10 13/49] bus: ti-sysc: Implement GPMC debug quirk to drop platform data gregkh
2021-03-10 13:23 ` [PATCH 5.10 14/49] net: ipa: ignore CHANNEL_NOT_RUNNING errors gregkh
2021-03-10 17:36 ` Naresh Kamboju
2021-03-10 17:48 ` Alex Elder
2021-03-10 18:00 ` Greg Kroah-Hartman
2021-03-10 18:27 ` Greg Kroah-Hartman
2021-03-10 13:23 ` [PATCH 5.10 15/49] platform/x86: acer-wmi: Cleanup ACER_CAP_FOO defines gregkh
2021-03-10 13:23 ` [PATCH 5.10 16/49] platform/x86: acer-wmi: Cleanup accelerometer device handling gregkh
2021-03-10 13:23 ` [PATCH 5.10 17/49] platform/x86: acer-wmi: Add new force_caps module parameter gregkh
2021-03-10 13:23 ` [PATCH 5.10 18/49] platform/x86: acer-wmi: Add ACER_CAP_SET_FUNCTION_MODE capability flag gregkh
2021-03-10 13:23 ` [PATCH 5.10 19/49] platform/x86: acer-wmi: Add support for SW_TABLET_MODE on Switch devices gregkh
2021-03-10 13:23 ` [PATCH 5.10 20/49] platform/x86: acer-wmi: Add ACER_CAP_KBD_DOCK quirk for the Aspire Switch 10E SW3-016 gregkh
2021-03-10 13:23 ` [PATCH 5.10 21/49] HID: mf: add support for 0079:1846 Mayflash/Dragonrise USB Gamecube Adapter gregkh
2021-03-10 13:23 ` [PATCH 5.10 22/49] media: cx23885: add more quirks for reset DMA on some AMD IOMMU gregkh
2021-03-10 13:23 ` [PATCH 5.10 23/49] ACPI: video: Add DMI quirk for GIGABYTE GB-BXBT-2807 gregkh
2021-03-10 20:04 ` Pavel Machek
2021-03-10 20:04 ` Pavel Machek
2021-03-11 12:37 ` Greg KH
2021-03-10 13:23 ` [PATCH 5.10 24/49] ASoC: Intel: bytcr_rt5640: Add quirk for ARCHOS Cesium 140 gregkh
2021-03-10 13:23 ` [PATCH 5.10 25/49] usb: cdns3: host: add .suspend_quirk for xhci-plat.c gregkh
2021-03-10 13:23 ` [PATCH 5.10 26/49] usb: cdns3: host: add xhci_plat_priv quirk XHCI_SKIP_PHY_INIT gregkh
2021-03-10 13:23 ` [PATCH 5.10 27/49] usb: cdns3: add quirk for enable runtime pm by default gregkh
2021-03-10 13:23 ` [PATCH 5.10 28/49] usb: cdns3: fix NULL pointer dereference on no platform data gregkh
2021-03-10 13:23 ` [PATCH 5.10 29/49] PCI: Add function 1 DMA alias quirk for Marvell 9215 SATA controller gregkh
2021-03-10 13:23 ` [PATCH 5.10 30/49] KVM: x86: Supplement __cr4_reserved_bits() with X86_FEATURE_PCID check gregkh
2021-03-10 13:23 ` [PATCH 5.10 31/49] ASoC: Intel: sof_sdw: add missing TGL_HDMI quirk for Dell SKU 0A32 gregkh
2021-03-10 13:23 ` [PATCH 5.10 32/49] scsi: ufs-mediatek: Enable UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL gregkh
2021-03-10 13:23 ` [PATCH 5.10 33/49] scsi: ufs: Add a quirk to permit overriding UniPro defaults gregkh
2021-03-10 13:23 ` [PATCH 5.10 34/49] misc: eeprom_93xx46: Add quirk to support Microchip 93LC46B eeprom gregkh
2021-03-10 13:23 ` [PATCH 5.10 35/49] scsi: ufs: Introduce a quirk to allow only page-aligned sg entries gregkh
2021-03-10 13:23 ` [PATCH 5.10 36/49] scsi: ufs: ufs-exynos: Apply vendor-specific values for three timeouts gregkh
2021-03-10 13:23 ` [PATCH 5.10 37/49] scsi: ufs: ufs-exynos: Use UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE gregkh
2021-03-10 13:23 ` [PATCH 5.10 38/49] drm/msm/a5xx: Remove overwriting A5XX_PC_DBG_ECO_CNTL register gregkh
2021-03-10 13:23 ` [PATCH 5.10 39/49] mmc: sdhci-of-dwcmshc: set SDHCI_QUIRK2_PRESET_VALUE_BROKEN gregkh
2021-03-10 13:23 ` [PATCH 5.10 40/49] HID: i2c-hid: Add I2C_HID_QUIRK_NO_IRQ_AFTER_RESET for ITE8568 EC on Voyo Winpad A15 gregkh
2021-03-10 13:23 ` [PATCH 5.10 41/49] ALSA: usb-audio: Add DJM750 to Pioneer mixer quirk gregkh
2021-03-10 13:23 ` [PATCH 5.10 42/49] ALSA: usb-audio: add mixer quirks for Pioneer DJM-900NXS2 gregkh
2021-03-10 13:23 ` gregkh [this message]
2021-03-10 13:23 ` [PATCH 5.10 44/49] ASoC: Intel: sof_sdw: reorganize quirks by generation gregkh
2021-03-10 13:23 ` [PATCH 5.10 45/49] ASoC: Intel: sof_sdw: add quirk for HP Spectre x360 convertible gregkh
2021-03-10 13:23 ` [PATCH 5.10 46/49] scsi: ufs: Fix a duplicate dev quirk number gregkh
2021-03-10 13:23 ` [PATCH 5.10 47/49] KVM: SVM: Clear the CR4 register on reset gregkh
2021-03-10 13:23 ` [PATCH 5.10 48/49] nvme-pci: mark Seagate Nytro XM1440 as QUIRK_NO_NS_DESC_LIST gregkh
2021-03-10 13:24 ` [PATCH 5.10 49/49] nvme-pci: add quirks for Lexar 256GB SSD gregkh
2021-03-10 17:38 ` [PATCH 5.10 00/49] 5.10.23-rc1 review Naresh Kamboju
2021-03-10 17:58 ` Guenter Roeck
2021-03-10 18:26 ` Greg Kroah-Hartman
2021-03-10 18:27 ` Greg Kroah-Hartman
2021-03-10 20:00 ` Shuah Khan
2021-03-11 2:38 ` Samuel Zou
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