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Wysocki" Cc: Linux PM , Linux Kernel Mailing List , "Deucher, Alexander" , Jason Bagavatsingham , "Pierre-Loup A . Griffais" , "Fontenot, Nathan" , "Rafael J . Wysocki" , Borislav Petkov , the arch/x86 maintainers , Stable Subject: Re: [PATCH v3] x86, sched: Fix the AMD CPPC maximum perf on some specific generations Message-ID: <20210423125208.GA688865@hr-amd> References: <20210423023928.688767-1-ray.huang@amd.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: X-Originating-IP: [58.247.170.245] X-ClientProxiedBy: HK2PR0302CA0001.apcprd03.prod.outlook.com (2603:1096:202::11) To MWHPR12MB1248.namprd12.prod.outlook.com (2603:10b6:300:12::21) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from hr-amd (58.247.170.245) by HK2PR0302CA0001.apcprd03.prod.outlook.com (2603:1096:202::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.16 via Frontend Transport; Fri, 23 Apr 2021 12:52:27 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 79353791-4971-4014-6e45-08d90656a77d X-MS-TrafficTypeDiagnostic: MWHPR12MB1789: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1824; 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X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?bOaCw4LoXaZkcKpA4gyhZ+jx47h1ktJOgS8ZudBB2jduW3BCLtXNDYdyac8+?= =?us-ascii?Q?HfnopXGtcUT7KSPi7JJwJawiK0smsqURknT9Ep1tTjzIF5HlJtyDt1vT4HbY?= =?us-ascii?Q?2XB8D1rlkOvE/bLCkPYBQm/dDkF+KJtwpWrlVoJVmjvpVUdzeNdxB97mDKNA?= =?us-ascii?Q?8SHWvKhY6Jm0Ac19jEcrrdRWW/0FmzMcZ1CPWhbTLw6grgXODbnGD486y2MM?= =?us-ascii?Q?FIyi723qeX+Kz+CSEdsFSivffcZuVvUa2rUfYi0+uMfjAOfzPaqUdPIGWNbI?= =?us-ascii?Q?0yE1w7Sh3i/aoxwYE22auxg4Tk0RUPcjmWy+HoCR+9lGXSK2x4H4E3UPmOSW?= =?us-ascii?Q?fsTByNe3jAWnRCS4xV9FvLtFGuCD1mcinDSaB2ijls8Cx0frPJa8UDrfBKvL?= =?us-ascii?Q?ejN4Ieg5zMSadz8Eg2D62MdFvjd9Vq1W3fZ0qc2l5BfycCCy1OZwx9ej+Ab1?= =?us-ascii?Q?V/0WcsowbyJAcMpqFQgFR92nIMFpdPX+AaF4KZ/+XhuNwRUpcwo025mcp6Zt?= =?us-ascii?Q?ZQ98G9R0QaZCSBqgeLnOboYFfxfrPKMEfqUEe9Y6uGbwc/oPvK0sxv+4LyHv?= =?us-ascii?Q?vFwSiGFSV2lSPteGAKqr5G1EaEJ49SoAzJEgLhV8BdpgWhhC9P/TBrVay2U7?= =?us-ascii?Q?3W4bId9KHbWOxCKEY6otiafcMHncUFfJmD4WpiE77kqKwos/RXE9bMbJywqw?= =?us-ascii?Q?H/YXaYMXJxvhzZAUXyaomwFTLcMl1usW9AMfLs5fQjW0NAFp7Cj6ifVuPH5g?= =?us-ascii?Q?OfeRIwGu1AWCPb3erjRu1f6wpjbeW6wYeZQo7AWqUSbmxAnM/9tHB00CDxne?= =?us-ascii?Q?NWSgwFwWCEPoWQ1YY5e21CzTYDzG3GjV0KKtBqADFT9607e4a7NAsBxFcSew?= =?us-ascii?Q?hH6cz321CR/I6u+DcQVkhJ9YonzoDFCOzYpXEQLbjcSWFM8wfYY/hid2PDNt?= =?us-ascii?Q?f5J+8UN7TAP6RzxABKx33u1zMNh67dP+7ZZ2KaMriga5b5qDzL/9yUUxiq2T?= =?us-ascii?Q?VqJxBofXG2BPnp/0A4Z93fgVwUkyRG+eksjdcnRqrl7r2mbZv2nVssaMzsp4?= =?us-ascii?Q?s8hEInmmhDuWipn+GUViygBoAuebN3kTj2sJKtle+Eyonex6fNVUWKdJahd3?= =?us-ascii?Q?fTc1Z3veVrjpqXBYnK2tu93nIagQfoav05wlb0RnQZxOYGVp8D2XpMlRtErX?= =?us-ascii?Q?2Lg1CnPueohtB222B7FdJsNp+0fEfauj81DSdKBMgNiDcpSJEzKsZ3lq7EW9?= =?us-ascii?Q?MsxyxelpyXauOo22hHmKqUPQp+wjjlbNPBAIrFlRxUGgaOVH5sL+y9bRX0GY?= =?us-ascii?Q?udwdBCmi0gEsqIiJTmsxw2K3?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 79353791-4971-4014-6e45-08d90656a77d X-MS-Exchange-CrossTenant-AuthSource: MWHPR12MB1248.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2021 12:52:29.8304 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: WrSS6knrC1iPMiznyXbvFX4vfMmw6VED48oaQZ++Id2Av6C8KNtrYktSEzfD0a14khP5UlaOM7SmdWjPaByHjA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1789 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On Fri, Apr 23, 2021 at 08:09:49PM +0800, Rafael J. Wysocki wrote: > On Fri, Apr 23, 2021 at 4:40 AM Huang Rui wrote: > > > > Some AMD Ryzen generations has different calculation method on maximum > > perf. 255 is not for all asics, some specific generations should use 166 > > as the maximum perf. Otherwise, it will report incorrect frequency value > > like below: > > > > ~ =1B$B"*=1B(B lscpu | grep MHz > > CPU MHz: 3400.000 > > CPU max MHz: 7228.3198 > > CPU min MHz: 2200.0000 > > > > Fixes: 41ea667227ba ("x86, sched: Calculate frequency invariance for AM= D systems") > > Fixes: 3c55e94c0ade ("cpufreq: ACPI: Extend frequency tables to cover b= oost frequencies") > > > > Reported-by: Jason Bagavatsingham > > Tested-by: Jason Bagavatsingham > > Bugzilla: https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3= A%2F%2Fbugzilla.kernel.org%2Fshow_bug.cgi%3Fid%3D211791&data=3D04%7C01%= 7Cray.huang%40amd.com%7Ce9ed877387fc4b7431e108d90650b98f%7C3dd8961fe4884e60= 8e11a82d994e183d%7C0%7C0%7C637547766057950380%7CUnknown%7CTWFpbGZsb3d8eyJWI= joiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sd= ata=3DR%2FSBLaYOhTjrli%2BT054EytKeh8VmN7ryOQuQW4mgz6M%3D&reserved=3D0 > > Signed-off-by: Huang Rui > > Cc: Alex Deucher > > Cc: Nathan Fontenot > > Cc: Rafael J. Wysocki > > Cc: Borislav Petkov > > Cc: x86@kernel.org > > Cc: stable@vger.kernel.org > > --- > > > > Changes from V1 -> V2: > > - Enhance the commit message. > > - Move amd_get_highest_perf() into amd.c. > > - Refine the implementation of switch-case. > > - Cc stable mail list. > > > > Changes from V2 -> V3: > > - Move the update into cppc_get_perf_caps() to correct the highest perf= value in > > the API. > > > > --- > > arch/x86/include/asm/processor.h | 2 ++ > > arch/x86/kernel/cpu/amd.c | 22 ++++++++++++++++++++++ > > drivers/acpi/cppc_acpi.c | 8 ++++++-- > > 3 files changed, 30 insertions(+), 2 deletions(-) > > > > diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/pr= ocessor.h > > index f1b9ed5efaa9..908bcaea1361 100644 > > --- a/arch/x86/include/asm/processor.h > > +++ b/arch/x86/include/asm/processor.h > > @@ -804,8 +804,10 @@ DECLARE_PER_CPU(u64, msr_misc_features_shadow); > > > > #ifdef CONFIG_CPU_SUP_AMD > > extern u32 amd_get_nodes_per_socket(void); > > +extern u32 amd_get_highest_perf(void); > > #else > > static inline u32 amd_get_nodes_per_socket(void) { return 0; } > > +static inline u32 amd_get_highest_perf(void) { return 0; } > > #endif > > > > static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t= leaves) > > diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c > > index 347a956f71ca..aadb691d9357 100644 > > --- a/arch/x86/kernel/cpu/amd.c > > +++ b/arch/x86/kernel/cpu/amd.c > > @@ -1170,3 +1170,25 @@ void set_dr_addr_mask(unsigned long mask, int dr) > > break; > > } > > } > > + > > +u32 amd_get_highest_perf(void) > > +{ > > + struct cpuinfo_x86 *c =3D &boot_cpu_data; > > + u32 cppc_max_perf =3D 225; > > + > > + switch (c->x86) { > > + case 0x17: > > + if ((c->x86_model >=3D 0x30 && c->x86_model < 0x40) || > > + (c->x86_model >=3D 0x70 && c->x86_model < 0x80)) > > + cppc_max_perf =3D 166; > > + break; > > + case 0x19: > > + if ((c->x86_model >=3D 0x20 && c->x86_model < 0x30) || > > + (c->x86_model >=3D 0x40 && c->x86_model < 0x70)) > > + cppc_max_perf =3D 166; > > + break; > > + } > > + > > + return cppc_max_perf; > > +} > > +EXPORT_SYMBOL_GPL(amd_get_highest_perf); > > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c > > index 69057fcd2c04..58e72b6e222f 100644 > > --- a/drivers/acpi/cppc_acpi.c > > +++ b/drivers/acpi/cppc_acpi.c > > @@ -1107,8 +1107,12 @@ int cppc_get_perf_caps(int cpunum, struct cppc_p= erf_caps *perf_caps) > > } > > } > > > > - cpc_read(cpunum, highest_reg, &high); > > - perf_caps->highest_perf =3D high; > > + if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) { >=20 > This is a generic arch-independent file. >=20 > Can we avoid adding the x86-specific check here? OK, I see, it will be used by ARM as well. Can I rollback to implementation of V2: https://lore.kernel.org/r/20210421023807.1540290-1-ray.huang@amd.com If stick to add quirk in cppc_acpi.c and avoid x86-specific check at the same time here, the code will not be straight forward. Or will you have any other good idea? Thanks, Ray