From: "Marek Behún" <kabel@kernel.org>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Sasha Levin <sashal@kernel.org>
Cc: pali@kernel.org, stable@vger.kernel.org,
"Marek Behún" <kabel@kernel.org>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>
Subject: [PATCH 5.4 19/22] PCI: aardvark: Set PCI Bridge Class Code to PCI Bridge
Date: Thu, 25 Nov 2021 01:26:13 +0100 [thread overview]
Message-ID: <20211125002616.31363-20-kabel@kernel.org> (raw)
In-Reply-To: <20211125002616.31363-1-kabel@kernel.org>
From: Pali Rohár <pali@kernel.org>
commit 84e1b4045dc887b78bdc87d92927093dc3a465aa upstream.
Aardvark controller has something like config space of a Root Port
available at offset 0x0 of internal registers - these registers are used
for implementation of the emulated bridge.
The default value of Class Code of this bridge corresponds to a RAID Mass
storage controller, though. (This is probably intended for when the
controller is used as Endpoint.)
Change the Class Code to correspond to a PCI Bridge.
Add comment explaining this change.
Link: https://lore.kernel.org/r/20211028185659.20329-6-kabel@kernel.org
Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
Signed-off-by: Marek Behún <kabel@kernel.org>
---
drivers/pci/controller/pci-aardvark.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 2fe6b3aa8919..3265709bfba9 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -502,6 +502,26 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL;
advk_writel(pcie, reg, VENDOR_ID_REG);
+ /*
+ * Change Class Code of PCI Bridge device to PCI Bridge (0x600400),
+ * because the default value is Mass storage controller (0x010400).
+ *
+ * Note that this Aardvark PCI Bridge does not have compliant Type 1
+ * Configuration Space and it even cannot be accessed via Aardvark's
+ * PCI config space access method. Something like config space is
+ * available in internal Aardvark registers starting at offset 0x0
+ * and is reported as Type 0. In range 0x10 - 0x34 it has totally
+ * different registers.
+ *
+ * Therefore driver uses emulation of PCI Bridge which emulates
+ * access to configuration space via internal Aardvark registers or
+ * emulated configuration buffer.
+ */
+ reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG);
+ reg &= ~0xffffff00;
+ reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
+ advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG);
+
/* Disable Root Bridge I/O space, memory space and bus mastering */
reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
--
2.32.0
next prev parent reply other threads:[~2021-11-25 0:32 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-25 0:25 [PATCH 5.4 00/22] Armada 3720 PCIe fixes for 5.4 Marek Behún
2021-11-25 0:25 ` [PATCH 5.4 01/22] PCI: aardvark: Wait for endpoint to be ready before training link Marek Behún
2021-11-25 0:25 ` [PATCH 5.4 02/22] PCI: aardvark: Fix big endian support Marek Behún
2021-11-25 0:25 ` [PATCH 5.4 03/22] PCI: aardvark: Train link immediately after enabling training Marek Behún
2021-11-25 0:25 ` [PATCH 5.4 04/22] PCI: aardvark: Improve link training Marek Behún
2021-11-25 0:25 ` [PATCH 5.4 05/22] PCI: aardvark: Issue PERST via GPIO Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 06/22] PCI: aardvark: Replace custom macros by standard linux/pci_regs.h macros Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 07/22] PCI: aardvark: Don't touch PCIe registers if no card connected Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 08/22] PCI: aardvark: Fix compilation on s390 Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 09/22] PCI: aardvark: Move PCIe reset card code to advk_pcie_train_link() Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 10/22] PCI: aardvark: Update comment about disabling link training Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 11/22] PCI: pci-bridge-emul: Fix array overruns, improve safety Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 12/22] PCI: aardvark: Configure PCIe resources from 'ranges' DT property Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 13/22] PCI: aardvark: Fix PCIe Max Payload Size setting Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 14/22] PCI: aardvark: Deduplicate code in advk_pcie_rd_conf() Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 15/22] PCI: aardvark: Implement re-issuing config requests on CRS response Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 16/22] PCI: aardvark: Simplify initialization of rootcap on virtual bridge Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 17/22] PCI: aardvark: Fix link training Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 18/22] PCI: aardvark: Fix support for bus mastering and PCI_COMMAND on emulated bridge Marek Behún
2021-11-25 0:26 ` Marek Behún [this message]
2021-11-25 0:26 ` [PATCH 5.4 20/22] PCI: aardvark: Fix support for PCI_BRIDGE_CTL_BUS_RESET " Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 21/22] pinctrl: armada-37xx: Correct PWM pins definitions Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 22/22] arm64: dts: marvell: armada-37xx: Set pcie_reset_pin to gpio function Marek Behún
2021-11-28 13:00 ` [PATCH 5.4 00/22] Armada 3720 PCIe fixes for 5.4 Greg Kroah-Hartman
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