From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6860FC4332F for ; Fri, 4 Feb 2022 09:21:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357455AbiBDJVe (ORCPT ); Fri, 4 Feb 2022 04:21:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357397AbiBDJVR (ORCPT ); Fri, 4 Feb 2022 04:21:17 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B1E0C06174E; Fri, 4 Feb 2022 01:21:17 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 836E9B836B9; Fri, 4 Feb 2022 09:21:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CCF46C004E1; Fri, 4 Feb 2022 09:21:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1643966474; bh=Xg9f6CFllZYrzcO1n0gxcgeybqgoqA71gctmrnJvsx0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UrmFBJIpG5GcIC7LtQXTT/MRWa72iG23gBaV6NPvP8Z/Yl1RpDfGGQHpQGOwFOj8j v5xnAypoOnYXhtc5LQGzLz28S1n7HVaE/B086ZyXHdTA7Ws43IsP8kyD9zrNLeTetO arWLhWq1Tw7xVSFAGGNwQT7igH6FazFzu8F1bLhE= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Ailin Xu , Tony Luck , Borislav Petkov Subject: [PATCH 5.10 11/25] x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN Date: Fri, 4 Feb 2022 10:20:18 +0100 Message-Id: <20220204091914.657258819@linuxfoundation.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220204091914.280602669@linuxfoundation.org> References: <20220204091914.280602669@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Tony Luck commit e464121f2d40eabc7d11823fb26db807ce945df4 upstream. Missed adding the Icelake-D CPU to the list. It uses the same MSRs to control and read the inventory number as all the other models. Fixes: dc6b025de95b ("x86/mce: Add Xeon Icelake to list of CPUs that support PPIN") Reported-by: Ailin Xu Signed-off-by: Tony Luck Signed-off-by: Borislav Petkov Cc: Link: https://lore.kernel.org/r/20220121174743.1875294-2-tony.luck@intel.com Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/mce/intel.c | 1 + 1 file changed, 1 insertion(+) --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuin case INTEL_FAM6_BROADWELL_X: case INTEL_FAM6_SKYLAKE_X: case INTEL_FAM6_ICELAKE_X: + case INTEL_FAM6_ICELAKE_D: case INTEL_FAM6_SAPPHIRERAPIDS_X: case INTEL_FAM6_XEON_PHI_KNL: case INTEL_FAM6_XEON_PHI_KNM: