* [PATCH 1/5] arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs
[not found] <20220215201008.15235-1-nm@ti.com>
@ 2022-02-15 20:10 ` Nishanth Menon
2022-02-15 20:10 ` [PATCH 2/5] arm64: dts: ti: k3-j721e: " Nishanth Menon
` (3 subsequent siblings)
4 siblings, 0 replies; 5+ messages in thread
From: Nishanth Menon @ 2022-02-15 20:10 UTC (permalink / raw)
To: Tero Kristo, Vignesh Raghavendra, Marc Zyngier
Cc: linux-kernel, devicetree, linux-arm-kernel, Krzysztof Kozlowski,
Rob Herring, Nishanth Menon, stable
Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A53 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.
Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.
[1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
[3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map
Fixes: ea47eed33a3f ("arm64: dts: ti: Add Support for AM654 SoC")
Cc: stable@vger.kernel.org # 5.10+
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
Testing: based on next-20220215
am65xx-evm Log: https://gist.github.com/nmenon/7e086c4d96d928429b9cd987a6e16b82
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 ++++-
arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index ce8bb4a61011..e749343acced 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -35,7 +35,10 @@ gic500: interrupt-controller@1800000 {
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01880000 0x00 0x90000>; /* GICR */
+ <0x00 0x01880000 0x00 0x90000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
/*
* vcpumntirq:
* virtual CPU interface maintenance interrupt
diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
index a58a39fa42db..c538a0bf3cdd 100644
--- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
@@ -86,6 +86,7 @@ cbass_main: bus@100000 {
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
--
2.31.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/5] arm64: dts: ti: k3-j721e: Fix gic-v3 compatible regs
[not found] <20220215201008.15235-1-nm@ti.com>
2022-02-15 20:10 ` [PATCH 1/5] arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs Nishanth Menon
@ 2022-02-15 20:10 ` Nishanth Menon
2022-02-15 20:10 ` [PATCH 3/5] arm64: dts: ti: k3-j7200: " Nishanth Menon
` (2 subsequent siblings)
4 siblings, 0 replies; 5+ messages in thread
From: Nishanth Menon @ 2022-02-15 20:10 UTC (permalink / raw)
To: Tero Kristo, Vignesh Raghavendra, Marc Zyngier
Cc: linux-kernel, devicetree, linux-arm-kernel, Krzysztof Kozlowski,
Rob Herring, Nishanth Menon, stable
Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A72 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.
Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.
[1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
[3] https://developer.arm.com/documentation/100095/0002/way1382452674438
Fixes: 2d87061e70de ("arm64: dts: ti: Add Support for J721E SoC")
Cc: stable@vger.kernel.org # 5.10+
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
Testing: based on next-20220215
j721e-sk: https://gist.github.com/nmenon/db3f29f2f241f1b5294c7e4054c3fbf1
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 5 ++++-
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 599861259a30..db0669985e42 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -76,7 +76,10 @@ gic500: interrupt-controller@1800000 {
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01900000 0x00 0x100000>; /* GICR */
+ <0x00 0x01900000 0x00 0x100000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index 4a3872fce533..0e23886c9fd1 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -139,6 +139,7 @@ cbass_main: bus@100000 {
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/
<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
<0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
<0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
<0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
<0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
--
2.31.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 3/5] arm64: dts: ti: k3-j7200: Fix gic-v3 compatible regs
[not found] <20220215201008.15235-1-nm@ti.com>
2022-02-15 20:10 ` [PATCH 1/5] arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs Nishanth Menon
2022-02-15 20:10 ` [PATCH 2/5] arm64: dts: ti: k3-j721e: " Nishanth Menon
@ 2022-02-15 20:10 ` Nishanth Menon
2022-02-15 20:10 ` [PATCH 4/5] arm64: dts: ti: k3-am64: " Nishanth Menon
2022-02-15 20:10 ` [PATCH 5/5] arm64: dts: ti: k3-j721s2: " Nishanth Menon
4 siblings, 0 replies; 5+ messages in thread
From: Nishanth Menon @ 2022-02-15 20:10 UTC (permalink / raw)
To: Tero Kristo, Vignesh Raghavendra, Marc Zyngier
Cc: linux-kernel, devicetree, linux-arm-kernel, Krzysztof Kozlowski,
Rob Herring, Nishanth Menon, stable
Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A72 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.
Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.
[1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
[3] https://developer.arm.com/documentation/100095/0002/way1382452674438
Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")
Cc: stable@vger.kernel.org
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
Testing: based on next-20220215
j7200-evm: https://gist.github.com/nmenon/23a7844a794a0123af9b211eee2b7d0b
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 5 ++++-
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 05a627ad6cdc..16684a2f054d 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -54,7 +54,10 @@ gic500: interrupt-controller@1800000 {
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01900000 0x00 0x100000>; /* GICR */
+ <0x00 0x01900000 0x00 0x100000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
index 64fef4e67d76..b6da0454cc5b 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
@@ -129,6 +129,7 @@ cbass_main: bus@100000 {
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
--
2.31.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 4/5] arm64: dts: ti: k3-am64: Fix gic-v3 compatible regs
[not found] <20220215201008.15235-1-nm@ti.com>
` (2 preceding siblings ...)
2022-02-15 20:10 ` [PATCH 3/5] arm64: dts: ti: k3-j7200: " Nishanth Menon
@ 2022-02-15 20:10 ` Nishanth Menon
2022-02-15 20:10 ` [PATCH 5/5] arm64: dts: ti: k3-j721s2: " Nishanth Menon
4 siblings, 0 replies; 5+ messages in thread
From: Nishanth Menon @ 2022-02-15 20:10 UTC (permalink / raw)
To: Tero Kristo, Vignesh Raghavendra, Marc Zyngier
Cc: linux-kernel, devicetree, linux-arm-kernel, Krzysztof Kozlowski,
Rob Herring, Nishanth Menon, stable
Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A53 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.
Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.
[1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
[3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map
Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC")
Cc: stable@vger.kernel.org
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
Testing: based on next-20220215
AM64xx-sk: https://gist.github.com/nmenon/75d413e53005fabc4bde8a4efe227594
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 5 ++++-
arch/arm64/boot/dts/ti/k3-am64.dtsi | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 0c9f3bce8418..f64b368c6c37 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -59,7 +59,10 @@ gic500: interrupt-controller@1800000 {
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01840000 0x00 0xC0000>; /* GICR */
+ <0x00 0x01840000 0x00 0xC0000>, /* GICR */
+ <0x01 0x00000000 0x00 0x2000>, /* GICC */
+ <0x01 0x00010000 0x00 0x1000>, /* GICH */
+ <0x01 0x00020000 0x00 0x2000>; /* GICV */
/*
* vcpumntirq:
* virtual CPU interface maintenance interrupt
diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi
index 84bd07cd1824..e88349846871 100644
--- a/arch/arm64/boot/dts/ti/k3-am64.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi
@@ -89,6 +89,7 @@ cbass_main: bus@f4000 {
<0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
<0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
+ <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
<0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
--
2.31.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 5/5] arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regs
[not found] <20220215201008.15235-1-nm@ti.com>
` (3 preceding siblings ...)
2022-02-15 20:10 ` [PATCH 4/5] arm64: dts: ti: k3-am64: " Nishanth Menon
@ 2022-02-15 20:10 ` Nishanth Menon
4 siblings, 0 replies; 5+ messages in thread
From: Nishanth Menon @ 2022-02-15 20:10 UTC (permalink / raw)
To: Tero Kristo, Vignesh Raghavendra, Marc Zyngier
Cc: linux-kernel, devicetree, linux-arm-kernel, Krzysztof Kozlowski,
Rob Herring, Nishanth Menon, stable
Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A72 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.
Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.
[1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
[3] https://developer.arm.com/documentation/100095/0002/way1382452674438
Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC")
Cc: stable@vger.kernel.org
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
Testing: based on next-20220215
J721s2-evm Log: https://gist.github.com/nmenon/302b0bcfbb1b5b8743fa5c242eb7d15f
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 5 ++++-
arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index b04db1d3ab61..be7f39299894 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -34,7 +34,10 @@ gic500: interrupt-controller@1800000 {
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
- <0x00 0x01900000 0x00 0x100000>; /* GICR */
+ <0x00 0x01900000 0x00 0x100000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
index fe5234c40f6c..7b930a85a29d 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
@@ -119,6 +119,7 @@ cbass_main: bus@100000 {
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
<0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
--
2.31.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-02-16 2:41 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <20220215201008.15235-1-nm@ti.com>
2022-02-15 20:10 ` [PATCH 1/5] arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs Nishanth Menon
2022-02-15 20:10 ` [PATCH 2/5] arm64: dts: ti: k3-j721e: " Nishanth Menon
2022-02-15 20:10 ` [PATCH 3/5] arm64: dts: ti: k3-j7200: " Nishanth Menon
2022-02-15 20:10 ` [PATCH 4/5] arm64: dts: ti: k3-am64: " Nishanth Menon
2022-02-15 20:10 ` [PATCH 5/5] arm64: dts: ti: k3-j721s2: " Nishanth Menon
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).