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From: Tudor Ambarus <tudor.ambarus@linaro.org>
To: Takahiro.Kuwano@infineon.com, tkuw584924@gmail.com
Cc: linux-mtd@lists.infradead.org, pratyush@kernel.org,
	michael@walle.cc, miquel.raynal@bootlin.com, richard@nod.at,
	Bacem.Daassi@infineon.com,
	Tudor Ambarus <tudor.ambarus@linaro.org>,
	stable@vger.kernel.org
Subject: [PATCH 1/2] mtd: spi-nor: spansion: Consider reserved bits in CFR5 register
Date: Tue, 10 Jan 2023 18:47:02 +0200	[thread overview]
Message-ID: <20230110164703.83413-1-tudor.ambarus@linaro.org> (raw)
In-Reply-To: <493d9a10-aaf3-70f6-36c3-9a2cf39f0759@linaro.org>

CFR5[6] is reserved bit and must be always 1. Set it to comply with flash
requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_{EN, DS}
definition, stop using magic numbers and describe the missing bit fields
in CFR5 register. This is useful for both readability and future possible
addition of Octal STR mode support.

Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Semper flash")
Cc: stable@vger.kernel.org
Reported-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
 drivers/mtd/spi-nor/spansion.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index b621cdfd506f..07fe0f6fdfe3 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -21,8 +21,13 @@
 #define SPINOR_REG_CYPRESS_CFR3V		0x00800004
 #define SPINOR_REG_CYPRESS_CFR3V_PGSZ		BIT(4) /* Page size. */
 #define SPINOR_REG_CYPRESS_CFR5V		0x00800006
-#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN	0x3
-#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS	0
+#define SPINOR_REG_CYPRESS_CFR5_BIT6		BIT(6)
+#define SPINOR_REG_CYPRESS_CFR5_DDR		BIT(1)
+#define SPINOR_REG_CYPRESS_CFR5_OPI		BIT(0)
+#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN				\
+	(SPINOR_REG_CYPRESS_CFR5_BIT6 |	SPINOR_REG_CYPRESS_CFR5_DDR |	\
+	 SPINOR_REG_CYPRESS_CFR5_OPI)
+#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS	SPINOR_REG_CYPRESS_CFR5_BIT6
 #define SPINOR_OP_CYPRESS_RD_FAST		0xee
 
 /* Cypress SPI NOR flash operations. */
-- 
2.34.1


  parent reply	other threads:[~2023-01-10 16:49 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-06  3:06 [PATCH] mtd: spi-nor: spansion: Keep CFR5V[6] as 1 in Octal DTR enable/disable tkuw584924
2023-01-06  9:47 ` Tudor Ambarus
2023-01-06  9:55   ` Tudor Ambarus
2023-01-10  4:39   ` Takahiro Kuwano
2023-01-10 16:47   ` Tudor Ambarus [this message]
2023-01-11  6:28     ` [PATCH 1/2] mtd: spi-nor: spansion: Consider reserved bits in CFR5 register Dhruva Gole
2023-01-18  7:34     ` Takahiro Kuwano
2023-01-23 14:37     ` Pratyush Yadav
2023-01-23 16:31       ` Dhruva Gole
2023-01-24 10:43         ` Pratyush Yadav
2023-01-24 11:12           ` Dhruva Gole
2023-01-24 12:03             ` Pratyush Yadav
2023-02-01  7:14         ` Takahiro Kuwano
2023-01-31  9:00     ` Tudor Ambarus

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