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[2001:1c00:c0c:fe00:7e79:4dac:39d0:9c14]) by smtp.gmail.com with ESMTPSA id d204sm2480650wmd.30.2020.01.29.06.27.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Jan 2020 06:27:34 -0800 (PST) Subject: Re: [v3] x86/tsc: Unset TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Bay Trail SoC To: Andy Shevchenko Cc: Thomas Gleixner , vipul kumar , Daniel Lezcano , linux-kernel@vger.kernel.org, Stable , Srikanth Krishnakar , Cedric Hombourger , x86@kernel.org, Len Brown , Vipul Kumar References: <20200123144108.GU32742@smile.fi.intel.com> <87iml11ccf.fsf@nanos.tec.linutronix.de> <87ftg5131x.fsf@nanos.tec.linutronix.de> <30d49be8-67ad-6f32-37a8-0cdd26f0852e@redhat.com> <87sgjz434v.fsf@nanos.tec.linutronix.de> <20200129130350.GD32742@smile.fi.intel.com> <0d361322-87aa-af48-492c-e8c4983bb35b@redhat.com> <20200129141444.GE32742@smile.fi.intel.com> From: Hans de Goede Message-ID: <91cdda7a-4194-ebe7-225d-854447b0436e@redhat.com> Date: Wed, 29 Jan 2020 15:27:33 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200129141444.GE32742@smile.fi.intel.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Hi, On 29-01-2020 15:14, Andy Shevchenko wrote: > On Wed, Jan 29, 2020 at 02:21:40PM +0100, Hans de Goede wrote: >> On 29-01-2020 14:03, Andy Shevchenko wrote: >>> On Tue, Jan 28, 2020 at 11:39:28PM +0100, Thomas Gleixner wrote: >>>> Hans de Goede writes: > > ... > >>>> Typical crystal frequencies are 19.2, 24 and 25Mhz. >>> >>> Hans, I think Cherrytrail may be affected by this as the others. >>> CHT AFAIK uses 19.2MHz xtal. >> >> Are you sure? > > I'm not. I may mixed this with PMC clock. Ok, then I'm going to go with 25MHz for now. >> The first 5 entries of the CHT MSR_FSB_FREQ documentation exactly >> match those of the BYT documentation (which has only 5 entries), >> which suggests to me that CHT is also using a 25 MHz crystal. >> >> I can also make the other CHT only frequencies when assuming a 25 >> MHz crystal, here is a bit from the patch I'm working on for this: >> >> /* >> * Cherry Trail SDM MSR_FSB_FREQ frequencies to PLL settings map: >> * 0000: 25 * 20 / 6 = 83.3333 MHz >> * 0001: 25 * 4 / 1 = 100.0000 MHz >> * 0010: 25 * 16 / 3 = 133.3333 MHz >> * 0011: 25 * 28 / 6 = 116.6667 MHz >> * 0100: 25 * 16 / 5 = 80.0000 MHz >> * 0101: 25 * 56 / 15 = 93.3333 MHz >> * 0110: 25 * 18 / 5 = 90.0000 MHz >> * 0111: 25 * 32 / 9 = 88.8889 MHz >> * 1000: 25 * 7 / 2 = 87.5000 MHz >> */ >> >> The only one which is possibly suspicious here is this line: >> >> * 0111: 25 * 32 / 9 = 88.8889 MHz >> >> The SDM says 88.9 MHz for this one. > > Anyway it seems need to be fixed as well. > > Btw, why we are mentioning 20 / 6 and 28 / 6 when arithmetically > it's the same as 10 / 3 and 14 / 3? I copied the BYT values from Thomas' email and I guess he did not get around to simplifying them, I'll use the simplified versions for my patch. Regards, Hans