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From: Anup Patel <anup@brainfault.org>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Anup Patel <Anup.Patel@wdc.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>,
	Marc Zyngier <maz@kernel.org>, Atish Patra <Atish.Patra@wdc.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	"linux-kernel@vger.kernel.org List"
	<linux-kernel@vger.kernel.org>,
	stable@vger.kernel.org
Subject: Re: [PATCH v2 2/3] irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is present
Date: Fri, 22 May 2020 12:16:24 +0530	[thread overview]
Message-ID: <CAAhSdy1NmtRW+LGJ013xAe9AwroUPcujqC2yLcNY+5ZtvGpCUQ@mail.gmail.com> (raw)
In-Reply-To: <mhng-06a48d36-b37c-481f-97aa-8fc0b1f9795e@palmerdabbelt-glaptop1>

On Fri, May 22, 2020 at 3:36 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Mon, 18 May 2020 02:14:40 PDT (-0700), Anup Patel wrote:
> > For multiple PLIC instances, the plic_init() is called once for each
> > PLIC instance. Due to this we have two issues:
> > 1. cpuhp_setup_state() is called multiple times
> > 2. plic_starting_cpu() can crash for boot CPU if cpuhp_setup_state()
> >    is called before boot CPU PLIC handler is available.
> >
> > This patch fixes both above issues.
> >
> > Fixes: f1ad1133b18f ("irqchip/sifive-plic: Add support for multiple PLICs")
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> >  drivers/irqchip/irq-sifive-plic.c | 14 ++++++++++++--
> >  1 file changed, 12 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> > index 9f7f8ce88c00..6c54abf5cc5e 100644
> > --- a/drivers/irqchip/irq-sifive-plic.c
> > +++ b/drivers/irqchip/irq-sifive-plic.c
> > @@ -76,6 +76,7 @@ struct plic_handler {
> >       void __iomem            *enable_base;
> >       struct plic_priv        *priv;
> >  };
> > +static bool plic_cpuhp_setup_done;
> >  static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
> >
> >  static inline void plic_toggle(struct plic_handler *handler,
> > @@ -285,6 +286,7 @@ static int __init plic_init(struct device_node *node,
> >       int error = 0, nr_contexts, nr_handlers = 0, i;
> >       u32 nr_irqs;
> >       struct plic_priv *priv;
> > +     struct plic_handler *handler;
> >
> >       priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> >       if (!priv)
> > @@ -313,7 +315,6 @@ static int __init plic_init(struct device_node *node,
> >
> >       for (i = 0; i < nr_contexts; i++) {
> >               struct of_phandle_args parent;
> > -             struct plic_handler *handler;
> >               irq_hw_number_t hwirq;
> >               int cpu, hartid;
> >
> > @@ -367,9 +368,18 @@ static int __init plic_init(struct device_node *node,
> >               nr_handlers++;
> >       }
> >
> > -     cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
> > +     /*
> > +      * We can have multiple PLIC instances so setup cpuhp state only
> > +      * when context handler for current/boot CPU is present.
> > +      */
> > +     handler = this_cpu_ptr(&plic_handlers);
> > +     if (handler->present && !plic_cpuhp_setup_done) {
> > +             cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
> >                                 "irqchip/sifive/plic:starting",
> >                                 plic_starting_cpu, plic_dying_cpu);
> > +             plic_cpuhp_setup_done = true;
>
> So presumably something else is preventing multiple plic_init() calls from
> executing at the same time?  Assuming that's the case

AFAIK, interrupt controller and timer probing happens sequentially on
boot CPU before all secondary CPUs are brought-up.

>
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
>
> > +     }
> > +
> >       pr_info("mapped %d interrupts with %d handlers for %d contexts.\n",
> >               nr_irqs, nr_handlers, nr_contexts);
> >       set_handle_irq(plic_handle_irq);

Thanks,
Anup

  reply	other threads:[~2020-05-22  6:46 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20200518091441.94843-1-anup.patel@wdc.com>
2020-05-18  9:14 ` [PATCH v2 1/3] irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map() Anup Patel
2020-05-21 22:06   ` Palmer Dabbelt
2020-05-22  6:44     ` Anup Patel
2020-05-30  7:46   ` [tip: irq/core] " tip-bot2 for Anup Patel
2020-05-18  9:14 ` [PATCH v2 2/3] irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is present Anup Patel
2020-05-21 22:06   ` Palmer Dabbelt
2020-05-22  6:46     ` Anup Patel [this message]
2020-05-30  7:46   ` [tip: irq/core] " tip-bot2 for Anup Patel

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