Re: [PATCH] arm64: errata: Add Cortex-A510 to the repeat tlbi list

[Lucas Wei <lucaswei@google.com>]

Hi Greg,

I send this mail through git send-email from kernel
guide(https://www.kernel.org/doc/html/v4.10/process/email-clients.html).
Would you help to confirm this could be applied on linux-5.15.y? Great thanks.

 - Lucas


On Tue, Aug 30, 2022 at 11:08 PM Lucas Wei <lucaswei@google.com> wrote:
>
> From: James Morse <james.morse@arm.com>
>
> Cortex-A510 is affected by an erratum where in rare circumstances the
> CPUs may not handle a race between a break-before-make sequence on one
> CPU, and another CPU accessing the same page. This could allow a store
> to a page that has been unmapped.
>
> Work around this by adding the affected CPUs to the list that needs
> TLB sequences to be done twice.
>
> Signed-off-by: James Morse <james.morse@arm.com>
> Link: https://lore.kernel.org/r/20220704155732.21216-1-james.morse@arm.com
> Signed-off-by: Will Deacon <will@kernel.org>
> ---
>  Documentation/arm64/silicon-errata.rst |  2 ++
>  arch/arm64/Kconfig                     | 17 +++++++++++++++++
>  arch/arm64/kernel/cpu_errata.c         |  8 +++++++-
>  3 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
> index 0b4235b1f8c4..33b04db8408f 100644
> --- a/Documentation/arm64/silicon-errata.rst
> +++ b/Documentation/arm64/silicon-errata.rst
> @@ -106,6 +106,8 @@ stable kernels.
>  +----------------+-----------------+-----------------+-----------------------------+
>  | ARM            | Cortex-A510     | #2077057        | ARM64_ERRATUM_2077057       |
>  +----------------+-----------------+-----------------+-----------------------------+
> +| ARM            | Cortex-A510     | #2441009        | ARM64_ERRATUM_2441009       |
> ++----------------+-----------------+-----------------+-----------------------------+
>  | ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       |
>  +----------------+-----------------+-----------------+-----------------------------+
>  | ARM            | Cortex-A710     | #2054223        | ARM64_ERRATUM_2054223       |
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index a5d1b561ed53..001eaba5a6b4 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -838,6 +838,23 @@ config ARM64_ERRATUM_2224489
>
>           If unsure, say Y.
>
> +config ARM64_ERRATUM_2441009
> +       bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
> +       default y
> +       select ARM64_WORKAROUND_REPEAT_TLBI
> +       help
> +         This option adds a workaround for ARM Cortex-A510 erratum #2441009.
> +
> +         Under very rare circumstances, affected Cortex-A510 CPUs
> +         may not handle a race between a break-before-make sequence on one
> +         CPU, and another CPU accessing the same page. This could allow a
> +         store to a page that has been unmapped.
> +
> +         Work around this by adding the affected CPUs to the list that needs
> +         TLB sequences to be done twice.
> +
> +         If unsure, say Y.
> +
>  config ARM64_ERRATUM_2064142
>         bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
>         depends on CORESIGHT_TRBE
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index 6b92989f4cc2..aa9609e6ca67 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -211,6 +211,12 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
>                 /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */
>                 ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
>         },
> +#endif
> +#ifdef CONFIG_ARM64_ERRATUM_2441009
> +       {
> +               /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */
> +               ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
> +       },
>  #endif
>         {},
>  };
> @@ -488,7 +494,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
>  #endif
>  #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
>         {
> -               .desc = "Qualcomm erratum 1009, or ARM erratum 1286807",
> +               .desc = "Qualcomm erratum 1009, or ARM erratum 1286807, 2441009",
>                 .capability = ARM64_WORKAROUND_REPEAT_TLBI,
>                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
>                 .matches = cpucap_multi_entry_cap_matches,
> --
>
>


-- 

Lucas Wei
Embedded Software Engineer
lucaswei@google.com
0287260408