From: Vinod Koul <vkoul@kernel.org>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: stable@vger.kernel.org, patches@lists.linux.dev,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Sasha Levin <sashal@kernel.org>
Subject: Re: [PATCH 5.15 557/731] phy: qcom-qmp: create copies of QMP PHY driver
Date: Wed, 28 Dec 2022 22:19:05 +0530 [thread overview]
Message-ID: <Y6xzgWqijrtJl6oJ@matsya> (raw)
In-Reply-To: <20221228144312.695000223@linuxfoundation.org>
On 28-12-22, 15:41, Greg Kroah-Hartman wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> [ Upstream commit 94a407cc17a445ddb3f7315cee0b0916d35d177c ]
>
> In order to split and cleanup the single monstrous QMP PHY driver,
> create blind copies of the current file. They will be used for:
> - PCIe (and a separate msm8996 PCIe PHY driver)
> - UFS
> - USB
> - Combo DP + USB
Greg,
Please drop this. This is a full driver rework and code reorg thus not
suitable for stable
Thanks
>
> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Link: https://lore.kernel.org/r/20220607213203.2819885-2-dmitry.baryshkov@linaro.org
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> Stable-dep-of: c7b98de745cf ("phy: qcom-qmp-combo: fix runtime suspend")
> Signed-off-by: Sasha Levin <sashal@kernel.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 6350 +++++++++++++++++
> .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 6350 +++++++++++++++++
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 6350 +++++++++++++++++
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 6350 +++++++++++++++++
> drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 6350 +++++++++++++++++
> 5 files changed, 31750 insertions(+)
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-usb.c
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> new file mode 100644
> index 000000000000..c7309e981bfb
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> @@ -0,0 +1,6350 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2017, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +
> +#include <dt-bindings/phy/phy.h>
> +
> +#include "phy-qcom-qmp.h"
> +
> +/* QPHY_SW_RESET bit */
> +#define SW_RESET BIT(0)
> +/* QPHY_POWER_DOWN_CONTROL */
> +#define SW_PWRDN BIT(0)
> +#define REFCLK_DRV_DSBL BIT(1)
> +/* QPHY_START_CONTROL bits */
> +#define SERDES_START BIT(0)
> +#define PCS_START BIT(1)
> +#define PLL_READY_GATE_EN BIT(3)
> +/* QPHY_PCS_STATUS bit */
> +#define PHYSTATUS BIT(6)
> +#define PHYSTATUS_4_20 BIT(7)
> +/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
> +#define PCS_READY BIT(0)
> +
> +/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
> +/* DP PHY soft reset */
> +#define SW_DPPHY_RESET BIT(0)
> +/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
> +#define SW_DPPHY_RESET_MUX BIT(1)
> +/* USB3 PHY soft reset */
> +#define SW_USB3PHY_RESET BIT(2)
> +/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
> +#define SW_USB3PHY_RESET_MUX BIT(3)
> +
> +/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
> +#define USB3_MODE BIT(0) /* enables USB3 mode */
> +#define DP_MODE BIT(1) /* enables DP mode */
> +
> +/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
> +#define ARCVR_DTCT_EN BIT(0)
> +#define ALFPS_DTCT_EN BIT(1)
> +#define ARCVR_DTCT_EVENT_SEL BIT(4)
> +
> +/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
> +#define IRQ_CLEAR BIT(0)
> +
> +/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
> +#define RCVR_DETECT BIT(0)
> +
> +/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
> +#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
> +
> +#define PHY_INIT_COMPLETE_TIMEOUT 10000
> +#define POWER_DOWN_DELAY_US_MIN 10
> +#define POWER_DOWN_DELAY_US_MAX 11
> +
> +#define MAX_PROP_NAME 32
> +
> +/* Define the assumed distance between lanes for underspecified device trees. */
> +#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
> +
> +struct qmp_phy_init_tbl {
> + unsigned int offset;
> + unsigned int val;
> + /*
> + * register part of layout ?
> + * if yes, then offset gives index in the reg-layout
> + */
> + bool in_layout;
> + /*
> + * mask of lanes for which this register is written
> + * for cases when second lane needs different values
> + */
> + u8 lane_mask;
> +};
> +
> +#define QMP_PHY_INIT_CFG(o, v) \
> + { \
> + .offset = o, \
> + .val = v, \
> + .lane_mask = 0xff, \
> + }
> +
> +#define QMP_PHY_INIT_CFG_L(o, v) \
> + { \
> + .offset = o, \
> + .val = v, \
> + .in_layout = true, \
> + .lane_mask = 0xff, \
> + }
> +
> +#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
> + { \
> + .offset = o, \
> + .val = v, \
> + .lane_mask = l, \
> + }
> +
> +/* set of registers with offsets different per-PHY */
> +enum qphy_reg_layout {
> + /* Common block control registers */
> + QPHY_COM_SW_RESET,
> + QPHY_COM_POWER_DOWN_CONTROL,
> + QPHY_COM_START_CONTROL,
> + QPHY_COM_PCS_READY_STATUS,
> + /* PCS registers */
> + QPHY_PLL_LOCK_CHK_DLY_TIME,
> + QPHY_FLL_CNTRL1,
> + QPHY_FLL_CNTRL2,
> + QPHY_FLL_CNT_VAL_L,
> + QPHY_FLL_CNT_VAL_H_TOL,
> + QPHY_FLL_MAN_CODE,
> + QPHY_SW_RESET,
> + QPHY_START_CTRL,
> + QPHY_PCS_READY_STATUS,
> + QPHY_PCS_STATUS,
> + QPHY_PCS_AUTONOMOUS_MODE_CTRL,
> + QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
> + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
> + QPHY_PCS_POWER_DOWN_CONTROL,
> + /* PCS_MISC registers */
> + QPHY_PCS_MISC_TYPEC_CTRL,
> + /* Keep last to ensure regs_layout arrays are properly initialized */
> + QPHY_LAYOUT_SIZE
> +};
> +
> +static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = 0x00,
> + [QPHY_PCS_READY_STATUS] = 0x168,
> +};
> +
> +static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> +};
> +
> +static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_COM_SW_RESET] = 0x400,
> + [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
> + [QPHY_COM_START_CONTROL] = 0x408,
> + [QPHY_COM_PCS_READY_STATUS] = 0x448,
> + [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
> + [QPHY_FLL_CNTRL1] = 0xc4,
> + [QPHY_FLL_CNTRL2] = 0xc8,
> + [QPHY_FLL_CNT_VAL_L] = 0xcc,
> + [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
> + [QPHY_FLL_MAN_CODE] = 0xd4,
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x174,
> +};
> +
> +static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_FLL_CNTRL1] = 0xc0,
> + [QPHY_FLL_CNTRL2] = 0xc4,
> + [QPHY_FLL_CNT_VAL_L] = 0xc8,
> + [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
> + [QPHY_FLL_MAN_CODE] = 0xd0,
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x17c,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
> +};
> +
> +static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x174,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
> +};
> +
> +static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x174,
> +};
> +
> +static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x2ac,
> +};
> +
> +static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
> +};
> +
> +static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
> +};
> +
> +static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
> +};
> +
> +static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
> + [QPHY_PCS_STATUS] = 0x174,
> + [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
> +};
> +
> +static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = 0x00,
> + [QPHY_PCS_READY_STATUS] = 0x160,
> +};
> +
> +static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = 0x00,
> + [QPHY_PCS_READY_STATUS] = 0x168,
> +};
> +
> +static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> +};
> +
> +static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
> + [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
> + [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + /* PLL and Loop filter settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + /* SSC settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
> + QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
> +
> + QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
> +
> + QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
> + QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
> + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
> + /* PLL and Loop filter settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + /* SSC settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
> + /* FLL settings */
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
> +
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
> + QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
> + QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
> + QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
> + QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
> + QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
> + QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
> + QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> + QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
> + QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
> + QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
> + QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
> + QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
> + QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
> + QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
> + QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
> + QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
> + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
> + QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
> + QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
> + /* FLL settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> +
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
> + /* FLL settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> +
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
> + QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
> + QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
> + QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
> +
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> +
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
> +};
> +
> +/* Register names should be validated, they might be different for this PHY */
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
> +};
> +
> +struct qmp_phy;
> +
> +/* struct qmp_phy_cfg - per-PHY initialization config */
> +struct qmp_phy_cfg {
> + /* phy-type - PCIE/UFS/USB */
> + unsigned int type;
> + /* number of lanes provided by phy */
> + int nlanes;
> +
> + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
> + const struct qmp_phy_init_tbl *serdes_tbl;
> + int serdes_tbl_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_sec;
> + int serdes_tbl_num_sec;
> + const struct qmp_phy_init_tbl *tx_tbl;
> + int tx_tbl_num;
> + const struct qmp_phy_init_tbl *tx_tbl_sec;
> + int tx_tbl_num_sec;
> + const struct qmp_phy_init_tbl *rx_tbl;
> + int rx_tbl_num;
> + const struct qmp_phy_init_tbl *rx_tbl_sec;
> + int rx_tbl_num_sec;
> + const struct qmp_phy_init_tbl *pcs_tbl;
> + int pcs_tbl_num;
> + const struct qmp_phy_init_tbl *pcs_tbl_sec;
> + int pcs_tbl_num_sec;
> + const struct qmp_phy_init_tbl *pcs_misc_tbl;
> + int pcs_misc_tbl_num;
> + const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
> + int pcs_misc_tbl_num_sec;
> +
> + /* Init sequence for DP PHY block link rates */
> + const struct qmp_phy_init_tbl *serdes_tbl_rbr;
> + int serdes_tbl_rbr_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_hbr;
> + int serdes_tbl_hbr_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
> + int serdes_tbl_hbr2_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
> + int serdes_tbl_hbr3_num;
> +
> + /* DP PHY callbacks */
> + int (*configure_dp_phy)(struct qmp_phy *qphy);
> + void (*configure_dp_tx)(struct qmp_phy *qphy);
> + int (*calibrate_dp_phy)(struct qmp_phy *qphy);
> + void (*dp_aux_init)(struct qmp_phy *qphy);
> +
> + /* clock ids to be requested */
> + const char * const *clk_list;
> + int num_clks;
> + /* resets to be requested */
> + const char * const *reset_list;
> + int num_resets;
> + /* regulators to be requested */
> + const char * const *vreg_list;
> + int num_vregs;
> +
> + /* array of registers with different offsets */
> + const unsigned int *regs;
> +
> + unsigned int start_ctrl;
> + unsigned int pwrdn_ctrl;
> + unsigned int mask_com_pcs_ready;
> + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
> + unsigned int phy_status;
> +
> + /* true, if PHY has a separate PHY_COM control block */
> + bool has_phy_com_ctrl;
> + /* true, if PHY has a reset for individual lanes */
> + bool has_lane_rst;
> + /* true, if PHY needs delay after POWER_DOWN */
> + bool has_pwrdn_delay;
> + /* power_down delay in usec */
> + int pwrdn_delay_min;
> + int pwrdn_delay_max;
> +
> + /* true, if PHY has a separate DP_COM control block */
> + bool has_phy_dp_com_ctrl;
> + /* true, if PHY has secondary tx/rx lanes to be configured */
> + bool is_dual_lane_phy;
> +
> + /* true, if PCS block has no separate SW_RESET register */
> + bool no_pcs_sw_reset;
> +};
> +
> +struct qmp_phy_combo_cfg {
> + const struct qmp_phy_cfg *usb_cfg;
> + const struct qmp_phy_cfg *dp_cfg;
> +};
> +
> +/**
> + * struct qmp_phy - per-lane phy descriptor
> + *
> + * @phy: generic phy
> + * @cfg: phy specific configuration
> + * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
> + * @tx: iomapped memory space for lane's tx
> + * @rx: iomapped memory space for lane's rx
> + * @pcs: iomapped memory space for lane's pcs
> + * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
> + * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
> + * @pcs_misc: iomapped memory space for lane's pcs_misc
> + * @pipe_clk: pipe clock
> + * @index: lane index
> + * @qmp: QMP phy to which this lane belongs
> + * @lane_rst: lane's reset controller
> + * @mode: current PHY mode
> + * @dp_aux_cfg: Display port aux config
> + * @dp_opts: Display port optional config
> + * @dp_clks: Display port clocks
> + */
> +struct qmp_phy {
> + struct phy *phy;
> + const struct qmp_phy_cfg *cfg;
> + void __iomem *serdes;
> + void __iomem *tx;
> + void __iomem *rx;
> + void __iomem *pcs;
> + void __iomem *tx2;
> + void __iomem *rx2;
> + void __iomem *pcs_misc;
> + struct clk *pipe_clk;
> + unsigned int index;
> + struct qcom_qmp *qmp;
> + struct reset_control *lane_rst;
> + enum phy_mode mode;
> + unsigned int dp_aux_cfg;
> + struct phy_configure_opts_dp dp_opts;
> + struct qmp_phy_dp_clks *dp_clks;
> +};
> +
> +struct qmp_phy_dp_clks {
> + struct qmp_phy *qphy;
> + struct clk_hw dp_link_hw;
> + struct clk_hw dp_pixel_hw;
> +};
> +
> +/**
> + * struct qcom_qmp - structure holding QMP phy block attributes
> + *
> + * @dev: device
> + * @dp_com: iomapped memory space for phy's dp_com control block
> + *
> + * @clks: array of clocks required by phy
> + * @resets: array of resets required by phy
> + * @vregs: regulator supplies bulk data
> + *
> + * @phys: array of per-lane phy descriptors
> + * @phy_mutex: mutex lock for PHY common block initialization
> + * @init_count: phy common block initialization count
> + * @ufs_reset: optional UFS PHY reset handle
> + */
> +struct qcom_qmp {
> + struct device *dev;
> + void __iomem *dp_com;
> +
> + struct clk_bulk_data *clks;
> + struct reset_control **resets;
> + struct regulator_bulk_data *vregs;
> +
> + struct qmp_phy **phys;
> +
> + struct mutex phy_mutex;
> + int init_count;
> +
> + struct reset_control *ufs_reset;
> +};
> +
> +static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
> +static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
> +static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
> +static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
> +
> +static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
> +static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
> +static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
> +static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
> +
> +static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
> +{
> + u32 reg;
> +
> + reg = readl(base + offset);
> + reg |= val;
> + writel(reg, base + offset);
> +
> + /* ensure that above write is through */
> + readl(base + offset);
> +}
> +
> +static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
> +{
> + u32 reg;
> +
> + reg = readl(base + offset);
> + reg &= ~val;
> + writel(reg, base + offset);
> +
> + /* ensure that above write is through */
> + readl(base + offset);
> +}
> +
> +/* list of clocks required by phy */
> +static const char * const msm8996_phy_clk_l[] = {
> + "aux", "cfg_ahb", "ref",
> +};
> +
> +static const char * const msm8996_ufs_phy_clk_l[] = {
> + "ref",
> +};
> +
> +static const char * const qmp_v3_phy_clk_l[] = {
> + "aux", "cfg_ahb", "ref", "com_aux",
> +};
> +
> +static const char * const sdm845_pciephy_clk_l[] = {
> + "aux", "cfg_ahb", "ref", "refgen",
> +};
> +
> +static const char * const qmp_v4_phy_clk_l[] = {
> + "aux", "ref_clk_src", "ref", "com_aux",
> +};
> +
> +/* the primary usb3 phy on sm8250 doesn't have a ref clock */
> +static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
> + "aux", "ref_clk_src", "com_aux"
> +};
> +
> +static const char * const sm8450_ufs_phy_clk_l[] = {
> + "qref", "ref", "ref_aux",
> +};
> +
> +static const char * const sdm845_ufs_phy_clk_l[] = {
> + "ref", "ref_aux",
> +};
> +
> +/* usb3 phy on sdx55 doesn't have com_aux clock */
> +static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
> + "aux", "cfg_ahb", "ref"
> +};
> +
> +static const char * const qcm2290_usb3phy_clk_l[] = {
> + "cfg_ahb", "ref", "com_aux",
> +};
> +
> +/* list of resets */
> +static const char * const msm8996_pciephy_reset_l[] = {
> + "phy", "common", "cfg",
> +};
> +
> +static const char * const msm8996_usb3phy_reset_l[] = {
> + "phy", "common",
> +};
> +
> +static const char * const sc7180_usb3phy_reset_l[] = {
> + "phy",
> +};
> +
> +static const char * const qcm2290_usb3phy_reset_l[] = {
> + "phy_phy", "phy",
> +};
> +
> +static const char * const sdm845_pciephy_reset_l[] = {
> + "phy",
> +};
> +
> +/* list of regulators */
> +static const char * const qmp_phy_vreg_l[] = {
> + "vdda-phy", "vdda-pll",
> +};
> +
> +static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = ipq8074_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
> + .tx_tbl = msm8996_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
> + .rx_tbl = ipq8074_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
> + .pcs_tbl = ipq8074_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +};
> +
> +static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 3,
> +
> + .serdes_tbl = msm8996_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
> + .tx_tbl = msm8996_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
> + .rx_tbl = msm8996_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
> + .pcs_tbl = msm8996_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = pciephy_regs_layout,
> +
> + .start_ctrl = PCS_START | PLL_READY_GATE_EN,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .mask_com_pcs_ready = PCS_READY,
> + .phy_status = PHYSTATUS,
> +
> + .has_phy_com_ctrl = true,
> + .has_lane_rst = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg msm8996_ufs_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8996_ufs_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
> + .tx_tbl = msm8996_ufs_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
> + .rx_tbl = msm8996_ufs_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
> +
> + .clk_list = msm8996_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
> +
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> +
> + .regs = msm8996_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .no_pcs_sw_reset = true,
> +};
> +
> +static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8996_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
> + .tx_tbl = msm8996_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
> + .rx_tbl = msm8996_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
> + .pcs_tbl = msm8996_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +};
> +
> +static const char * const ipq8074_pciephy_clk_l[] = {
> + "aux", "cfg_ahb",
> +};
> +/* list of resets */
> +static const char * const ipq8074_pciephy_reset_l[] = {
> + "phy", "common",
> +};
> +
> +static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = ipq8074_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
> + .tx_tbl = ipq8074_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
> + .rx_tbl = ipq8074_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
> + .pcs_tbl = ipq8074_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
> + .clk_list = ipq8074_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
> + .reset_list = ipq8074_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
> + .vreg_list = NULL,
> + .num_vregs = 0,
> + .regs = pciephy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_phy_com_ctrl = false,
> + .has_lane_rst = false,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = ipq6018_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
> + .tx_tbl = ipq6018_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
> + .rx_tbl = ipq6018_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
> + .pcs_tbl = ipq6018_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
> + .clk_list = ipq8074_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
> + .reset_list = ipq8074_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
> + .vreg_list = NULL,
> + .num_vregs = 0,
> + .regs = ipq_pciephy_gen3_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> +
> + .has_phy_com_ctrl = false,
> + .has_lane_rst = false,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
> + .tx_tbl = sdm845_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
> + .rx_tbl = sdm845_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
> + .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
> + .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sdm845_qmp_pciephy_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
> + .tx_tbl = sdm845_qhp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
> + .rx_tbl = sdm845_qhp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
> + .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sdm845_qhp_pciephy_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
> + .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
> + .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
> + .tx_tbl = sm8250_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
> + .rx_tbl = sm8250_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
> + .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
> + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
> + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
> + .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
> + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
> + .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
> + .tx_tbl = sm8250_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
> + .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
> + .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
> + .rx_tbl = sm8250_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
> + .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
> + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
> + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
> + .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
> + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
> + .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
> + .tx_tbl = qmp_v3_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
> + .rx_tbl = qmp_v3_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
> + .pcs_tbl = qmp_v3_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
> + .tx_tbl = qmp_v3_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
> + .rx_tbl = qmp_v3_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
> + .pcs_tbl = qmp_v3_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = sc7180_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
> + .type = PHY_TYPE_DP,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_dp_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
> + .tx_tbl = qmp_v3_dp_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
> +
> + .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
> + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
> + .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
> + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
> + .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
> + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
> + .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
> + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
> +
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = sc7180_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +
> + .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
> + .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
> + .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
> + .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
> +};
> +
> +static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
> + .usb_cfg = &sc7180_usb3phy_cfg,
> + .dp_cfg = &sc7180_dpphy_cfg,
> +};
> +
> +static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
> + .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
> + .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
> + .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sdm845_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
> + .tx_tbl = sdm845_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
> + .rx_tbl = sdm845_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
> + .pcs_tbl = sdm845_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sdm845_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> + .no_pcs_sw_reset = true,
> +};
> +
> +static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm6115_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
> + .tx_tbl = sm6115_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
> + .rx_tbl = sm6115_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
> + .pcs_tbl = sm6115_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm6115_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> +
> + .is_dual_lane_phy = false,
> + .no_pcs_sw_reset = true,
> +};
> +
> +static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8998_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
> + .tx_tbl = msm8998_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
> + .rx_tbl = msm8998_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
> + .pcs_tbl = msm8998_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = ipq8074_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = pciephy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +};
> +
> +static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8998_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
> + .tx_tbl = msm8998_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
> + .rx_tbl = msm8998_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
> + .pcs_tbl = msm8998_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8150_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
> + .tx_tbl = sm8150_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
> + .rx_tbl = sm8150_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
> + .pcs_tbl = sm8150_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8150_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
> + .tx_tbl = sm8150_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
> + .rx_tbl = sm8150_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
> + .pcs_tbl = sm8150_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
> + .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
> + .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
> + .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
> + .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
> + .type = PHY_TYPE_DP,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v4_dp_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
> + .tx_tbl = qmp_v4_dp_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
> +
> + .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
> + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
> + .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
> + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
> + .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
> + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
> + .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
> + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
> +
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = sc7180_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +
> + .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
> + .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
> + .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
> + .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
> +};
> +
> +static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
> + .usb_cfg = &sm8150_usb3phy_cfg,
> + .dp_cfg = &sc8180x_dpphy_cfg,
> +};
> +
> +static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
> + .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
> + .tx_tbl = sm8250_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
> + .rx_tbl = sm8250_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
> + .pcs_tbl = sm8250_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
> + .clk_list = qmp_v4_sm8250_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
> + .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
> + .type = PHY_TYPE_DP,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v4_dp_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
> + .tx_tbl = qmp_v4_dp_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
> +
> + .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
> + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
> + .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
> + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
> + .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
> + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
> + .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
> + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
> +
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +
> + .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
> + .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
> + .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
> + .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
> +};
> +
> +static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
> + .usb_cfg = &sm8250_usb3phy_cfg,
> + .dp_cfg = &sm8250_dpphy_cfg,
> +};
> +
> +static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
> + .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_sdx55_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 2,
> +
> + .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
> + .tx_tbl = sdx55_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
> + .rx_tbl = sdx55_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
> + .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
> + .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS_4_20,
> +
> + .is_dual_lane_phy = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
> + .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_sdx55_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8350_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8350_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
> + .tx_tbl = sm8350_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
> + .rx_tbl = sm8350_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
> + .pcs_tbl = sm8350_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8150_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
> + .tx_tbl = sm8350_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
> + .rx_tbl = sm8350_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
> + .pcs_tbl = sm8350_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
> + .clk_list = qmp_v4_sm8250_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
> + .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8350_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8350_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
> + .tx_tbl = sm8350_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
> + .rx_tbl = sm8350_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
> + .pcs_tbl = sm8350_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
> + .clk_list = sm8450_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8150_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
> + .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
> + .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
> + .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
> + .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
> + .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
> + .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS_4_20,
> +
> + .is_dual_lane_phy = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qcm2290_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
> + .tx_tbl = qcm2290_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
> + .rx_tbl = qcm2290_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
> + .pcs_tbl = qcm2290_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
> + .clk_list = qcm2290_usb3phy_clk_l,
> + .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
> + .reset_list = qcm2290_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qcm2290_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static void qcom_qmp_phy_configure_lane(void __iomem *base,
> + const unsigned int *regs,
> + const struct qmp_phy_init_tbl tbl[],
> + int num,
> + u8 lane_mask)
> +{
> + int i;
> + const struct qmp_phy_init_tbl *t = tbl;
> +
> + if (!t)
> + return;
> +
> + for (i = 0; i < num; i++, t++) {
> + if (!(t->lane_mask & lane_mask))
> + continue;
> +
> + if (t->in_layout)
> + writel(t->val, base + regs[t->offset]);
> + else
> + writel(t->val, base + t->offset);
> + }
> +}
> +
> +static void qcom_qmp_phy_configure(void __iomem *base,
> + const unsigned int *regs,
> + const struct qmp_phy_init_tbl tbl[],
> + int num)
> +{
> + qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
> +}
> +
> +static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
> +{
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
> + int serdes_tbl_num = cfg->serdes_tbl_num;
> + int ret;
> +
> + qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
> + if (cfg->serdes_tbl_sec)
> + qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
> + cfg->serdes_tbl_num_sec);
> +
> + if (cfg->type == PHY_TYPE_DP) {
> + switch (dp_opts->link_rate) {
> + case 1620:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_rbr,
> + cfg->serdes_tbl_rbr_num);
> + break;
> + case 2700:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_hbr,
> + cfg->serdes_tbl_hbr_num);
> + break;
> + case 5400:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_hbr2,
> + cfg->serdes_tbl_hbr2_num);
> + break;
> + case 8100:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_hbr3,
> + cfg->serdes_tbl_hbr3_num);
> + break;
> + default:
> + /* Other link rates aren't supported */
> + return -EINVAL;
> + }
> + }
> +
> +
> + if (cfg->has_phy_com_ctrl) {
> + void __iomem *status;
> + unsigned int mask, val;
> +
> + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
> + SERDES_START | PCS_START);
> +
> + status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
> + mask = cfg->mask_com_pcs_ready;
> +
> + ret = readl_poll_timeout(status, val, (val & mask), 10,
> + PHY_INIT_COMPLETE_TIMEOUT);
> + if (ret) {
> + dev_err(qmp->dev,
> + "phy common block init timed-out\n");
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
> +{
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
> + qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + /* Turn on BIAS current for PHY/PLL */
> + writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
> + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
> + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
> +
> + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_LANE_0_1_PWRDN |
> + DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
> + DP_PHY_PD_CTL_DP_CLAMP_EN,
> + qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + writel(QSERDES_V3_COM_BIAS_EN |
> + QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
> + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
> + QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
> + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
> +
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
> + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> + writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
> + writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
> + writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
> + qphy->dp_aux_cfg = 0;
> +
> + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
> + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
> + PHY_AUX_REQ_ERR_MASK,
> + qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
> +}
> +
> +static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
> + { 0x00, 0x0c, 0x15, 0x1a },
> + { 0x02, 0x0e, 0x16, 0xff },
> + { 0x02, 0x11, 0xff, 0xff },
> + { 0x04, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
> + { 0x02, 0x12, 0x16, 0x1a },
> + { 0x09, 0x19, 0x1f, 0xff },
> + { 0x10, 0x1f, 0xff, 0xff },
> + { 0x1f, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
> + { 0x00, 0x0c, 0x14, 0x19 },
> + { 0x00, 0x0b, 0x12, 0xff },
> + { 0x00, 0x0b, 0xff, 0xff },
> + { 0x04, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
> + { 0x08, 0x0f, 0x16, 0x1f },
> + { 0x11, 0x1e, 0x1f, 0xff },
> + { 0x19, 0x1f, 0xff, 0xff },
> + { 0x1f, 0xff, 0xff, 0xff }
> +};
> +
> +static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
> + unsigned int drv_lvl_reg, unsigned int emp_post_reg)
> +{
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + unsigned int v_level = 0, p_level = 0;
> + u8 voltage_swing_cfg, pre_emphasis_cfg;
> + int i;
> +
> + for (i = 0; i < dp_opts->lanes; i++) {
> + v_level = max(v_level, dp_opts->voltage[i]);
> + p_level = max(p_level, dp_opts->pre[i]);
> + }
> +
> + if (dp_opts->link_rate <= 2700) {
> + voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
> + pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
> + } else {
> + voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
> + pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
> + }
> +
> + /* TODO: Move check to config check */
> + if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
> + return -EINVAL;
> +
> + /* Enable MUX to use Cursor values from these registers */
> + voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
> + pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
> +
> + writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
> + writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
> + writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
> + writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
> +{
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + u32 bias_en, drvr_en;
> +
> + if (qcom_qmp_phy_configure_dp_swing(qphy,
> + QSERDES_V3_TX_TX_DRV_LVL,
> + QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
> + return;
> +
> + if (dp_opts->lanes == 1) {
> + bias_en = 0x3e;
> + drvr_en = 0x13;
> + } else {
> + bias_en = 0x3f;
> + drvr_en = 0x10;
> + }
> +
> + writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
> + writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
> + writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
> + writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
> +}
> +
> +static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
> +{
> + u32 val;
> + bool reverse = false;
> +
> + val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
> +
> + /*
> + * TODO: Assume orientation is CC1 for now and two lanes, need to
> + * use type-c connector to understand orientation and lanes.
> + *
> + * Otherwise val changes to be like below if this code understood
> + * the orientation of the type-c cable.
> + *
> + * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
> + * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
> + * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
> + * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
> + * if (orientation == ORIENTATION_CC2)
> + * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
> + */
> + val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
> + writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
> +
> + return reverse;
> +}
> +
> +static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + u32 phy_vco_div, status;
> + unsigned long pixel_freq;
> +
> + qcom_qmp_phy_configure_dp_mode(qphy);
> +
> + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
> + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + phy_vco_div = 0x1;
> + pixel_freq = 1620000000UL / 2;
> + break;
> + case 2700:
> + phy_vco_div = 0x1;
> + pixel_freq = 2700000000UL / 2;
> + break;
> + case 5400:
> + phy_vco_div = 0x2;
> + pixel_freq = 5400000000UL / 4;
> + break;
> + case 8100:
> + phy_vco_div = 0x0;
> + pixel_freq = 8100000000UL / 6;
> + break;
> + default:
> + /* Other link rates aren't supported */
> + return -EINVAL;
> + }
> + writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
> +
> + clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
> + clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
> +
> + writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
> + udelay(2000);
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000);
> +}
> +
> +/*
> + * We need to calibrate the aux setting here as many times
> + * as the caller tries
> + */
> +static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
> +{
> + static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
> + u8 val;
> +
> + qphy->dp_aux_cfg++;
> + qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
> + val = cfg1_settings[qphy->dp_aux_cfg];
> +
> + writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
> +{
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
> + qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + /* Turn on BIAS current for PHY/PLL */
> + writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
> +
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
> + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> + writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
> + writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
> + writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
> + qphy->dp_aux_cfg = 0;
> +
> + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
> + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
> + PHY_AUX_REQ_ERR_MASK,
> + qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
> +}
> +
> +static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
> +{
> + /* Program default values before writing proper values */
> + writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
> + writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
> +
> + writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> + writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> +
> + qcom_qmp_phy_configure_dp_swing(qphy,
> + QSERDES_V4_TX_TX_DRV_LVL,
> + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> +}
> +
> +static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + u32 phy_vco_div, status;
> + unsigned long pixel_freq;
> + u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
> + bool reverse;
> +
> + writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
> +
> + reverse = qcom_qmp_phy_configure_dp_mode(qphy);
> +
> + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> + writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> +
> + writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
> + writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + phy_vco_div = 0x1;
> + pixel_freq = 1620000000UL / 2;
> + break;
> + case 2700:
> + phy_vco_div = 0x1;
> + pixel_freq = 2700000000UL / 2;
> + break;
> + case 5400:
> + phy_vco_div = 0x2;
> + pixel_freq = 5400000000UL / 4;
> + break;
> + case 8100:
> + phy_vco_div = 0x0;
> + pixel_freq = 8100000000UL / 6;
> + break;
> + default:
> + /* Other link rates aren't supported */
> + return -EINVAL;
> + }
> + writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
> +
> + clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
> + clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
> +
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + /*
> + * At least for 7nm DP PHY this has to be done after enabling link
> + * clock.
> + */
> +
> + if (dp_opts->lanes == 1) {
> + bias0_en = reverse ? 0x3e : 0x15;
> + bias1_en = reverse ? 0x15 : 0x3e;
> + drvr0_en = reverse ? 0x13 : 0x10;
> + drvr1_en = reverse ? 0x10 : 0x13;
> + } else if (dp_opts->lanes == 2) {
> + bias0_en = reverse ? 0x3f : 0x15;
> + bias1_en = reverse ? 0x15 : 0x3f;
> + drvr0_en = 0x10;
> + drvr1_en = 0x10;
> + } else {
> + bias0_en = 0x3f;
> + bias1_en = 0x3f;
> + drvr0_en = 0x10;
> + drvr1_en = 0x10;
> + }
> +
> + writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
> + writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
> + writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
> + writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
> +
> + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
> + udelay(2000);
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
> + writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
> +
> + writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
> + writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
> +
> + writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> + writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> +
> + return 0;
> +}
> +
> +/*
> + * We need to calibrate the aux setting here as many times
> + * as the caller tries
> + */
> +static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
> +{
> + static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
> + u8 val;
> +
> + qphy->dp_aux_cfg++;
> + qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
> + val = cfg1_settings[qphy->dp_aux_cfg];
> +
> + writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
> +{
> + const struct phy_configure_opts_dp *dp_opts = &opts->dp;
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
> + if (qphy->dp_opts.set_voltages) {
> + cfg->configure_dp_tx(qphy);
> + qphy->dp_opts.set_voltages = 0;
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + if (cfg->calibrate_dp_phy)
> + return cfg->calibrate_dp_phy(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
> +{
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *dp_com = qmp->dp_com;
> + int ret, i;
> +
> + mutex_lock(&qmp->phy_mutex);
> + if (qmp->init_count++) {
> + mutex_unlock(&qmp->phy_mutex);
> + return 0;
> + }
> +
> + /* turn on regulator supplies */
> + ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
> + if (ret) {
> + dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
> + goto err_unlock;
> + }
> +
> + for (i = 0; i < cfg->num_resets; i++) {
> + ret = reset_control_assert(qmp->resets[i]);
> + if (ret) {
> + dev_err(qmp->dev, "%s reset assert failed\n",
> + cfg->reset_list[i]);
> + goto err_disable_regulators;
> + }
> + }
> +
> + for (i = cfg->num_resets - 1; i >= 0; i--) {
> + ret = reset_control_deassert(qmp->resets[i]);
> + if (ret) {
> + dev_err(qmp->dev, "%s reset deassert failed\n",
> + qphy->cfg->reset_list[i]);
> + goto err_assert_reset;
> + }
> + }
> +
> + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
> + if (ret)
> + goto err_assert_reset;
> +
> + if (cfg->has_phy_dp_com_ctrl) {
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
> + SW_PWRDN);
> + /* override hardware control for reset of qmp phy */
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
> + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
> + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
> +
> + /* Default type-c orientation, i.e CC1 */
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
> +
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
> + USB3_MODE | DP_MODE);
> +
> + /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
> + qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
> + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
> + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
> +
> + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
> + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
> + }
> +
> + if (cfg->has_phy_com_ctrl) {
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
> + SW_PWRDN);
> + } else {
> + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
> + qphy_setbits(pcs,
> + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
> + cfg->pwrdn_ctrl);
> + else
> + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
> + cfg->pwrdn_ctrl);
> + }
> +
> + mutex_unlock(&qmp->phy_mutex);
> +
> + return 0;
> +
> +err_assert_reset:
> + while (++i < cfg->num_resets)
> + reset_control_assert(qmp->resets[i]);
> +err_disable_regulators:
> + regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
> +err_unlock:
> + mutex_unlock(&qmp->phy_mutex);
> +
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
> +{
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + int i = cfg->num_resets;
> +
> + mutex_lock(&qmp->phy_mutex);
> + if (--qmp->init_count) {
> + mutex_unlock(&qmp->phy_mutex);
> + return 0;
> + }
> +
> + reset_control_assert(qmp->ufs_reset);
> + if (cfg->has_phy_com_ctrl) {
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
> + SERDES_START | PCS_START);
> + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
> + SW_RESET);
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
> + SW_PWRDN);
> + }
> +
> + while (--i >= 0)
> + reset_control_assert(qmp->resets[i]);
> +
> + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
> +
> + regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
> +
> + mutex_unlock(&qmp->phy_mutex);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_init(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + int ret;
> + dev_vdbg(qmp->dev, "Initializing QMP phy\n");
> +
> + if (cfg->no_pcs_sw_reset) {
> + /*
> + * Get UFS reset, which is delayed until now to avoid a
> + * circular dependency where UFS needs its PHY, but the PHY
> + * needs this UFS reset.
> + */
> + if (!qmp->ufs_reset) {
> + qmp->ufs_reset =
> + devm_reset_control_get_exclusive(qmp->dev,
> + "ufsphy");
> +
> + if (IS_ERR(qmp->ufs_reset)) {
> + ret = PTR_ERR(qmp->ufs_reset);
> + dev_err(qmp->dev,
> + "failed to get UFS reset: %d\n",
> + ret);
> +
> + qmp->ufs_reset = NULL;
> + return ret;
> + }
> + }
> +
> + ret = reset_control_assert(qmp->ufs_reset);
> + if (ret)
> + return ret;
> + }
> +
> + ret = qcom_qmp_phy_com_init(qphy);
> + if (ret)
> + return ret;
> +
> + if (cfg->type == PHY_TYPE_DP)
> + cfg->dp_aux_init(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_power_on(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *tx = qphy->tx;
> + void __iomem *rx = qphy->rx;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *pcs_misc = qphy->pcs_misc;
> + void __iomem *status;
> + unsigned int mask, val, ready;
> + int ret;
> +
> + qcom_qmp_phy_serdes_init(qphy);
> +
> + if (cfg->has_lane_rst) {
> + ret = reset_control_deassert(qphy->lane_rst);
> + if (ret) {
> + dev_err(qmp->dev, "lane%d reset deassert failed\n",
> + qphy->index);
> + return ret;
> + }
> + }
> +
> + ret = clk_prepare_enable(qphy->pipe_clk);
> + if (ret) {
> + dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
> + goto err_reset_lane;
> + }
> +
> + /* Tx, Rx, and PCS configurations */
> + qcom_qmp_phy_configure_lane(tx, cfg->regs,
> + cfg->tx_tbl, cfg->tx_tbl_num, 1);
> + if (cfg->tx_tbl_sec)
> + qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
> + cfg->tx_tbl_num_sec, 1);
> +
> + /* Configuration for other LANE for USB-DP combo PHY */
> + if (cfg->is_dual_lane_phy) {
> + qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
> + cfg->tx_tbl, cfg->tx_tbl_num, 2);
> + if (cfg->tx_tbl_sec)
> + qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
> + cfg->tx_tbl_sec,
> + cfg->tx_tbl_num_sec, 2);
> + }
> +
> + /* Configure special DP tx tunings */
> + if (cfg->type == PHY_TYPE_DP)
> + cfg->configure_dp_tx(qphy);
> +
> + qcom_qmp_phy_configure_lane(rx, cfg->regs,
> + cfg->rx_tbl, cfg->rx_tbl_num, 1);
> + if (cfg->rx_tbl_sec)
> + qcom_qmp_phy_configure_lane(rx, cfg->regs,
> + cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
> +
> + if (cfg->is_dual_lane_phy) {
> + qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
> + cfg->rx_tbl, cfg->rx_tbl_num, 2);
> + if (cfg->rx_tbl_sec)
> + qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
> + cfg->rx_tbl_sec,
> + cfg->rx_tbl_num_sec, 2);
> + }
> +
> + /* Configure link rate, swing, etc. */
> + if (cfg->type == PHY_TYPE_DP) {
> + cfg->configure_dp_phy(qphy);
> + } else {
> + qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
> + if (cfg->pcs_tbl_sec)
> + qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
> + cfg->pcs_tbl_num_sec);
> + }
> +
> + ret = reset_control_deassert(qmp->ufs_reset);
> + if (ret)
> + goto err_disable_pipe_clk;
> +
> + qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
> + cfg->pcs_misc_tbl_num);
> + if (cfg->pcs_misc_tbl_sec)
> + qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
> + cfg->pcs_misc_tbl_num_sec);
> +
> + /*
> + * Pull out PHY from POWER DOWN state.
> + * This is active low enable signal to power-down PHY.
> + */
> + if(cfg->type == PHY_TYPE_PCIE)
> + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
> +
> + if (cfg->has_pwrdn_delay)
> + usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
> +
> + if (cfg->type != PHY_TYPE_DP) {
> + /* Pull PHY out of reset state */
> + if (!cfg->no_pcs_sw_reset)
> + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
> + /* start SerDes and Phy-Coding-Sublayer */
> + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
> +
> + if (cfg->type == PHY_TYPE_UFS) {
> + status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
> + mask = PCS_READY;
> + ready = PCS_READY;
> + } else {
> + status = pcs + cfg->regs[QPHY_PCS_STATUS];
> + mask = cfg->phy_status;
> + ready = 0;
> + }
> +
> + ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
> + PHY_INIT_COMPLETE_TIMEOUT);
> + if (ret) {
> + dev_err(qmp->dev, "phy initialization timed-out\n");
> + goto err_disable_pipe_clk;
> + }
> + }
> + return 0;
> +
> +err_disable_pipe_clk:
> + clk_disable_unprepare(qphy->pipe_clk);
> +err_reset_lane:
> + if (cfg->has_lane_rst)
> + reset_control_assert(qphy->lane_rst);
> +
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_power_off(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + clk_disable_unprepare(qphy->pipe_clk);
> +
> + if (cfg->type == PHY_TYPE_DP) {
> + /* Assert DP PHY power down */
> + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> + } else {
> + /* PHY reset */
> + if (!cfg->no_pcs_sw_reset)
> + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
> +
> + /* stop SerDes and Phy-Coding-Sublayer */
> + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
> +
> + /* Put PHY into POWER DOWN state: active low */
> + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
> + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
> + cfg->pwrdn_ctrl);
> + } else {
> + qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
> + cfg->pwrdn_ctrl);
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_exit(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + if (cfg->has_lane_rst)
> + reset_control_assert(qphy->lane_rst);
> +
> + qcom_qmp_phy_com_exit(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_enable(struct phy *phy)
> +{
> + int ret;
> +
> + ret = qcom_qmp_phy_init(phy);
> + if (ret)
> + return ret;
> +
> + ret = qcom_qmp_phy_power_on(phy);
> + if (ret)
> + qcom_qmp_phy_exit(phy);
> +
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_disable(struct phy *phy)
> +{
> + int ret;
> +
> + ret = qcom_qmp_phy_power_off(phy);
> + if (ret)
> + return ret;
> + return qcom_qmp_phy_exit(phy);
> +}
> +
> +static int qcom_qmp_phy_set_mode(struct phy *phy,
> + enum phy_mode mode, int submode)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> +
> + qphy->mode = mode;
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *pcs_misc = qphy->pcs_misc;
> + u32 intr_mask;
> +
> + if (qphy->mode == PHY_MODE_USB_HOST_SS ||
> + qphy->mode == PHY_MODE_USB_DEVICE_SS)
> + intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
> + else
> + intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
> +
> + /* Clear any pending interrupts status */
> + qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> + /* Writing 1 followed by 0 clears the interrupt */
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> +
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
> + ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
> +
> + /* Enable required PHY autonomous mode interrupts */
> + qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
> +
> + /* Enable i/o clamp_n for autonomous mode */
> + if (pcs_misc)
> + qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
> +}
> +
> +static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *pcs_misc = qphy->pcs_misc;
> +
> + /* Disable i/o clamp_n on resume for normal mode */
> + if (pcs_misc)
> + qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
> +
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
> + ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
> +
> + qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> + /* Writing 1 followed by 0 clears the interrupt */
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> +}
> +
> +static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + struct qmp_phy *qphy = qmp->phys[0];
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
> +
> + /* Supported only for USB3 PHY and luckily USB3 is the first phy */
> + if (cfg->type != PHY_TYPE_USB3)
> + return 0;
> +
> + if (!qmp->init_count) {
> + dev_vdbg(dev, "PHY not initialized, bailing out\n");
> + return 0;
> + }
> +
> + qcom_qmp_phy_enable_autonomous_mode(qphy);
> +
> + clk_disable_unprepare(qphy->pipe_clk);
> + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
> +
> + return 0;
> +}
> +
> +static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + struct qmp_phy *qphy = qmp->phys[0];
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + int ret = 0;
> +
> + dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
> +
> + /* Supported only for USB3 PHY and luckily USB3 is the first phy */
> + if (cfg->type != PHY_TYPE_USB3)
> + return 0;
> +
> + if (!qmp->init_count) {
> + dev_vdbg(dev, "PHY not initialized, bailing out\n");
> + return 0;
> + }
> +
> + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(qphy->pipe_clk);
> + if (ret) {
> + dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
> + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
> + return ret;
> + }
> +
> + qcom_qmp_phy_disable_autonomous_mode(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + int num = cfg->num_vregs;
> + int i;
> +
> + qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
> + if (!qmp->vregs)
> + return -ENOMEM;
> +
> + for (i = 0; i < num; i++)
> + qmp->vregs[i].supply = cfg->vreg_list[i];
> +
> + return devm_regulator_bulk_get(dev, num, qmp->vregs);
> +}
> +
> +static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + int i;
> +
> + qmp->resets = devm_kcalloc(dev, cfg->num_resets,
> + sizeof(*qmp->resets), GFP_KERNEL);
> + if (!qmp->resets)
> + return -ENOMEM;
> +
> + for (i = 0; i < cfg->num_resets; i++) {
> + struct reset_control *rst;
> + const char *name = cfg->reset_list[i];
> +
> + rst = devm_reset_control_get_exclusive(dev, name);
> + if (IS_ERR(rst)) {
> + dev_err(dev, "failed to get %s reset\n", name);
> + return PTR_ERR(rst);
> + }
> + qmp->resets[i] = rst;
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + int num = cfg->num_clks;
> + int i;
> +
> + qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
> + if (!qmp->clks)
> + return -ENOMEM;
> +
> + for (i = 0; i < num; i++)
> + qmp->clks[i].id = cfg->clk_list[i];
> +
> + return devm_clk_bulk_get(dev, num, qmp->clks);
> +}
> +
> +static void phy_clk_release_provider(void *res)
> +{
> + of_clk_del_provider(res);
> +}
> +
> +/*
> + * Register a fixed rate pipe clock.
> + *
> + * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
> + * controls it. The <s>_pipe_clk coming out of the GCC is requested
> + * by the PHY driver for its operations.
> + * We register the <s>_pipe_clksrc here. The gcc driver takes care
> + * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
> + * Below picture shows this relationship.
> + *
> + * +---------------+
> + * | PHY block |<<---------------------------------------+
> + * | | |
> + * | +-------+ | +-----+ |
> + * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
> + * clk | +-------+ | +-----+
> + * +---------------+
> + */
> +static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
> +{
> + struct clk_fixed_rate *fixed;
> + struct clk_init_data init = { };
> + int ret;
> +
> + ret = of_property_read_string(np, "clock-output-names", &init.name);
> + if (ret) {
> + dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
> + return ret;
> + }
> +
> + fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
> + if (!fixed)
> + return -ENOMEM;
> +
> + init.ops = &clk_fixed_rate_ops;
> +
> + /* controllers using QMP phys use 125MHz pipe clock interface */
> + fixed->fixed_rate = 125000000;
> + fixed->hw.init = &init;
> +
> + ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
> + if (ret)
> + return ret;
> +
> + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
> + if (ret)
> + return ret;
> +
> + /*
> + * Roll a devm action because the clock provider is the child node, but
> + * the child node is not actually a device.
> + */
> + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
> +}
> +
> +/*
> + * Display Port PLL driver block diagram for branch clocks
> + *
> + * +------------------------------+
> + * | DP_VCO_CLK |
> + * | |
> + * | +-------------------+ |
> + * | | (DP PLL/VCO) | |
> + * | +---------+---------+ |
> + * | v |
> + * | +----------+-----------+ |
> + * | | hsclk_divsel_clk_src | |
> + * | +----------+-----------+ |
> + * +------------------------------+
> + * |
> + * +---------<---------v------------>----------+
> + * | |
> + * +--------v----------------+ |
> + * | dp_phy_pll_link_clk | |
> + * | link_clk | |
> + * +--------+----------------+ |
> + * | |
> + * | |
> + * v v
> + * Input to DISPCC block |
> + * for link clk, crypto clk |
> + * and interface clock |
> + * |
> + * |
> + * +--------<------------+-----------------+---<---+
> + * | | |
> + * +----v---------+ +--------v-----+ +--------v------+
> + * | vco_divided | | vco_divided | | vco_divided |
> + * | _clk_src | | _clk_src | | _clk_src |
> + * | | | | | |
> + * |divsel_six | | divsel_two | | divsel_four |
> + * +-------+------+ +-----+--------+ +--------+------+
> + * | | |
> + * v---->----------v-------------<------v
> + * |
> + * +----------+-----------------+
> + * | dp_phy_pll_vco_div_clk |
> + * +---------+------------------+
> + * |
> + * v
> + * Input to DISPCC block
> + * for DP pixel clock
> + *
> + */
> +static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + switch (req->rate) {
> + case 1620000000UL / 2:
> + case 2700000000UL / 2:
> + /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
> + return 0;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static unsigned long
> +qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + const struct qmp_phy_dp_clks *dp_clks;
> + const struct qmp_phy *qphy;
> + const struct phy_configure_opts_dp *dp_opts;
> +
> + dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
> + qphy = dp_clks->qphy;
> + dp_opts = &qphy->dp_opts;
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + return 1620000000UL / 2;
> + case 2700:
> + return 2700000000UL / 2;
> + case 5400:
> + return 5400000000UL / 4;
> + case 8100:
> + return 8100000000UL / 6;
> + default:
> + return 0;
> + }
> +}
> +
> +static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
> + .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
> + .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
> +};
> +
> +static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + switch (req->rate) {
> + case 162000000:
> + case 270000000:
> + case 540000000:
> + case 810000000:
> + return 0;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static unsigned long
> +qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + const struct qmp_phy_dp_clks *dp_clks;
> + const struct qmp_phy *qphy;
> + const struct phy_configure_opts_dp *dp_opts;
> +
> + dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
> + qphy = dp_clks->qphy;
> + dp_opts = &qphy->dp_opts;
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + case 2700:
> + case 5400:
> + case 8100:
> + return dp_opts->link_rate * 100000;
> + default:
> + return 0;
> + }
> +}
> +
> +static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
> + .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
> + .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
> +};
> +
> +static struct clk_hw *
> +qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
> +{
> + struct qmp_phy_dp_clks *dp_clks = data;
> + unsigned int idx = clkspec->args[0];
> +
> + if (idx >= 2) {
> + pr_err("%s: invalid index %u\n", __func__, idx);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + if (idx == 0)
> + return &dp_clks->dp_link_hw;
> +
> + return &dp_clks->dp_pixel_hw;
> +}
> +
> +static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
> + struct device_node *np)
> +{
> + struct clk_init_data init = { };
> + struct qmp_phy_dp_clks *dp_clks;
> + char name[64];
> + int ret;
> +
> + dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
> + if (!dp_clks)
> + return -ENOMEM;
> +
> + dp_clks->qphy = qphy;
> + qphy->dp_clks = dp_clks;
> +
> + snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
> + init.ops = &qcom_qmp_dp_link_clk_ops;
> + init.name = name;
> + dp_clks->dp_link_hw.init = &init;
> + ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
> + if (ret)
> + return ret;
> +
> + snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
> + init.ops = &qcom_qmp_dp_pixel_clk_ops;
> + init.name = name;
> + dp_clks->dp_pixel_hw.init = &init;
> + ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
> + if (ret)
> + return ret;
> +
> + ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
> + if (ret)
> + return ret;
> +
> + /*
> + * Roll a devm action because the clock provider is the child node, but
> + * the child node is not actually a device.
> + */
> + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
> +}
> +
> +static const struct phy_ops qcom_qmp_phy_gen_ops = {
> + .init = qcom_qmp_phy_enable,
> + .exit = qcom_qmp_phy_disable,
> + .set_mode = qcom_qmp_phy_set_mode,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct phy_ops qcom_qmp_phy_dp_ops = {
> + .init = qcom_qmp_phy_init,
> + .configure = qcom_qmp_dp_phy_configure,
> + .power_on = qcom_qmp_phy_power_on,
> + .calibrate = qcom_qmp_dp_phy_calibrate,
> + .power_off = qcom_qmp_phy_power_off,
> + .exit = qcom_qmp_phy_exit,
> + .set_mode = qcom_qmp_phy_set_mode,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
> + .power_on = qcom_qmp_phy_enable,
> + .power_off = qcom_qmp_phy_disable,
> + .set_mode = qcom_qmp_phy_set_mode,
> + .owner = THIS_MODULE,
> +};
> +
> +static void qcom_qmp_reset_control_put(void *data)
> +{
> + reset_control_put(data);
> +}
> +
> +static
> +int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
> + void __iomem *serdes, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + struct phy *generic_phy;
> + struct qmp_phy *qphy;
> + const struct phy_ops *ops;
> + char prop_name[MAX_PROP_NAME];
> + int ret;
> +
> + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
> + if (!qphy)
> + return -ENOMEM;
> +
> + qphy->cfg = cfg;
> + qphy->serdes = serdes;
> + /*
> + * Get memory resources for each phy lane:
> + * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
> + * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
> + * For single lane PHYs: pcs_misc (optional) -> 3.
> + */
> + qphy->tx = of_iomap(np, 0);
> + if (!qphy->tx)
> + return -ENOMEM;
> +
> + qphy->rx = of_iomap(np, 1);
> + if (!qphy->rx)
> + return -ENOMEM;
> +
> + qphy->pcs = of_iomap(np, 2);
> + if (!qphy->pcs)
> + return -ENOMEM;
> +
> + /*
> + * If this is a dual-lane PHY, then there should be registers for the
> + * second lane. Some old device trees did not specify this, so fall
> + * back to old legacy behavior of assuming they can be reached at an
> + * offset from the first lane.
> + */
> + if (cfg->is_dual_lane_phy) {
> + qphy->tx2 = of_iomap(np, 3);
> + qphy->rx2 = of_iomap(np, 4);
> + if (!qphy->tx2 || !qphy->rx2) {
> + dev_warn(dev,
> + "Underspecified device tree, falling back to legacy register regions\n");
> +
> + /* In the old version, pcs_misc is at index 3. */
> + qphy->pcs_misc = qphy->tx2;
> + qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
> + qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
> +
> + } else {
> + qphy->pcs_misc = of_iomap(np, 5);
> + }
> +
> + } else {
> + qphy->pcs_misc = of_iomap(np, 3);
> + }
> +
> + if (!qphy->pcs_misc)
> + dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
> +
> + /*
> + * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
> + * based phys, so they essentially have pipe clock. So,
> + * we return error in case phy is USB3 or PIPE type.
> + * Otherwise, we initialize pipe clock to NULL for
> + * all phys that don't need this.
> + */
> + snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
> + qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
> + if (IS_ERR(qphy->pipe_clk)) {
> + if (cfg->type == PHY_TYPE_PCIE ||
> + cfg->type == PHY_TYPE_USB3) {
> + ret = PTR_ERR(qphy->pipe_clk);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev,
> + "failed to get lane%d pipe_clk, %d\n",
> + id, ret);
> + return ret;
> + }
> + qphy->pipe_clk = NULL;
> + }
> +
> + /* Get lane reset, if any */
> + if (cfg->has_lane_rst) {
> + snprintf(prop_name, sizeof(prop_name), "lane%d", id);
> + qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
> + if (IS_ERR(qphy->lane_rst)) {
> + dev_err(dev, "failed to get lane%d reset\n", id);
> + return PTR_ERR(qphy->lane_rst);
> + }
> + ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
> + qphy->lane_rst);
> + if (ret)
> + return ret;
> + }
> +
> + if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
> + ops = &qcom_qmp_pcie_ufs_ops;
> + else if (cfg->type == PHY_TYPE_DP)
> + ops = &qcom_qmp_phy_dp_ops;
> + else
> + ops = &qcom_qmp_phy_gen_ops;
> +
> + generic_phy = devm_phy_create(dev, np, ops);
> + if (IS_ERR(generic_phy)) {
> + ret = PTR_ERR(generic_phy);
> + dev_err(dev, "failed to create qphy %d\n", ret);
> + return ret;
> + }
> +
> + qphy->phy = generic_phy;
> + qphy->index = id;
> + qphy->qmp = qmp;
> + qmp->phys[id] = qphy;
> + phy_set_drvdata(generic_phy, qphy);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
> + {
> + .compatible = "qcom,ipq8074-qmp-usb3-phy",
> + .data = &ipq8074_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,msm8996-qmp-pcie-phy",
> + .data = &msm8996_pciephy_cfg,
> + }, {
> + .compatible = "qcom,msm8996-qmp-ufs-phy",
> + .data = &msm8996_ufs_cfg,
> + }, {
> + .compatible = "qcom,msm8996-qmp-usb3-phy",
> + .data = &msm8996_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,msm8998-qmp-pcie-phy",
> + .data = &msm8998_pciephy_cfg,
> + }, {
> + .compatible = "qcom,msm8998-qmp-ufs-phy",
> + .data = &sdm845_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,ipq8074-qmp-pcie-phy",
> + .data = &ipq8074_pciephy_cfg,
> + }, {
> + .compatible = "qcom,ipq6018-qmp-pcie-phy",
> + .data = &ipq6018_pciephy_cfg,
> + }, {
> + .compatible = "qcom,ipq6018-qmp-usb3-phy",
> + .data = &ipq8074_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sc7180-qmp-usb3-phy",
> + .data = &sc7180_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
> + /* It's a combo phy */
> + }, {
> + .compatible = "qcom,sc8180x-qmp-pcie-phy",
> + .data = &sc8180x_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sc8180x-qmp-ufs-phy",
> + .data = &sm8150_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sc8280xp-qmp-ufs-phy",
> + .data = &sm8350_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sc8180x-qmp-usb3-phy",
> + .data = &sm8150_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
> + /* It's a combo phy */
> + }, {
> + .compatible = "qcom,sdm845-qhp-pcie-phy",
> + .data = &sdm845_qhp_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-pcie-phy",
> + .data = &sdm845_qmp_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-usb3-phy",
> + .data = &qmp_v3_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
> + .data = &qmp_v3_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-ufs-phy",
> + .data = &sdm845_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,msm8998-qmp-usb3-phy",
> + .data = &msm8998_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm6115-qmp-ufs-phy",
> + .data = &sm6115_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm6350-qmp-ufs-phy",
> + .data = &sdm845_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8150-qmp-ufs-phy",
> + .data = &sm8150_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-ufs-phy",
> + .data = &sm8150_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8150-qmp-usb3-phy",
> + .data = &sm8150_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
> + .data = &sm8150_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-usb3-phy",
> + .data = &sm8250_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
> + /* It's a combo phy */
> + }, {
> + .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
> + .data = &sm8250_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
> + .data = &sm8250_qmp_gen3x1_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
> + .data = &sm8250_qmp_gen3x2_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8350-qmp-ufs-phy",
> + .data = &sm8350_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
> + .data = &sm8250_qmp_gen3x2_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdx55-qmp-pcie-phy",
> + .data = &sdx55_qmp_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
> + .data = &sdx55_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
> + .data = &sdx65_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8350-qmp-usb3-phy",
> + .data = &sm8350_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
> + .data = &sm8350_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
> + .data = &sm8450_qmp_gen3x1_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
> + .data = &sm8450_qmp_gen4x2_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-ufs-phy",
> + .data = &sm8450_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-usb3-phy",
> + .data = &sm8350_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,qcm2290-qmp-usb3-phy",
> + .data = &qcm2290_usb3phy_cfg,
> + },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
> +
> +static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
> + {
> + .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
> + .data = &sc7180_usb3dpphy_cfg,
> + },
> + {
> + .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
> + .data = &sm8250_usb3dpphy_cfg,
> + },
> + {
> + .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
> + .data = &sc8180x_usb3dpphy_cfg,
> + },
> + { }
> +};
> +
> +static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
> + SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
> + qcom_qmp_phy_runtime_resume, NULL)
> +};
> +
> +static int qcom_qmp_phy_probe(struct platform_device *pdev)
> +{
> + struct qcom_qmp *qmp;
> + struct device *dev = &pdev->dev;
> + struct device_node *child;
> + struct phy_provider *phy_provider;
> + void __iomem *serdes;
> + void __iomem *usb_serdes;
> + void __iomem *dp_serdes = NULL;
> + const struct qmp_phy_combo_cfg *combo_cfg = NULL;
> + const struct qmp_phy_cfg *cfg = NULL;
> + const struct qmp_phy_cfg *usb_cfg = NULL;
> + const struct qmp_phy_cfg *dp_cfg = NULL;
> + int num, id, expected_phys;
> + int ret;
> +
> + qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
> + if (!qmp)
> + return -ENOMEM;
> +
> + qmp->dev = dev;
> + dev_set_drvdata(dev, qmp);
> +
> + /* Get the specific init parameters of QMP phy */
> + cfg = of_device_get_match_data(dev);
> + if (!cfg) {
> + const struct of_device_id *match;
> +
> + match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
> + if (!match)
> + return -EINVAL;
> +
> + combo_cfg = match->data;
> + if (!combo_cfg)
> + return -EINVAL;
> +
> + usb_cfg = combo_cfg->usb_cfg;
> + cfg = usb_cfg; /* Setup clks and regulators */
> + }
> +
> + /* per PHY serdes; usually located at base address */
> + usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(serdes))
> + return PTR_ERR(serdes);
> +
> + /* per PHY dp_com; if PHY has dp_com control block */
> + if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
> + qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
> + if (IS_ERR(qmp->dp_com))
> + return PTR_ERR(qmp->dp_com);
> + }
> +
> + if (combo_cfg) {
> + /* Only two serdes for combo PHY */
> + dp_serdes = devm_platform_ioremap_resource(pdev, 2);
> + if (IS_ERR(dp_serdes))
> + return PTR_ERR(dp_serdes);
> +
> + dp_cfg = combo_cfg->dp_cfg;
> + expected_phys = 2;
> + } else {
> + expected_phys = cfg->nlanes;
> + }
> +
> + mutex_init(&qmp->phy_mutex);
> +
> + ret = qcom_qmp_phy_clk_init(dev, cfg);
> + if (ret)
> + return ret;
> +
> + ret = qcom_qmp_phy_reset_init(dev, cfg);
> + if (ret)
> + return ret;
> +
> + ret = qcom_qmp_phy_vreg_init(dev, cfg);
> + if (ret) {
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "failed to get regulator supplies: %d\n",
> + ret);
> + return ret;
> + }
> +
> + num = of_get_available_child_count(dev->of_node);
> + /* do we have a rogue child node ? */
> + if (num > expected_phys)
> + return -EINVAL;
> +
> + qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
> + if (!qmp->phys)
> + return -ENOMEM;
> +
> + pm_runtime_set_active(dev);
> + pm_runtime_enable(dev);
> + /*
> + * Prevent runtime pm from being ON by default. Users can enable
> + * it using power/control in sysfs.
> + */
> + pm_runtime_forbid(dev);
> +
> + id = 0;
> + for_each_available_child_of_node(dev->of_node, child) {
> + if (of_node_name_eq(child, "dp-phy")) {
> + cfg = dp_cfg;
> + serdes = dp_serdes;
> + } else if (of_node_name_eq(child, "usb3-phy")) {
> + cfg = usb_cfg;
> + serdes = usb_serdes;
> + }
> +
> + /* Create per-lane phy */
> + ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
> + if (ret) {
> + dev_err(dev, "failed to create lane%d phy, %d\n",
> + id, ret);
> + goto err_node_put;
> + }
> +
> + /*
> + * Register the pipe clock provided by phy.
> + * See function description to see details of this pipe clock.
> + */
> + if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
> + ret = phy_pipe_clk_register(qmp, child);
> + if (ret) {
> + dev_err(qmp->dev,
> + "failed to register pipe clock source\n");
> + goto err_node_put;
> + }
> + } else if (cfg->type == PHY_TYPE_DP) {
> + ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
> + if (ret) {
> + dev_err(qmp->dev,
> + "failed to register DP clock source\n");
> + goto err_node_put;
> + }
> + }
> + id++;
> + }
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (!IS_ERR(phy_provider))
> + dev_info(dev, "Registered Qcom-QMP phy\n");
> + else
> + pm_runtime_disable(dev);
> +
> + return PTR_ERR_OR_ZERO(phy_provider);
> +
> +err_node_put:
> + pm_runtime_disable(dev);
> + of_node_put(child);
> + return ret;
> +}
> +
> +static struct platform_driver qcom_qmp_phy_driver = {
> + .probe = qcom_qmp_phy_probe,
> + .driver = {
> + .name = "qcom-qmp-phy",
> + .pm = &qcom_qmp_phy_pm_ops,
> + .of_match_table = qcom_qmp_phy_of_match_table,
> + },
> +};
> +
> +module_platform_driver(qcom_qmp_phy_driver);
> +
> +MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
> +MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
> new file mode 100644
> index 000000000000..c7309e981bfb
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
> @@ -0,0 +1,6350 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2017, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +
> +#include <dt-bindings/phy/phy.h>
> +
> +#include "phy-qcom-qmp.h"
> +
> +/* QPHY_SW_RESET bit */
> +#define SW_RESET BIT(0)
> +/* QPHY_POWER_DOWN_CONTROL */
> +#define SW_PWRDN BIT(0)
> +#define REFCLK_DRV_DSBL BIT(1)
> +/* QPHY_START_CONTROL bits */
> +#define SERDES_START BIT(0)
> +#define PCS_START BIT(1)
> +#define PLL_READY_GATE_EN BIT(3)
> +/* QPHY_PCS_STATUS bit */
> +#define PHYSTATUS BIT(6)
> +#define PHYSTATUS_4_20 BIT(7)
> +/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
> +#define PCS_READY BIT(0)
> +
> +/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
> +/* DP PHY soft reset */
> +#define SW_DPPHY_RESET BIT(0)
> +/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
> +#define SW_DPPHY_RESET_MUX BIT(1)
> +/* USB3 PHY soft reset */
> +#define SW_USB3PHY_RESET BIT(2)
> +/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
> +#define SW_USB3PHY_RESET_MUX BIT(3)
> +
> +/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
> +#define USB3_MODE BIT(0) /* enables USB3 mode */
> +#define DP_MODE BIT(1) /* enables DP mode */
> +
> +/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
> +#define ARCVR_DTCT_EN BIT(0)
> +#define ALFPS_DTCT_EN BIT(1)
> +#define ARCVR_DTCT_EVENT_SEL BIT(4)
> +
> +/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
> +#define IRQ_CLEAR BIT(0)
> +
> +/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
> +#define RCVR_DETECT BIT(0)
> +
> +/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
> +#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
> +
> +#define PHY_INIT_COMPLETE_TIMEOUT 10000
> +#define POWER_DOWN_DELAY_US_MIN 10
> +#define POWER_DOWN_DELAY_US_MAX 11
> +
> +#define MAX_PROP_NAME 32
> +
> +/* Define the assumed distance between lanes for underspecified device trees. */
> +#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
> +
> +struct qmp_phy_init_tbl {
> + unsigned int offset;
> + unsigned int val;
> + /*
> + * register part of layout ?
> + * if yes, then offset gives index in the reg-layout
> + */
> + bool in_layout;
> + /*
> + * mask of lanes for which this register is written
> + * for cases when second lane needs different values
> + */
> + u8 lane_mask;
> +};
> +
> +#define QMP_PHY_INIT_CFG(o, v) \
> + { \
> + .offset = o, \
> + .val = v, \
> + .lane_mask = 0xff, \
> + }
> +
> +#define QMP_PHY_INIT_CFG_L(o, v) \
> + { \
> + .offset = o, \
> + .val = v, \
> + .in_layout = true, \
> + .lane_mask = 0xff, \
> + }
> +
> +#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
> + { \
> + .offset = o, \
> + .val = v, \
> + .lane_mask = l, \
> + }
> +
> +/* set of registers with offsets different per-PHY */
> +enum qphy_reg_layout {
> + /* Common block control registers */
> + QPHY_COM_SW_RESET,
> + QPHY_COM_POWER_DOWN_CONTROL,
> + QPHY_COM_START_CONTROL,
> + QPHY_COM_PCS_READY_STATUS,
> + /* PCS registers */
> + QPHY_PLL_LOCK_CHK_DLY_TIME,
> + QPHY_FLL_CNTRL1,
> + QPHY_FLL_CNTRL2,
> + QPHY_FLL_CNT_VAL_L,
> + QPHY_FLL_CNT_VAL_H_TOL,
> + QPHY_FLL_MAN_CODE,
> + QPHY_SW_RESET,
> + QPHY_START_CTRL,
> + QPHY_PCS_READY_STATUS,
> + QPHY_PCS_STATUS,
> + QPHY_PCS_AUTONOMOUS_MODE_CTRL,
> + QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
> + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
> + QPHY_PCS_POWER_DOWN_CONTROL,
> + /* PCS_MISC registers */
> + QPHY_PCS_MISC_TYPEC_CTRL,
> + /* Keep last to ensure regs_layout arrays are properly initialized */
> + QPHY_LAYOUT_SIZE
> +};
> +
> +static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = 0x00,
> + [QPHY_PCS_READY_STATUS] = 0x168,
> +};
> +
> +static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> +};
> +
> +static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_COM_SW_RESET] = 0x400,
> + [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
> + [QPHY_COM_START_CONTROL] = 0x408,
> + [QPHY_COM_PCS_READY_STATUS] = 0x448,
> + [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
> + [QPHY_FLL_CNTRL1] = 0xc4,
> + [QPHY_FLL_CNTRL2] = 0xc8,
> + [QPHY_FLL_CNT_VAL_L] = 0xcc,
> + [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
> + [QPHY_FLL_MAN_CODE] = 0xd4,
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x174,
> +};
> +
> +static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_FLL_CNTRL1] = 0xc0,
> + [QPHY_FLL_CNTRL2] = 0xc4,
> + [QPHY_FLL_CNT_VAL_L] = 0xc8,
> + [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
> + [QPHY_FLL_MAN_CODE] = 0xd0,
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x17c,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
> +};
> +
> +static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x174,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
> +};
> +
> +static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x174,
> +};
> +
> +static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x2ac,
> +};
> +
> +static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
> +};
> +
> +static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
> +};
> +
> +static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
> +};
> +
> +static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
> + [QPHY_PCS_STATUS] = 0x174,
> + [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
> +};
> +
> +static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = 0x00,
> + [QPHY_PCS_READY_STATUS] = 0x160,
> +};
> +
> +static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = 0x00,
> + [QPHY_PCS_READY_STATUS] = 0x168,
> +};
> +
> +static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> +};
> +
> +static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
> + [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
> + [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + /* PLL and Loop filter settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + /* SSC settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
> + QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
> +
> + QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
> +
> + QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
> + QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
> + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
> + /* PLL and Loop filter settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + /* SSC settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
> + /* FLL settings */
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
> +
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
> + QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
> + QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
> + QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
> + QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
> + QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
> + QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
> + QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> + QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
> + QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
> + QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
> + QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
> + QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
> + QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
> + QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
> + QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
> + QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
> + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
> + QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
> + QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
> + /* FLL settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> +
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
> + /* FLL settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> +
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
> + QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
> + QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
> + QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
> +
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> +
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
> +};
> +
> +/* Register names should be validated, they might be different for this PHY */
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
> +};
> +
> +struct qmp_phy;
> +
> +/* struct qmp_phy_cfg - per-PHY initialization config */
> +struct qmp_phy_cfg {
> + /* phy-type - PCIE/UFS/USB */
> + unsigned int type;
> + /* number of lanes provided by phy */
> + int nlanes;
> +
> + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
> + const struct qmp_phy_init_tbl *serdes_tbl;
> + int serdes_tbl_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_sec;
> + int serdes_tbl_num_sec;
> + const struct qmp_phy_init_tbl *tx_tbl;
> + int tx_tbl_num;
> + const struct qmp_phy_init_tbl *tx_tbl_sec;
> + int tx_tbl_num_sec;
> + const struct qmp_phy_init_tbl *rx_tbl;
> + int rx_tbl_num;
> + const struct qmp_phy_init_tbl *rx_tbl_sec;
> + int rx_tbl_num_sec;
> + const struct qmp_phy_init_tbl *pcs_tbl;
> + int pcs_tbl_num;
> + const struct qmp_phy_init_tbl *pcs_tbl_sec;
> + int pcs_tbl_num_sec;
> + const struct qmp_phy_init_tbl *pcs_misc_tbl;
> + int pcs_misc_tbl_num;
> + const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
> + int pcs_misc_tbl_num_sec;
> +
> + /* Init sequence for DP PHY block link rates */
> + const struct qmp_phy_init_tbl *serdes_tbl_rbr;
> + int serdes_tbl_rbr_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_hbr;
> + int serdes_tbl_hbr_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
> + int serdes_tbl_hbr2_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
> + int serdes_tbl_hbr3_num;
> +
> + /* DP PHY callbacks */
> + int (*configure_dp_phy)(struct qmp_phy *qphy);
> + void (*configure_dp_tx)(struct qmp_phy *qphy);
> + int (*calibrate_dp_phy)(struct qmp_phy *qphy);
> + void (*dp_aux_init)(struct qmp_phy *qphy);
> +
> + /* clock ids to be requested */
> + const char * const *clk_list;
> + int num_clks;
> + /* resets to be requested */
> + const char * const *reset_list;
> + int num_resets;
> + /* regulators to be requested */
> + const char * const *vreg_list;
> + int num_vregs;
> +
> + /* array of registers with different offsets */
> + const unsigned int *regs;
> +
> + unsigned int start_ctrl;
> + unsigned int pwrdn_ctrl;
> + unsigned int mask_com_pcs_ready;
> + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
> + unsigned int phy_status;
> +
> + /* true, if PHY has a separate PHY_COM control block */
> + bool has_phy_com_ctrl;
> + /* true, if PHY has a reset for individual lanes */
> + bool has_lane_rst;
> + /* true, if PHY needs delay after POWER_DOWN */
> + bool has_pwrdn_delay;
> + /* power_down delay in usec */
> + int pwrdn_delay_min;
> + int pwrdn_delay_max;
> +
> + /* true, if PHY has a separate DP_COM control block */
> + bool has_phy_dp_com_ctrl;
> + /* true, if PHY has secondary tx/rx lanes to be configured */
> + bool is_dual_lane_phy;
> +
> + /* true, if PCS block has no separate SW_RESET register */
> + bool no_pcs_sw_reset;
> +};
> +
> +struct qmp_phy_combo_cfg {
> + const struct qmp_phy_cfg *usb_cfg;
> + const struct qmp_phy_cfg *dp_cfg;
> +};
> +
> +/**
> + * struct qmp_phy - per-lane phy descriptor
> + *
> + * @phy: generic phy
> + * @cfg: phy specific configuration
> + * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
> + * @tx: iomapped memory space for lane's tx
> + * @rx: iomapped memory space for lane's rx
> + * @pcs: iomapped memory space for lane's pcs
> + * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
> + * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
> + * @pcs_misc: iomapped memory space for lane's pcs_misc
> + * @pipe_clk: pipe clock
> + * @index: lane index
> + * @qmp: QMP phy to which this lane belongs
> + * @lane_rst: lane's reset controller
> + * @mode: current PHY mode
> + * @dp_aux_cfg: Display port aux config
> + * @dp_opts: Display port optional config
> + * @dp_clks: Display port clocks
> + */
> +struct qmp_phy {
> + struct phy *phy;
> + const struct qmp_phy_cfg *cfg;
> + void __iomem *serdes;
> + void __iomem *tx;
> + void __iomem *rx;
> + void __iomem *pcs;
> + void __iomem *tx2;
> + void __iomem *rx2;
> + void __iomem *pcs_misc;
> + struct clk *pipe_clk;
> + unsigned int index;
> + struct qcom_qmp *qmp;
> + struct reset_control *lane_rst;
> + enum phy_mode mode;
> + unsigned int dp_aux_cfg;
> + struct phy_configure_opts_dp dp_opts;
> + struct qmp_phy_dp_clks *dp_clks;
> +};
> +
> +struct qmp_phy_dp_clks {
> + struct qmp_phy *qphy;
> + struct clk_hw dp_link_hw;
> + struct clk_hw dp_pixel_hw;
> +};
> +
> +/**
> + * struct qcom_qmp - structure holding QMP phy block attributes
> + *
> + * @dev: device
> + * @dp_com: iomapped memory space for phy's dp_com control block
> + *
> + * @clks: array of clocks required by phy
> + * @resets: array of resets required by phy
> + * @vregs: regulator supplies bulk data
> + *
> + * @phys: array of per-lane phy descriptors
> + * @phy_mutex: mutex lock for PHY common block initialization
> + * @init_count: phy common block initialization count
> + * @ufs_reset: optional UFS PHY reset handle
> + */
> +struct qcom_qmp {
> + struct device *dev;
> + void __iomem *dp_com;
> +
> + struct clk_bulk_data *clks;
> + struct reset_control **resets;
> + struct regulator_bulk_data *vregs;
> +
> + struct qmp_phy **phys;
> +
> + struct mutex phy_mutex;
> + int init_count;
> +
> + struct reset_control *ufs_reset;
> +};
> +
> +static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
> +static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
> +static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
> +static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
> +
> +static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
> +static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
> +static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
> +static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
> +
> +static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
> +{
> + u32 reg;
> +
> + reg = readl(base + offset);
> + reg |= val;
> + writel(reg, base + offset);
> +
> + /* ensure that above write is through */
> + readl(base + offset);
> +}
> +
> +static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
> +{
> + u32 reg;
> +
> + reg = readl(base + offset);
> + reg &= ~val;
> + writel(reg, base + offset);
> +
> + /* ensure that above write is through */
> + readl(base + offset);
> +}
> +
> +/* list of clocks required by phy */
> +static const char * const msm8996_phy_clk_l[] = {
> + "aux", "cfg_ahb", "ref",
> +};
> +
> +static const char * const msm8996_ufs_phy_clk_l[] = {
> + "ref",
> +};
> +
> +static const char * const qmp_v3_phy_clk_l[] = {
> + "aux", "cfg_ahb", "ref", "com_aux",
> +};
> +
> +static const char * const sdm845_pciephy_clk_l[] = {
> + "aux", "cfg_ahb", "ref", "refgen",
> +};
> +
> +static const char * const qmp_v4_phy_clk_l[] = {
> + "aux", "ref_clk_src", "ref", "com_aux",
> +};
> +
> +/* the primary usb3 phy on sm8250 doesn't have a ref clock */
> +static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
> + "aux", "ref_clk_src", "com_aux"
> +};
> +
> +static const char * const sm8450_ufs_phy_clk_l[] = {
> + "qref", "ref", "ref_aux",
> +};
> +
> +static const char * const sdm845_ufs_phy_clk_l[] = {
> + "ref", "ref_aux",
> +};
> +
> +/* usb3 phy on sdx55 doesn't have com_aux clock */
> +static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
> + "aux", "cfg_ahb", "ref"
> +};
> +
> +static const char * const qcm2290_usb3phy_clk_l[] = {
> + "cfg_ahb", "ref", "com_aux",
> +};
> +
> +/* list of resets */
> +static const char * const msm8996_pciephy_reset_l[] = {
> + "phy", "common", "cfg",
> +};
> +
> +static const char * const msm8996_usb3phy_reset_l[] = {
> + "phy", "common",
> +};
> +
> +static const char * const sc7180_usb3phy_reset_l[] = {
> + "phy",
> +};
> +
> +static const char * const qcm2290_usb3phy_reset_l[] = {
> + "phy_phy", "phy",
> +};
> +
> +static const char * const sdm845_pciephy_reset_l[] = {
> + "phy",
> +};
> +
> +/* list of regulators */
> +static const char * const qmp_phy_vreg_l[] = {
> + "vdda-phy", "vdda-pll",
> +};
> +
> +static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = ipq8074_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
> + .tx_tbl = msm8996_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
> + .rx_tbl = ipq8074_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
> + .pcs_tbl = ipq8074_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +};
> +
> +static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 3,
> +
> + .serdes_tbl = msm8996_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
> + .tx_tbl = msm8996_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
> + .rx_tbl = msm8996_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
> + .pcs_tbl = msm8996_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = pciephy_regs_layout,
> +
> + .start_ctrl = PCS_START | PLL_READY_GATE_EN,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .mask_com_pcs_ready = PCS_READY,
> + .phy_status = PHYSTATUS,
> +
> + .has_phy_com_ctrl = true,
> + .has_lane_rst = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg msm8996_ufs_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8996_ufs_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
> + .tx_tbl = msm8996_ufs_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
> + .rx_tbl = msm8996_ufs_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
> +
> + .clk_list = msm8996_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
> +
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> +
> + .regs = msm8996_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .no_pcs_sw_reset = true,
> +};
> +
> +static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8996_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
> + .tx_tbl = msm8996_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
> + .rx_tbl = msm8996_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
> + .pcs_tbl = msm8996_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +};
> +
> +static const char * const ipq8074_pciephy_clk_l[] = {
> + "aux", "cfg_ahb",
> +};
> +/* list of resets */
> +static const char * const ipq8074_pciephy_reset_l[] = {
> + "phy", "common",
> +};
> +
> +static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = ipq8074_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
> + .tx_tbl = ipq8074_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
> + .rx_tbl = ipq8074_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
> + .pcs_tbl = ipq8074_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
> + .clk_list = ipq8074_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
> + .reset_list = ipq8074_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
> + .vreg_list = NULL,
> + .num_vregs = 0,
> + .regs = pciephy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_phy_com_ctrl = false,
> + .has_lane_rst = false,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = ipq6018_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
> + .tx_tbl = ipq6018_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
> + .rx_tbl = ipq6018_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
> + .pcs_tbl = ipq6018_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
> + .clk_list = ipq8074_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
> + .reset_list = ipq8074_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
> + .vreg_list = NULL,
> + .num_vregs = 0,
> + .regs = ipq_pciephy_gen3_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> +
> + .has_phy_com_ctrl = false,
> + .has_lane_rst = false,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
> + .tx_tbl = sdm845_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
> + .rx_tbl = sdm845_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
> + .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
> + .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sdm845_qmp_pciephy_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
> + .tx_tbl = sdm845_qhp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
> + .rx_tbl = sdm845_qhp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
> + .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sdm845_qhp_pciephy_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
> + .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
> + .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
> + .tx_tbl = sm8250_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
> + .rx_tbl = sm8250_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
> + .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
> + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
> + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
> + .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
> + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
> + .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
> + .tx_tbl = sm8250_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
> + .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
> + .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
> + .rx_tbl = sm8250_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
> + .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
> + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
> + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
> + .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
> + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
> + .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
> + .tx_tbl = qmp_v3_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
> + .rx_tbl = qmp_v3_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
> + .pcs_tbl = qmp_v3_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
> + .tx_tbl = qmp_v3_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
> + .rx_tbl = qmp_v3_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
> + .pcs_tbl = qmp_v3_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = sc7180_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
> + .type = PHY_TYPE_DP,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_dp_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
> + .tx_tbl = qmp_v3_dp_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
> +
> + .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
> + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
> + .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
> + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
> + .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
> + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
> + .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
> + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
> +
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = sc7180_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +
> + .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
> + .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
> + .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
> + .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
> +};
> +
> +static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
> + .usb_cfg = &sc7180_usb3phy_cfg,
> + .dp_cfg = &sc7180_dpphy_cfg,
> +};
> +
> +static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
> + .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
> + .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
> + .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sdm845_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
> + .tx_tbl = sdm845_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
> + .rx_tbl = sdm845_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
> + .pcs_tbl = sdm845_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sdm845_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> + .no_pcs_sw_reset = true,
> +};
> +
> +static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm6115_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
> + .tx_tbl = sm6115_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
> + .rx_tbl = sm6115_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
> + .pcs_tbl = sm6115_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm6115_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> +
> + .is_dual_lane_phy = false,
> + .no_pcs_sw_reset = true,
> +};
> +
> +static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8998_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
> + .tx_tbl = msm8998_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
> + .rx_tbl = msm8998_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
> + .pcs_tbl = msm8998_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = ipq8074_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = pciephy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +};
> +
> +static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8998_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
> + .tx_tbl = msm8998_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
> + .rx_tbl = msm8998_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
> + .pcs_tbl = msm8998_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8150_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
> + .tx_tbl = sm8150_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
> + .rx_tbl = sm8150_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
> + .pcs_tbl = sm8150_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8150_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
> + .tx_tbl = sm8150_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
> + .rx_tbl = sm8150_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
> + .pcs_tbl = sm8150_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
> + .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
> + .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
> + .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
> + .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
> + .type = PHY_TYPE_DP,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v4_dp_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
> + .tx_tbl = qmp_v4_dp_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
> +
> + .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
> + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
> + .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
> + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
> + .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
> + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
> + .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
> + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
> +
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = sc7180_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +
> + .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
> + .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
> + .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
> + .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
> +};
> +
> +static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
> + .usb_cfg = &sm8150_usb3phy_cfg,
> + .dp_cfg = &sc8180x_dpphy_cfg,
> +};
> +
> +static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
> + .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
> + .tx_tbl = sm8250_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
> + .rx_tbl = sm8250_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
> + .pcs_tbl = sm8250_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
> + .clk_list = qmp_v4_sm8250_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
> + .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
> + .type = PHY_TYPE_DP,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v4_dp_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
> + .tx_tbl = qmp_v4_dp_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
> +
> + .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
> + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
> + .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
> + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
> + .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
> + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
> + .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
> + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
> +
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +
> + .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
> + .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
> + .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
> + .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
> +};
> +
> +static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
> + .usb_cfg = &sm8250_usb3phy_cfg,
> + .dp_cfg = &sm8250_dpphy_cfg,
> +};
> +
> +static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
> + .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_sdx55_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 2,
> +
> + .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
> + .tx_tbl = sdx55_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
> + .rx_tbl = sdx55_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
> + .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
> + .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS_4_20,
> +
> + .is_dual_lane_phy = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
> + .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_sdx55_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8350_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8350_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
> + .tx_tbl = sm8350_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
> + .rx_tbl = sm8350_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
> + .pcs_tbl = sm8350_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8150_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
> + .tx_tbl = sm8350_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
> + .rx_tbl = sm8350_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
> + .pcs_tbl = sm8350_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
> + .clk_list = qmp_v4_sm8250_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
> + .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8350_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8350_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
> + .tx_tbl = sm8350_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
> + .rx_tbl = sm8350_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
> + .pcs_tbl = sm8350_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
> + .clk_list = sm8450_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8150_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
> + .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
> + .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
> + .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
> + .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
> + .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
> + .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS_4_20,
> +
> + .is_dual_lane_phy = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qcm2290_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
> + .tx_tbl = qcm2290_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
> + .rx_tbl = qcm2290_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
> + .pcs_tbl = qcm2290_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
> + .clk_list = qcm2290_usb3phy_clk_l,
> + .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
> + .reset_list = qcm2290_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qcm2290_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static void qcom_qmp_phy_configure_lane(void __iomem *base,
> + const unsigned int *regs,
> + const struct qmp_phy_init_tbl tbl[],
> + int num,
> + u8 lane_mask)
> +{
> + int i;
> + const struct qmp_phy_init_tbl *t = tbl;
> +
> + if (!t)
> + return;
> +
> + for (i = 0; i < num; i++, t++) {
> + if (!(t->lane_mask & lane_mask))
> + continue;
> +
> + if (t->in_layout)
> + writel(t->val, base + regs[t->offset]);
> + else
> + writel(t->val, base + t->offset);
> + }
> +}
> +
> +static void qcom_qmp_phy_configure(void __iomem *base,
> + const unsigned int *regs,
> + const struct qmp_phy_init_tbl tbl[],
> + int num)
> +{
> + qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
> +}
> +
> +static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
> +{
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
> + int serdes_tbl_num = cfg->serdes_tbl_num;
> + int ret;
> +
> + qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
> + if (cfg->serdes_tbl_sec)
> + qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
> + cfg->serdes_tbl_num_sec);
> +
> + if (cfg->type == PHY_TYPE_DP) {
> + switch (dp_opts->link_rate) {
> + case 1620:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_rbr,
> + cfg->serdes_tbl_rbr_num);
> + break;
> + case 2700:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_hbr,
> + cfg->serdes_tbl_hbr_num);
> + break;
> + case 5400:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_hbr2,
> + cfg->serdes_tbl_hbr2_num);
> + break;
> + case 8100:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_hbr3,
> + cfg->serdes_tbl_hbr3_num);
> + break;
> + default:
> + /* Other link rates aren't supported */
> + return -EINVAL;
> + }
> + }
> +
> +
> + if (cfg->has_phy_com_ctrl) {
> + void __iomem *status;
> + unsigned int mask, val;
> +
> + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
> + SERDES_START | PCS_START);
> +
> + status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
> + mask = cfg->mask_com_pcs_ready;
> +
> + ret = readl_poll_timeout(status, val, (val & mask), 10,
> + PHY_INIT_COMPLETE_TIMEOUT);
> + if (ret) {
> + dev_err(qmp->dev,
> + "phy common block init timed-out\n");
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
> +{
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
> + qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + /* Turn on BIAS current for PHY/PLL */
> + writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
> + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
> + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
> +
> + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_LANE_0_1_PWRDN |
> + DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
> + DP_PHY_PD_CTL_DP_CLAMP_EN,
> + qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + writel(QSERDES_V3_COM_BIAS_EN |
> + QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
> + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
> + QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
> + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
> +
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
> + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> + writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
> + writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
> + writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
> + qphy->dp_aux_cfg = 0;
> +
> + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
> + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
> + PHY_AUX_REQ_ERR_MASK,
> + qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
> +}
> +
> +static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
> + { 0x00, 0x0c, 0x15, 0x1a },
> + { 0x02, 0x0e, 0x16, 0xff },
> + { 0x02, 0x11, 0xff, 0xff },
> + { 0x04, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
> + { 0x02, 0x12, 0x16, 0x1a },
> + { 0x09, 0x19, 0x1f, 0xff },
> + { 0x10, 0x1f, 0xff, 0xff },
> + { 0x1f, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
> + { 0x00, 0x0c, 0x14, 0x19 },
> + { 0x00, 0x0b, 0x12, 0xff },
> + { 0x00, 0x0b, 0xff, 0xff },
> + { 0x04, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
> + { 0x08, 0x0f, 0x16, 0x1f },
> + { 0x11, 0x1e, 0x1f, 0xff },
> + { 0x19, 0x1f, 0xff, 0xff },
> + { 0x1f, 0xff, 0xff, 0xff }
> +};
> +
> +static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
> + unsigned int drv_lvl_reg, unsigned int emp_post_reg)
> +{
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + unsigned int v_level = 0, p_level = 0;
> + u8 voltage_swing_cfg, pre_emphasis_cfg;
> + int i;
> +
> + for (i = 0; i < dp_opts->lanes; i++) {
> + v_level = max(v_level, dp_opts->voltage[i]);
> + p_level = max(p_level, dp_opts->pre[i]);
> + }
> +
> + if (dp_opts->link_rate <= 2700) {
> + voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
> + pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
> + } else {
> + voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
> + pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
> + }
> +
> + /* TODO: Move check to config check */
> + if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
> + return -EINVAL;
> +
> + /* Enable MUX to use Cursor values from these registers */
> + voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
> + pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
> +
> + writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
> + writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
> + writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
> + writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
> +{
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + u32 bias_en, drvr_en;
> +
> + if (qcom_qmp_phy_configure_dp_swing(qphy,
> + QSERDES_V3_TX_TX_DRV_LVL,
> + QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
> + return;
> +
> + if (dp_opts->lanes == 1) {
> + bias_en = 0x3e;
> + drvr_en = 0x13;
> + } else {
> + bias_en = 0x3f;
> + drvr_en = 0x10;
> + }
> +
> + writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
> + writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
> + writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
> + writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
> +}
> +
> +static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
> +{
> + u32 val;
> + bool reverse = false;
> +
> + val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
> +
> + /*
> + * TODO: Assume orientation is CC1 for now and two lanes, need to
> + * use type-c connector to understand orientation and lanes.
> + *
> + * Otherwise val changes to be like below if this code understood
> + * the orientation of the type-c cable.
> + *
> + * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
> + * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
> + * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
> + * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
> + * if (orientation == ORIENTATION_CC2)
> + * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
> + */
> + val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
> + writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
> +
> + return reverse;
> +}
> +
> +static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + u32 phy_vco_div, status;
> + unsigned long pixel_freq;
> +
> + qcom_qmp_phy_configure_dp_mode(qphy);
> +
> + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
> + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + phy_vco_div = 0x1;
> + pixel_freq = 1620000000UL / 2;
> + break;
> + case 2700:
> + phy_vco_div = 0x1;
> + pixel_freq = 2700000000UL / 2;
> + break;
> + case 5400:
> + phy_vco_div = 0x2;
> + pixel_freq = 5400000000UL / 4;
> + break;
> + case 8100:
> + phy_vco_div = 0x0;
> + pixel_freq = 8100000000UL / 6;
> + break;
> + default:
> + /* Other link rates aren't supported */
> + return -EINVAL;
> + }
> + writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
> +
> + clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
> + clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
> +
> + writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
> + udelay(2000);
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000);
> +}
> +
> +/*
> + * We need to calibrate the aux setting here as many times
> + * as the caller tries
> + */
> +static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
> +{
> + static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
> + u8 val;
> +
> + qphy->dp_aux_cfg++;
> + qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
> + val = cfg1_settings[qphy->dp_aux_cfg];
> +
> + writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
> +{
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
> + qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + /* Turn on BIAS current for PHY/PLL */
> + writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
> +
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
> + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> + writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
> + writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
> + writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
> + qphy->dp_aux_cfg = 0;
> +
> + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
> + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
> + PHY_AUX_REQ_ERR_MASK,
> + qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
> +}
> +
> +static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
> +{
> + /* Program default values before writing proper values */
> + writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
> + writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
> +
> + writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> + writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> +
> + qcom_qmp_phy_configure_dp_swing(qphy,
> + QSERDES_V4_TX_TX_DRV_LVL,
> + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> +}
> +
> +static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + u32 phy_vco_div, status;
> + unsigned long pixel_freq;
> + u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
> + bool reverse;
> +
> + writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
> +
> + reverse = qcom_qmp_phy_configure_dp_mode(qphy);
> +
> + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> + writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> +
> + writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
> + writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + phy_vco_div = 0x1;
> + pixel_freq = 1620000000UL / 2;
> + break;
> + case 2700:
> + phy_vco_div = 0x1;
> + pixel_freq = 2700000000UL / 2;
> + break;
> + case 5400:
> + phy_vco_div = 0x2;
> + pixel_freq = 5400000000UL / 4;
> + break;
> + case 8100:
> + phy_vco_div = 0x0;
> + pixel_freq = 8100000000UL / 6;
> + break;
> + default:
> + /* Other link rates aren't supported */
> + return -EINVAL;
> + }
> + writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
> +
> + clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
> + clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
> +
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + /*
> + * At least for 7nm DP PHY this has to be done after enabling link
> + * clock.
> + */
> +
> + if (dp_opts->lanes == 1) {
> + bias0_en = reverse ? 0x3e : 0x15;
> + bias1_en = reverse ? 0x15 : 0x3e;
> + drvr0_en = reverse ? 0x13 : 0x10;
> + drvr1_en = reverse ? 0x10 : 0x13;
> + } else if (dp_opts->lanes == 2) {
> + bias0_en = reverse ? 0x3f : 0x15;
> + bias1_en = reverse ? 0x15 : 0x3f;
> + drvr0_en = 0x10;
> + drvr1_en = 0x10;
> + } else {
> + bias0_en = 0x3f;
> + bias1_en = 0x3f;
> + drvr0_en = 0x10;
> + drvr1_en = 0x10;
> + }
> +
> + writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
> + writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
> + writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
> + writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
> +
> + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
> + udelay(2000);
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
> + writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
> +
> + writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
> + writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
> +
> + writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> + writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> +
> + return 0;
> +}
> +
> +/*
> + * We need to calibrate the aux setting here as many times
> + * as the caller tries
> + */
> +static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
> +{
> + static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
> + u8 val;
> +
> + qphy->dp_aux_cfg++;
> + qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
> + val = cfg1_settings[qphy->dp_aux_cfg];
> +
> + writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
> +{
> + const struct phy_configure_opts_dp *dp_opts = &opts->dp;
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
> + if (qphy->dp_opts.set_voltages) {
> + cfg->configure_dp_tx(qphy);
> + qphy->dp_opts.set_voltages = 0;
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + if (cfg->calibrate_dp_phy)
> + return cfg->calibrate_dp_phy(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
> +{
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *dp_com = qmp->dp_com;
> + int ret, i;
> +
> + mutex_lock(&qmp->phy_mutex);
> + if (qmp->init_count++) {
> + mutex_unlock(&qmp->phy_mutex);
> + return 0;
> + }
> +
> + /* turn on regulator supplies */
> + ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
> + if (ret) {
> + dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
> + goto err_unlock;
> + }
> +
> + for (i = 0; i < cfg->num_resets; i++) {
> + ret = reset_control_assert(qmp->resets[i]);
> + if (ret) {
> + dev_err(qmp->dev, "%s reset assert failed\n",
> + cfg->reset_list[i]);
> + goto err_disable_regulators;
> + }
> + }
> +
> + for (i = cfg->num_resets - 1; i >= 0; i--) {
> + ret = reset_control_deassert(qmp->resets[i]);
> + if (ret) {
> + dev_err(qmp->dev, "%s reset deassert failed\n",
> + qphy->cfg->reset_list[i]);
> + goto err_assert_reset;
> + }
> + }
> +
> + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
> + if (ret)
> + goto err_assert_reset;
> +
> + if (cfg->has_phy_dp_com_ctrl) {
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
> + SW_PWRDN);
> + /* override hardware control for reset of qmp phy */
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
> + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
> + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
> +
> + /* Default type-c orientation, i.e CC1 */
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
> +
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
> + USB3_MODE | DP_MODE);
> +
> + /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
> + qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
> + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
> + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
> +
> + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
> + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
> + }
> +
> + if (cfg->has_phy_com_ctrl) {
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
> + SW_PWRDN);
> + } else {
> + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
> + qphy_setbits(pcs,
> + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
> + cfg->pwrdn_ctrl);
> + else
> + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
> + cfg->pwrdn_ctrl);
> + }
> +
> + mutex_unlock(&qmp->phy_mutex);
> +
> + return 0;
> +
> +err_assert_reset:
> + while (++i < cfg->num_resets)
> + reset_control_assert(qmp->resets[i]);
> +err_disable_regulators:
> + regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
> +err_unlock:
> + mutex_unlock(&qmp->phy_mutex);
> +
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
> +{
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + int i = cfg->num_resets;
> +
> + mutex_lock(&qmp->phy_mutex);
> + if (--qmp->init_count) {
> + mutex_unlock(&qmp->phy_mutex);
> + return 0;
> + }
> +
> + reset_control_assert(qmp->ufs_reset);
> + if (cfg->has_phy_com_ctrl) {
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
> + SERDES_START | PCS_START);
> + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
> + SW_RESET);
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
> + SW_PWRDN);
> + }
> +
> + while (--i >= 0)
> + reset_control_assert(qmp->resets[i]);
> +
> + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
> +
> + regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
> +
> + mutex_unlock(&qmp->phy_mutex);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_init(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + int ret;
> + dev_vdbg(qmp->dev, "Initializing QMP phy\n");
> +
> + if (cfg->no_pcs_sw_reset) {
> + /*
> + * Get UFS reset, which is delayed until now to avoid a
> + * circular dependency where UFS needs its PHY, but the PHY
> + * needs this UFS reset.
> + */
> + if (!qmp->ufs_reset) {
> + qmp->ufs_reset =
> + devm_reset_control_get_exclusive(qmp->dev,
> + "ufsphy");
> +
> + if (IS_ERR(qmp->ufs_reset)) {
> + ret = PTR_ERR(qmp->ufs_reset);
> + dev_err(qmp->dev,
> + "failed to get UFS reset: %d\n",
> + ret);
> +
> + qmp->ufs_reset = NULL;
> + return ret;
> + }
> + }
> +
> + ret = reset_control_assert(qmp->ufs_reset);
> + if (ret)
> + return ret;
> + }
> +
> + ret = qcom_qmp_phy_com_init(qphy);
> + if (ret)
> + return ret;
> +
> + if (cfg->type == PHY_TYPE_DP)
> + cfg->dp_aux_init(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_power_on(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *tx = qphy->tx;
> + void __iomem *rx = qphy->rx;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *pcs_misc = qphy->pcs_misc;
> + void __iomem *status;
> + unsigned int mask, val, ready;
> + int ret;
> +
> + qcom_qmp_phy_serdes_init(qphy);
> +
> + if (cfg->has_lane_rst) {
> + ret = reset_control_deassert(qphy->lane_rst);
> + if (ret) {
> + dev_err(qmp->dev, "lane%d reset deassert failed\n",
> + qphy->index);
> + return ret;
> + }
> + }
> +
> + ret = clk_prepare_enable(qphy->pipe_clk);
> + if (ret) {
> + dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
> + goto err_reset_lane;
> + }
> +
> + /* Tx, Rx, and PCS configurations */
> + qcom_qmp_phy_configure_lane(tx, cfg->regs,
> + cfg->tx_tbl, cfg->tx_tbl_num, 1);
> + if (cfg->tx_tbl_sec)
> + qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
> + cfg->tx_tbl_num_sec, 1);
> +
> + /* Configuration for other LANE for USB-DP combo PHY */
> + if (cfg->is_dual_lane_phy) {
> + qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
> + cfg->tx_tbl, cfg->tx_tbl_num, 2);
> + if (cfg->tx_tbl_sec)
> + qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
> + cfg->tx_tbl_sec,
> + cfg->tx_tbl_num_sec, 2);
> + }
> +
> + /* Configure special DP tx tunings */
> + if (cfg->type == PHY_TYPE_DP)
> + cfg->configure_dp_tx(qphy);
> +
> + qcom_qmp_phy_configure_lane(rx, cfg->regs,
> + cfg->rx_tbl, cfg->rx_tbl_num, 1);
> + if (cfg->rx_tbl_sec)
> + qcom_qmp_phy_configure_lane(rx, cfg->regs,
> + cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
> +
> + if (cfg->is_dual_lane_phy) {
> + qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
> + cfg->rx_tbl, cfg->rx_tbl_num, 2);
> + if (cfg->rx_tbl_sec)
> + qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
> + cfg->rx_tbl_sec,
> + cfg->rx_tbl_num_sec, 2);
> + }
> +
> + /* Configure link rate, swing, etc. */
> + if (cfg->type == PHY_TYPE_DP) {
> + cfg->configure_dp_phy(qphy);
> + } else {
> + qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
> + if (cfg->pcs_tbl_sec)
> + qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
> + cfg->pcs_tbl_num_sec);
> + }
> +
> + ret = reset_control_deassert(qmp->ufs_reset);
> + if (ret)
> + goto err_disable_pipe_clk;
> +
> + qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
> + cfg->pcs_misc_tbl_num);
> + if (cfg->pcs_misc_tbl_sec)
> + qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
> + cfg->pcs_misc_tbl_num_sec);
> +
> + /*
> + * Pull out PHY from POWER DOWN state.
> + * This is active low enable signal to power-down PHY.
> + */
> + if(cfg->type == PHY_TYPE_PCIE)
> + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
> +
> + if (cfg->has_pwrdn_delay)
> + usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
> +
> + if (cfg->type != PHY_TYPE_DP) {
> + /* Pull PHY out of reset state */
> + if (!cfg->no_pcs_sw_reset)
> + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
> + /* start SerDes and Phy-Coding-Sublayer */
> + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
> +
> + if (cfg->type == PHY_TYPE_UFS) {
> + status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
> + mask = PCS_READY;
> + ready = PCS_READY;
> + } else {
> + status = pcs + cfg->regs[QPHY_PCS_STATUS];
> + mask = cfg->phy_status;
> + ready = 0;
> + }
> +
> + ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
> + PHY_INIT_COMPLETE_TIMEOUT);
> + if (ret) {
> + dev_err(qmp->dev, "phy initialization timed-out\n");
> + goto err_disable_pipe_clk;
> + }
> + }
> + return 0;
> +
> +err_disable_pipe_clk:
> + clk_disable_unprepare(qphy->pipe_clk);
> +err_reset_lane:
> + if (cfg->has_lane_rst)
> + reset_control_assert(qphy->lane_rst);
> +
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_power_off(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + clk_disable_unprepare(qphy->pipe_clk);
> +
> + if (cfg->type == PHY_TYPE_DP) {
> + /* Assert DP PHY power down */
> + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> + } else {
> + /* PHY reset */
> + if (!cfg->no_pcs_sw_reset)
> + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
> +
> + /* stop SerDes and Phy-Coding-Sublayer */
> + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
> +
> + /* Put PHY into POWER DOWN state: active low */
> + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
> + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
> + cfg->pwrdn_ctrl);
> + } else {
> + qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
> + cfg->pwrdn_ctrl);
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_exit(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + if (cfg->has_lane_rst)
> + reset_control_assert(qphy->lane_rst);
> +
> + qcom_qmp_phy_com_exit(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_enable(struct phy *phy)
> +{
> + int ret;
> +
> + ret = qcom_qmp_phy_init(phy);
> + if (ret)
> + return ret;
> +
> + ret = qcom_qmp_phy_power_on(phy);
> + if (ret)
> + qcom_qmp_phy_exit(phy);
> +
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_disable(struct phy *phy)
> +{
> + int ret;
> +
> + ret = qcom_qmp_phy_power_off(phy);
> + if (ret)
> + return ret;
> + return qcom_qmp_phy_exit(phy);
> +}
> +
> +static int qcom_qmp_phy_set_mode(struct phy *phy,
> + enum phy_mode mode, int submode)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> +
> + qphy->mode = mode;
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *pcs_misc = qphy->pcs_misc;
> + u32 intr_mask;
> +
> + if (qphy->mode == PHY_MODE_USB_HOST_SS ||
> + qphy->mode == PHY_MODE_USB_DEVICE_SS)
> + intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
> + else
> + intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
> +
> + /* Clear any pending interrupts status */
> + qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> + /* Writing 1 followed by 0 clears the interrupt */
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> +
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
> + ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
> +
> + /* Enable required PHY autonomous mode interrupts */
> + qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
> +
> + /* Enable i/o clamp_n for autonomous mode */
> + if (pcs_misc)
> + qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
> +}
> +
> +static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *pcs_misc = qphy->pcs_misc;
> +
> + /* Disable i/o clamp_n on resume for normal mode */
> + if (pcs_misc)
> + qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
> +
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
> + ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
> +
> + qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> + /* Writing 1 followed by 0 clears the interrupt */
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> +}
> +
> +static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + struct qmp_phy *qphy = qmp->phys[0];
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
> +
> + /* Supported only for USB3 PHY and luckily USB3 is the first phy */
> + if (cfg->type != PHY_TYPE_USB3)
> + return 0;
> +
> + if (!qmp->init_count) {
> + dev_vdbg(dev, "PHY not initialized, bailing out\n");
> + return 0;
> + }
> +
> + qcom_qmp_phy_enable_autonomous_mode(qphy);
> +
> + clk_disable_unprepare(qphy->pipe_clk);
> + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
> +
> + return 0;
> +}
> +
> +static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + struct qmp_phy *qphy = qmp->phys[0];
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + int ret = 0;
> +
> + dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
> +
> + /* Supported only for USB3 PHY and luckily USB3 is the first phy */
> + if (cfg->type != PHY_TYPE_USB3)
> + return 0;
> +
> + if (!qmp->init_count) {
> + dev_vdbg(dev, "PHY not initialized, bailing out\n");
> + return 0;
> + }
> +
> + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(qphy->pipe_clk);
> + if (ret) {
> + dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
> + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
> + return ret;
> + }
> +
> + qcom_qmp_phy_disable_autonomous_mode(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + int num = cfg->num_vregs;
> + int i;
> +
> + qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
> + if (!qmp->vregs)
> + return -ENOMEM;
> +
> + for (i = 0; i < num; i++)
> + qmp->vregs[i].supply = cfg->vreg_list[i];
> +
> + return devm_regulator_bulk_get(dev, num, qmp->vregs);
> +}
> +
> +static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + int i;
> +
> + qmp->resets = devm_kcalloc(dev, cfg->num_resets,
> + sizeof(*qmp->resets), GFP_KERNEL);
> + if (!qmp->resets)
> + return -ENOMEM;
> +
> + for (i = 0; i < cfg->num_resets; i++) {
> + struct reset_control *rst;
> + const char *name = cfg->reset_list[i];
> +
> + rst = devm_reset_control_get_exclusive(dev, name);
> + if (IS_ERR(rst)) {
> + dev_err(dev, "failed to get %s reset\n", name);
> + return PTR_ERR(rst);
> + }
> + qmp->resets[i] = rst;
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + int num = cfg->num_clks;
> + int i;
> +
> + qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
> + if (!qmp->clks)
> + return -ENOMEM;
> +
> + for (i = 0; i < num; i++)
> + qmp->clks[i].id = cfg->clk_list[i];
> +
> + return devm_clk_bulk_get(dev, num, qmp->clks);
> +}
> +
> +static void phy_clk_release_provider(void *res)
> +{
> + of_clk_del_provider(res);
> +}
> +
> +/*
> + * Register a fixed rate pipe clock.
> + *
> + * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
> + * controls it. The <s>_pipe_clk coming out of the GCC is requested
> + * by the PHY driver for its operations.
> + * We register the <s>_pipe_clksrc here. The gcc driver takes care
> + * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
> + * Below picture shows this relationship.
> + *
> + * +---------------+
> + * | PHY block |<<---------------------------------------+
> + * | | |
> + * | +-------+ | +-----+ |
> + * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
> + * clk | +-------+ | +-----+
> + * +---------------+
> + */
> +static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
> +{
> + struct clk_fixed_rate *fixed;
> + struct clk_init_data init = { };
> + int ret;
> +
> + ret = of_property_read_string(np, "clock-output-names", &init.name);
> + if (ret) {
> + dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
> + return ret;
> + }
> +
> + fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
> + if (!fixed)
> + return -ENOMEM;
> +
> + init.ops = &clk_fixed_rate_ops;
> +
> + /* controllers using QMP phys use 125MHz pipe clock interface */
> + fixed->fixed_rate = 125000000;
> + fixed->hw.init = &init;
> +
> + ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
> + if (ret)
> + return ret;
> +
> + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
> + if (ret)
> + return ret;
> +
> + /*
> + * Roll a devm action because the clock provider is the child node, but
> + * the child node is not actually a device.
> + */
> + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
> +}
> +
> +/*
> + * Display Port PLL driver block diagram for branch clocks
> + *
> + * +------------------------------+
> + * | DP_VCO_CLK |
> + * | |
> + * | +-------------------+ |
> + * | | (DP PLL/VCO) | |
> + * | +---------+---------+ |
> + * | v |
> + * | +----------+-----------+ |
> + * | | hsclk_divsel_clk_src | |
> + * | +----------+-----------+ |
> + * +------------------------------+
> + * |
> + * +---------<---------v------------>----------+
> + * | |
> + * +--------v----------------+ |
> + * | dp_phy_pll_link_clk | |
> + * | link_clk | |
> + * +--------+----------------+ |
> + * | |
> + * | |
> + * v v
> + * Input to DISPCC block |
> + * for link clk, crypto clk |
> + * and interface clock |
> + * |
> + * |
> + * +--------<------------+-----------------+---<---+
> + * | | |
> + * +----v---------+ +--------v-----+ +--------v------+
> + * | vco_divided | | vco_divided | | vco_divided |
> + * | _clk_src | | _clk_src | | _clk_src |
> + * | | | | | |
> + * |divsel_six | | divsel_two | | divsel_four |
> + * +-------+------+ +-----+--------+ +--------+------+
> + * | | |
> + * v---->----------v-------------<------v
> + * |
> + * +----------+-----------------+
> + * | dp_phy_pll_vco_div_clk |
> + * +---------+------------------+
> + * |
> + * v
> + * Input to DISPCC block
> + * for DP pixel clock
> + *
> + */
> +static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + switch (req->rate) {
> + case 1620000000UL / 2:
> + case 2700000000UL / 2:
> + /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
> + return 0;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static unsigned long
> +qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + const struct qmp_phy_dp_clks *dp_clks;
> + const struct qmp_phy *qphy;
> + const struct phy_configure_opts_dp *dp_opts;
> +
> + dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
> + qphy = dp_clks->qphy;
> + dp_opts = &qphy->dp_opts;
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + return 1620000000UL / 2;
> + case 2700:
> + return 2700000000UL / 2;
> + case 5400:
> + return 5400000000UL / 4;
> + case 8100:
> + return 8100000000UL / 6;
> + default:
> + return 0;
> + }
> +}
> +
> +static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
> + .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
> + .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
> +};
> +
> +static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + switch (req->rate) {
> + case 162000000:
> + case 270000000:
> + case 540000000:
> + case 810000000:
> + return 0;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static unsigned long
> +qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + const struct qmp_phy_dp_clks *dp_clks;
> + const struct qmp_phy *qphy;
> + const struct phy_configure_opts_dp *dp_opts;
> +
> + dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
> + qphy = dp_clks->qphy;
> + dp_opts = &qphy->dp_opts;
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + case 2700:
> + case 5400:
> + case 8100:
> + return dp_opts->link_rate * 100000;
> + default:
> + return 0;
> + }
> +}
> +
> +static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
> + .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
> + .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
> +};
> +
> +static struct clk_hw *
> +qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
> +{
> + struct qmp_phy_dp_clks *dp_clks = data;
> + unsigned int idx = clkspec->args[0];
> +
> + if (idx >= 2) {
> + pr_err("%s: invalid index %u\n", __func__, idx);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + if (idx == 0)
> + return &dp_clks->dp_link_hw;
> +
> + return &dp_clks->dp_pixel_hw;
> +}
> +
> +static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
> + struct device_node *np)
> +{
> + struct clk_init_data init = { };
> + struct qmp_phy_dp_clks *dp_clks;
> + char name[64];
> + int ret;
> +
> + dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
> + if (!dp_clks)
> + return -ENOMEM;
> +
> + dp_clks->qphy = qphy;
> + qphy->dp_clks = dp_clks;
> +
> + snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
> + init.ops = &qcom_qmp_dp_link_clk_ops;
> + init.name = name;
> + dp_clks->dp_link_hw.init = &init;
> + ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
> + if (ret)
> + return ret;
> +
> + snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
> + init.ops = &qcom_qmp_dp_pixel_clk_ops;
> + init.name = name;
> + dp_clks->dp_pixel_hw.init = &init;
> + ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
> + if (ret)
> + return ret;
> +
> + ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
> + if (ret)
> + return ret;
> +
> + /*
> + * Roll a devm action because the clock provider is the child node, but
> + * the child node is not actually a device.
> + */
> + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
> +}
> +
> +static const struct phy_ops qcom_qmp_phy_gen_ops = {
> + .init = qcom_qmp_phy_enable,
> + .exit = qcom_qmp_phy_disable,
> + .set_mode = qcom_qmp_phy_set_mode,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct phy_ops qcom_qmp_phy_dp_ops = {
> + .init = qcom_qmp_phy_init,
> + .configure = qcom_qmp_dp_phy_configure,
> + .power_on = qcom_qmp_phy_power_on,
> + .calibrate = qcom_qmp_dp_phy_calibrate,
> + .power_off = qcom_qmp_phy_power_off,
> + .exit = qcom_qmp_phy_exit,
> + .set_mode = qcom_qmp_phy_set_mode,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
> + .power_on = qcom_qmp_phy_enable,
> + .power_off = qcom_qmp_phy_disable,
> + .set_mode = qcom_qmp_phy_set_mode,
> + .owner = THIS_MODULE,
> +};
> +
> +static void qcom_qmp_reset_control_put(void *data)
> +{
> + reset_control_put(data);
> +}
> +
> +static
> +int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
> + void __iomem *serdes, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + struct phy *generic_phy;
> + struct qmp_phy *qphy;
> + const struct phy_ops *ops;
> + char prop_name[MAX_PROP_NAME];
> + int ret;
> +
> + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
> + if (!qphy)
> + return -ENOMEM;
> +
> + qphy->cfg = cfg;
> + qphy->serdes = serdes;
> + /*
> + * Get memory resources for each phy lane:
> + * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
> + * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
> + * For single lane PHYs: pcs_misc (optional) -> 3.
> + */
> + qphy->tx = of_iomap(np, 0);
> + if (!qphy->tx)
> + return -ENOMEM;
> +
> + qphy->rx = of_iomap(np, 1);
> + if (!qphy->rx)
> + return -ENOMEM;
> +
> + qphy->pcs = of_iomap(np, 2);
> + if (!qphy->pcs)
> + return -ENOMEM;
> +
> + /*
> + * If this is a dual-lane PHY, then there should be registers for the
> + * second lane. Some old device trees did not specify this, so fall
> + * back to old legacy behavior of assuming they can be reached at an
> + * offset from the first lane.
> + */
> + if (cfg->is_dual_lane_phy) {
> + qphy->tx2 = of_iomap(np, 3);
> + qphy->rx2 = of_iomap(np, 4);
> + if (!qphy->tx2 || !qphy->rx2) {
> + dev_warn(dev,
> + "Underspecified device tree, falling back to legacy register regions\n");
> +
> + /* In the old version, pcs_misc is at index 3. */
> + qphy->pcs_misc = qphy->tx2;
> + qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
> + qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
> +
> + } else {
> + qphy->pcs_misc = of_iomap(np, 5);
> + }
> +
> + } else {
> + qphy->pcs_misc = of_iomap(np, 3);
> + }
> +
> + if (!qphy->pcs_misc)
> + dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
> +
> + /*
> + * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
> + * based phys, so they essentially have pipe clock. So,
> + * we return error in case phy is USB3 or PIPE type.
> + * Otherwise, we initialize pipe clock to NULL for
> + * all phys that don't need this.
> + */
> + snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
> + qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
> + if (IS_ERR(qphy->pipe_clk)) {
> + if (cfg->type == PHY_TYPE_PCIE ||
> + cfg->type == PHY_TYPE_USB3) {
> + ret = PTR_ERR(qphy->pipe_clk);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev,
> + "failed to get lane%d pipe_clk, %d\n",
> + id, ret);
> + return ret;
> + }
> + qphy->pipe_clk = NULL;
> + }
> +
> + /* Get lane reset, if any */
> + if (cfg->has_lane_rst) {
> + snprintf(prop_name, sizeof(prop_name), "lane%d", id);
> + qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
> + if (IS_ERR(qphy->lane_rst)) {
> + dev_err(dev, "failed to get lane%d reset\n", id);
> + return PTR_ERR(qphy->lane_rst);
> + }
> + ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
> + qphy->lane_rst);
> + if (ret)
> + return ret;
> + }
> +
> + if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
> + ops = &qcom_qmp_pcie_ufs_ops;
> + else if (cfg->type == PHY_TYPE_DP)
> + ops = &qcom_qmp_phy_dp_ops;
> + else
> + ops = &qcom_qmp_phy_gen_ops;
> +
> + generic_phy = devm_phy_create(dev, np, ops);
> + if (IS_ERR(generic_phy)) {
> + ret = PTR_ERR(generic_phy);
> + dev_err(dev, "failed to create qphy %d\n", ret);
> + return ret;
> + }
> +
> + qphy->phy = generic_phy;
> + qphy->index = id;
> + qphy->qmp = qmp;
> + qmp->phys[id] = qphy;
> + phy_set_drvdata(generic_phy, qphy);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
> + {
> + .compatible = "qcom,ipq8074-qmp-usb3-phy",
> + .data = &ipq8074_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,msm8996-qmp-pcie-phy",
> + .data = &msm8996_pciephy_cfg,
> + }, {
> + .compatible = "qcom,msm8996-qmp-ufs-phy",
> + .data = &msm8996_ufs_cfg,
> + }, {
> + .compatible = "qcom,msm8996-qmp-usb3-phy",
> + .data = &msm8996_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,msm8998-qmp-pcie-phy",
> + .data = &msm8998_pciephy_cfg,
> + }, {
> + .compatible = "qcom,msm8998-qmp-ufs-phy",
> + .data = &sdm845_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,ipq8074-qmp-pcie-phy",
> + .data = &ipq8074_pciephy_cfg,
> + }, {
> + .compatible = "qcom,ipq6018-qmp-pcie-phy",
> + .data = &ipq6018_pciephy_cfg,
> + }, {
> + .compatible = "qcom,ipq6018-qmp-usb3-phy",
> + .data = &ipq8074_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sc7180-qmp-usb3-phy",
> + .data = &sc7180_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
> + /* It's a combo phy */
> + }, {
> + .compatible = "qcom,sc8180x-qmp-pcie-phy",
> + .data = &sc8180x_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sc8180x-qmp-ufs-phy",
> + .data = &sm8150_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sc8280xp-qmp-ufs-phy",
> + .data = &sm8350_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sc8180x-qmp-usb3-phy",
> + .data = &sm8150_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
> + /* It's a combo phy */
> + }, {
> + .compatible = "qcom,sdm845-qhp-pcie-phy",
> + .data = &sdm845_qhp_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-pcie-phy",
> + .data = &sdm845_qmp_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-usb3-phy",
> + .data = &qmp_v3_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
> + .data = &qmp_v3_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-ufs-phy",
> + .data = &sdm845_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,msm8998-qmp-usb3-phy",
> + .data = &msm8998_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm6115-qmp-ufs-phy",
> + .data = &sm6115_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm6350-qmp-ufs-phy",
> + .data = &sdm845_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8150-qmp-ufs-phy",
> + .data = &sm8150_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-ufs-phy",
> + .data = &sm8150_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8150-qmp-usb3-phy",
> + .data = &sm8150_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
> + .data = &sm8150_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-usb3-phy",
> + .data = &sm8250_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
> + /* It's a combo phy */
> + }, {
> + .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
> + .data = &sm8250_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
> + .data = &sm8250_qmp_gen3x1_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
> + .data = &sm8250_qmp_gen3x2_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8350-qmp-ufs-phy",
> + .data = &sm8350_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
> + .data = &sm8250_qmp_gen3x2_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdx55-qmp-pcie-phy",
> + .data = &sdx55_qmp_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
> + .data = &sdx55_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
> + .data = &sdx65_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8350-qmp-usb3-phy",
> + .data = &sm8350_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
> + .data = &sm8350_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
> + .data = &sm8450_qmp_gen3x1_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
> + .data = &sm8450_qmp_gen4x2_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-ufs-phy",
> + .data = &sm8450_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-usb3-phy",
> + .data = &sm8350_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,qcm2290-qmp-usb3-phy",
> + .data = &qcm2290_usb3phy_cfg,
> + },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
> +
> +static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
> + {
> + .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
> + .data = &sc7180_usb3dpphy_cfg,
> + },
> + {
> + .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
> + .data = &sm8250_usb3dpphy_cfg,
> + },
> + {
> + .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
> + .data = &sc8180x_usb3dpphy_cfg,
> + },
> + { }
> +};
> +
> +static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
> + SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
> + qcom_qmp_phy_runtime_resume, NULL)
> +};
> +
> +static int qcom_qmp_phy_probe(struct platform_device *pdev)
> +{
> + struct qcom_qmp *qmp;
> + struct device *dev = &pdev->dev;
> + struct device_node *child;
> + struct phy_provider *phy_provider;
> + void __iomem *serdes;
> + void __iomem *usb_serdes;
> + void __iomem *dp_serdes = NULL;
> + const struct qmp_phy_combo_cfg *combo_cfg = NULL;
> + const struct qmp_phy_cfg *cfg = NULL;
> + const struct qmp_phy_cfg *usb_cfg = NULL;
> + const struct qmp_phy_cfg *dp_cfg = NULL;
> + int num, id, expected_phys;
> + int ret;
> +
> + qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
> + if (!qmp)
> + return -ENOMEM;
> +
> + qmp->dev = dev;
> + dev_set_drvdata(dev, qmp);
> +
> + /* Get the specific init parameters of QMP phy */
> + cfg = of_device_get_match_data(dev);
> + if (!cfg) {
> + const struct of_device_id *match;
> +
> + match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
> + if (!match)
> + return -EINVAL;
> +
> + combo_cfg = match->data;
> + if (!combo_cfg)
> + return -EINVAL;
> +
> + usb_cfg = combo_cfg->usb_cfg;
> + cfg = usb_cfg; /* Setup clks and regulators */
> + }
> +
> + /* per PHY serdes; usually located at base address */
> + usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(serdes))
> + return PTR_ERR(serdes);
> +
> + /* per PHY dp_com; if PHY has dp_com control block */
> + if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
> + qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
> + if (IS_ERR(qmp->dp_com))
> + return PTR_ERR(qmp->dp_com);
> + }
> +
> + if (combo_cfg) {
> + /* Only two serdes for combo PHY */
> + dp_serdes = devm_platform_ioremap_resource(pdev, 2);
> + if (IS_ERR(dp_serdes))
> + return PTR_ERR(dp_serdes);
> +
> + dp_cfg = combo_cfg->dp_cfg;
> + expected_phys = 2;
> + } else {
> + expected_phys = cfg->nlanes;
> + }
> +
> + mutex_init(&qmp->phy_mutex);
> +
> + ret = qcom_qmp_phy_clk_init(dev, cfg);
> + if (ret)
> + return ret;
> +
> + ret = qcom_qmp_phy_reset_init(dev, cfg);
> + if (ret)
> + return ret;
> +
> + ret = qcom_qmp_phy_vreg_init(dev, cfg);
> + if (ret) {
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "failed to get regulator supplies: %d\n",
> + ret);
> + return ret;
> + }
> +
> + num = of_get_available_child_count(dev->of_node);
> + /* do we have a rogue child node ? */
> + if (num > expected_phys)
> + return -EINVAL;
> +
> + qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
> + if (!qmp->phys)
> + return -ENOMEM;
> +
> + pm_runtime_set_active(dev);
> + pm_runtime_enable(dev);
> + /*
> + * Prevent runtime pm from being ON by default. Users can enable
> + * it using power/control in sysfs.
> + */
> + pm_runtime_forbid(dev);
> +
> + id = 0;
> + for_each_available_child_of_node(dev->of_node, child) {
> + if (of_node_name_eq(child, "dp-phy")) {
> + cfg = dp_cfg;
> + serdes = dp_serdes;
> + } else if (of_node_name_eq(child, "usb3-phy")) {
> + cfg = usb_cfg;
> + serdes = usb_serdes;
> + }
> +
> + /* Create per-lane phy */
> + ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
> + if (ret) {
> + dev_err(dev, "failed to create lane%d phy, %d\n",
> + id, ret);
> + goto err_node_put;
> + }
> +
> + /*
> + * Register the pipe clock provided by phy.
> + * See function description to see details of this pipe clock.
> + */
> + if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
> + ret = phy_pipe_clk_register(qmp, child);
> + if (ret) {
> + dev_err(qmp->dev,
> + "failed to register pipe clock source\n");
> + goto err_node_put;
> + }
> + } else if (cfg->type == PHY_TYPE_DP) {
> + ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
> + if (ret) {
> + dev_err(qmp->dev,
> + "failed to register DP clock source\n");
> + goto err_node_put;
> + }
> + }
> + id++;
> + }
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (!IS_ERR(phy_provider))
> + dev_info(dev, "Registered Qcom-QMP phy\n");
> + else
> + pm_runtime_disable(dev);
> +
> + return PTR_ERR_OR_ZERO(phy_provider);
> +
> +err_node_put:
> + pm_runtime_disable(dev);
> + of_node_put(child);
> + return ret;
> +}
> +
> +static struct platform_driver qcom_qmp_phy_driver = {
> + .probe = qcom_qmp_phy_probe,
> + .driver = {
> + .name = "qcom-qmp-phy",
> + .pm = &qcom_qmp_phy_pm_ops,
> + .of_match_table = qcom_qmp_phy_of_match_table,
> + },
> +};
> +
> +module_platform_driver(qcom_qmp_phy_driver);
> +
> +MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
> +MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> new file mode 100644
> index 000000000000..c7309e981bfb
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -0,0 +1,6350 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2017, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +
> +#include <dt-bindings/phy/phy.h>
> +
> +#include "phy-qcom-qmp.h"
> +
> +/* QPHY_SW_RESET bit */
> +#define SW_RESET BIT(0)
> +/* QPHY_POWER_DOWN_CONTROL */
> +#define SW_PWRDN BIT(0)
> +#define REFCLK_DRV_DSBL BIT(1)
> +/* QPHY_START_CONTROL bits */
> +#define SERDES_START BIT(0)
> +#define PCS_START BIT(1)
> +#define PLL_READY_GATE_EN BIT(3)
> +/* QPHY_PCS_STATUS bit */
> +#define PHYSTATUS BIT(6)
> +#define PHYSTATUS_4_20 BIT(7)
> +/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
> +#define PCS_READY BIT(0)
> +
> +/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
> +/* DP PHY soft reset */
> +#define SW_DPPHY_RESET BIT(0)
> +/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
> +#define SW_DPPHY_RESET_MUX BIT(1)
> +/* USB3 PHY soft reset */
> +#define SW_USB3PHY_RESET BIT(2)
> +/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
> +#define SW_USB3PHY_RESET_MUX BIT(3)
> +
> +/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
> +#define USB3_MODE BIT(0) /* enables USB3 mode */
> +#define DP_MODE BIT(1) /* enables DP mode */
> +
> +/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
> +#define ARCVR_DTCT_EN BIT(0)
> +#define ALFPS_DTCT_EN BIT(1)
> +#define ARCVR_DTCT_EVENT_SEL BIT(4)
> +
> +/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
> +#define IRQ_CLEAR BIT(0)
> +
> +/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
> +#define RCVR_DETECT BIT(0)
> +
> +/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
> +#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
> +
> +#define PHY_INIT_COMPLETE_TIMEOUT 10000
> +#define POWER_DOWN_DELAY_US_MIN 10
> +#define POWER_DOWN_DELAY_US_MAX 11
> +
> +#define MAX_PROP_NAME 32
> +
> +/* Define the assumed distance between lanes for underspecified device trees. */
> +#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
> +
> +struct qmp_phy_init_tbl {
> + unsigned int offset;
> + unsigned int val;
> + /*
> + * register part of layout ?
> + * if yes, then offset gives index in the reg-layout
> + */
> + bool in_layout;
> + /*
> + * mask of lanes for which this register is written
> + * for cases when second lane needs different values
> + */
> + u8 lane_mask;
> +};
> +
> +#define QMP_PHY_INIT_CFG(o, v) \
> + { \
> + .offset = o, \
> + .val = v, \
> + .lane_mask = 0xff, \
> + }
> +
> +#define QMP_PHY_INIT_CFG_L(o, v) \
> + { \
> + .offset = o, \
> + .val = v, \
> + .in_layout = true, \
> + .lane_mask = 0xff, \
> + }
> +
> +#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
> + { \
> + .offset = o, \
> + .val = v, \
> + .lane_mask = l, \
> + }
> +
> +/* set of registers with offsets different per-PHY */
> +enum qphy_reg_layout {
> + /* Common block control registers */
> + QPHY_COM_SW_RESET,
> + QPHY_COM_POWER_DOWN_CONTROL,
> + QPHY_COM_START_CONTROL,
> + QPHY_COM_PCS_READY_STATUS,
> + /* PCS registers */
> + QPHY_PLL_LOCK_CHK_DLY_TIME,
> + QPHY_FLL_CNTRL1,
> + QPHY_FLL_CNTRL2,
> + QPHY_FLL_CNT_VAL_L,
> + QPHY_FLL_CNT_VAL_H_TOL,
> + QPHY_FLL_MAN_CODE,
> + QPHY_SW_RESET,
> + QPHY_START_CTRL,
> + QPHY_PCS_READY_STATUS,
> + QPHY_PCS_STATUS,
> + QPHY_PCS_AUTONOMOUS_MODE_CTRL,
> + QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
> + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
> + QPHY_PCS_POWER_DOWN_CONTROL,
> + /* PCS_MISC registers */
> + QPHY_PCS_MISC_TYPEC_CTRL,
> + /* Keep last to ensure regs_layout arrays are properly initialized */
> + QPHY_LAYOUT_SIZE
> +};
> +
> +static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = 0x00,
> + [QPHY_PCS_READY_STATUS] = 0x168,
> +};
> +
> +static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> +};
> +
> +static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_COM_SW_RESET] = 0x400,
> + [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
> + [QPHY_COM_START_CONTROL] = 0x408,
> + [QPHY_COM_PCS_READY_STATUS] = 0x448,
> + [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
> + [QPHY_FLL_CNTRL1] = 0xc4,
> + [QPHY_FLL_CNTRL2] = 0xc8,
> + [QPHY_FLL_CNT_VAL_L] = 0xcc,
> + [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
> + [QPHY_FLL_MAN_CODE] = 0xd4,
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x174,
> +};
> +
> +static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_FLL_CNTRL1] = 0xc0,
> + [QPHY_FLL_CNTRL2] = 0xc4,
> + [QPHY_FLL_CNT_VAL_L] = 0xc8,
> + [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
> + [QPHY_FLL_MAN_CODE] = 0xd0,
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x17c,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
> +};
> +
> +static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x174,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
> +};
> +
> +static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x174,
> +};
> +
> +static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x2ac,
> +};
> +
> +static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
> +};
> +
> +static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
> +};
> +
> +static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
> +};
> +
> +static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
> + [QPHY_PCS_STATUS] = 0x174,
> + [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
> +};
> +
> +static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = 0x00,
> + [QPHY_PCS_READY_STATUS] = 0x160,
> +};
> +
> +static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = 0x00,
> + [QPHY_PCS_READY_STATUS] = 0x168,
> +};
> +
> +static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> +};
> +
> +static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
> + [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
> + [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + /* PLL and Loop filter settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + /* SSC settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
> + QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
> +
> + QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
> +
> + QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
> + QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
> + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
> + /* PLL and Loop filter settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + /* SSC settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
> + /* FLL settings */
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
> +
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
> + QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
> + QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
> + QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
> + QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
> + QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
> + QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
> + QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> + QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
> + QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
> + QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
> + QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
> + QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
> + QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
> + QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
> + QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
> + QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
> + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
> + QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
> + QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
> + /* FLL settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> +
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
> + /* FLL settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> +
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
> + QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
> + QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
> + QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
> +
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> +
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
> +};
> +
> +/* Register names should be validated, they might be different for this PHY */
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
> +};
> +
> +struct qmp_phy;
> +
> +/* struct qmp_phy_cfg - per-PHY initialization config */
> +struct qmp_phy_cfg {
> + /* phy-type - PCIE/UFS/USB */
> + unsigned int type;
> + /* number of lanes provided by phy */
> + int nlanes;
> +
> + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
> + const struct qmp_phy_init_tbl *serdes_tbl;
> + int serdes_tbl_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_sec;
> + int serdes_tbl_num_sec;
> + const struct qmp_phy_init_tbl *tx_tbl;
> + int tx_tbl_num;
> + const struct qmp_phy_init_tbl *tx_tbl_sec;
> + int tx_tbl_num_sec;
> + const struct qmp_phy_init_tbl *rx_tbl;
> + int rx_tbl_num;
> + const struct qmp_phy_init_tbl *rx_tbl_sec;
> + int rx_tbl_num_sec;
> + const struct qmp_phy_init_tbl *pcs_tbl;
> + int pcs_tbl_num;
> + const struct qmp_phy_init_tbl *pcs_tbl_sec;
> + int pcs_tbl_num_sec;
> + const struct qmp_phy_init_tbl *pcs_misc_tbl;
> + int pcs_misc_tbl_num;
> + const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
> + int pcs_misc_tbl_num_sec;
> +
> + /* Init sequence for DP PHY block link rates */
> + const struct qmp_phy_init_tbl *serdes_tbl_rbr;
> + int serdes_tbl_rbr_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_hbr;
> + int serdes_tbl_hbr_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
> + int serdes_tbl_hbr2_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
> + int serdes_tbl_hbr3_num;
> +
> + /* DP PHY callbacks */
> + int (*configure_dp_phy)(struct qmp_phy *qphy);
> + void (*configure_dp_tx)(struct qmp_phy *qphy);
> + int (*calibrate_dp_phy)(struct qmp_phy *qphy);
> + void (*dp_aux_init)(struct qmp_phy *qphy);
> +
> + /* clock ids to be requested */
> + const char * const *clk_list;
> + int num_clks;
> + /* resets to be requested */
> + const char * const *reset_list;
> + int num_resets;
> + /* regulators to be requested */
> + const char * const *vreg_list;
> + int num_vregs;
> +
> + /* array of registers with different offsets */
> + const unsigned int *regs;
> +
> + unsigned int start_ctrl;
> + unsigned int pwrdn_ctrl;
> + unsigned int mask_com_pcs_ready;
> + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
> + unsigned int phy_status;
> +
> + /* true, if PHY has a separate PHY_COM control block */
> + bool has_phy_com_ctrl;
> + /* true, if PHY has a reset for individual lanes */
> + bool has_lane_rst;
> + /* true, if PHY needs delay after POWER_DOWN */
> + bool has_pwrdn_delay;
> + /* power_down delay in usec */
> + int pwrdn_delay_min;
> + int pwrdn_delay_max;
> +
> + /* true, if PHY has a separate DP_COM control block */
> + bool has_phy_dp_com_ctrl;
> + /* true, if PHY has secondary tx/rx lanes to be configured */
> + bool is_dual_lane_phy;
> +
> + /* true, if PCS block has no separate SW_RESET register */
> + bool no_pcs_sw_reset;
> +};
> +
> +struct qmp_phy_combo_cfg {
> + const struct qmp_phy_cfg *usb_cfg;
> + const struct qmp_phy_cfg *dp_cfg;
> +};
> +
> +/**
> + * struct qmp_phy - per-lane phy descriptor
> + *
> + * @phy: generic phy
> + * @cfg: phy specific configuration
> + * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
> + * @tx: iomapped memory space for lane's tx
> + * @rx: iomapped memory space for lane's rx
> + * @pcs: iomapped memory space for lane's pcs
> + * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
> + * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
> + * @pcs_misc: iomapped memory space for lane's pcs_misc
> + * @pipe_clk: pipe clock
> + * @index: lane index
> + * @qmp: QMP phy to which this lane belongs
> + * @lane_rst: lane's reset controller
> + * @mode: current PHY mode
> + * @dp_aux_cfg: Display port aux config
> + * @dp_opts: Display port optional config
> + * @dp_clks: Display port clocks
> + */
> +struct qmp_phy {
> + struct phy *phy;
> + const struct qmp_phy_cfg *cfg;
> + void __iomem *serdes;
> + void __iomem *tx;
> + void __iomem *rx;
> + void __iomem *pcs;
> + void __iomem *tx2;
> + void __iomem *rx2;
> + void __iomem *pcs_misc;
> + struct clk *pipe_clk;
> + unsigned int index;
> + struct qcom_qmp *qmp;
> + struct reset_control *lane_rst;
> + enum phy_mode mode;
> + unsigned int dp_aux_cfg;
> + struct phy_configure_opts_dp dp_opts;
> + struct qmp_phy_dp_clks *dp_clks;
> +};
> +
> +struct qmp_phy_dp_clks {
> + struct qmp_phy *qphy;
> + struct clk_hw dp_link_hw;
> + struct clk_hw dp_pixel_hw;
> +};
> +
> +/**
> + * struct qcom_qmp - structure holding QMP phy block attributes
> + *
> + * @dev: device
> + * @dp_com: iomapped memory space for phy's dp_com control block
> + *
> + * @clks: array of clocks required by phy
> + * @resets: array of resets required by phy
> + * @vregs: regulator supplies bulk data
> + *
> + * @phys: array of per-lane phy descriptors
> + * @phy_mutex: mutex lock for PHY common block initialization
> + * @init_count: phy common block initialization count
> + * @ufs_reset: optional UFS PHY reset handle
> + */
> +struct qcom_qmp {
> + struct device *dev;
> + void __iomem *dp_com;
> +
> + struct clk_bulk_data *clks;
> + struct reset_control **resets;
> + struct regulator_bulk_data *vregs;
> +
> + struct qmp_phy **phys;
> +
> + struct mutex phy_mutex;
> + int init_count;
> +
> + struct reset_control *ufs_reset;
> +};
> +
> +static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
> +static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
> +static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
> +static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
> +
> +static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
> +static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
> +static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
> +static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
> +
> +static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
> +{
> + u32 reg;
> +
> + reg = readl(base + offset);
> + reg |= val;
> + writel(reg, base + offset);
> +
> + /* ensure that above write is through */
> + readl(base + offset);
> +}
> +
> +static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
> +{
> + u32 reg;
> +
> + reg = readl(base + offset);
> + reg &= ~val;
> + writel(reg, base + offset);
> +
> + /* ensure that above write is through */
> + readl(base + offset);
> +}
> +
> +/* list of clocks required by phy */
> +static const char * const msm8996_phy_clk_l[] = {
> + "aux", "cfg_ahb", "ref",
> +};
> +
> +static const char * const msm8996_ufs_phy_clk_l[] = {
> + "ref",
> +};
> +
> +static const char * const qmp_v3_phy_clk_l[] = {
> + "aux", "cfg_ahb", "ref", "com_aux",
> +};
> +
> +static const char * const sdm845_pciephy_clk_l[] = {
> + "aux", "cfg_ahb", "ref", "refgen",
> +};
> +
> +static const char * const qmp_v4_phy_clk_l[] = {
> + "aux", "ref_clk_src", "ref", "com_aux",
> +};
> +
> +/* the primary usb3 phy on sm8250 doesn't have a ref clock */
> +static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
> + "aux", "ref_clk_src", "com_aux"
> +};
> +
> +static const char * const sm8450_ufs_phy_clk_l[] = {
> + "qref", "ref", "ref_aux",
> +};
> +
> +static const char * const sdm845_ufs_phy_clk_l[] = {
> + "ref", "ref_aux",
> +};
> +
> +/* usb3 phy on sdx55 doesn't have com_aux clock */
> +static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
> + "aux", "cfg_ahb", "ref"
> +};
> +
> +static const char * const qcm2290_usb3phy_clk_l[] = {
> + "cfg_ahb", "ref", "com_aux",
> +};
> +
> +/* list of resets */
> +static const char * const msm8996_pciephy_reset_l[] = {
> + "phy", "common", "cfg",
> +};
> +
> +static const char * const msm8996_usb3phy_reset_l[] = {
> + "phy", "common",
> +};
> +
> +static const char * const sc7180_usb3phy_reset_l[] = {
> + "phy",
> +};
> +
> +static const char * const qcm2290_usb3phy_reset_l[] = {
> + "phy_phy", "phy",
> +};
> +
> +static const char * const sdm845_pciephy_reset_l[] = {
> + "phy",
> +};
> +
> +/* list of regulators */
> +static const char * const qmp_phy_vreg_l[] = {
> + "vdda-phy", "vdda-pll",
> +};
> +
> +static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = ipq8074_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
> + .tx_tbl = msm8996_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
> + .rx_tbl = ipq8074_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
> + .pcs_tbl = ipq8074_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +};
> +
> +static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 3,
> +
> + .serdes_tbl = msm8996_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
> + .tx_tbl = msm8996_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
> + .rx_tbl = msm8996_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
> + .pcs_tbl = msm8996_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = pciephy_regs_layout,
> +
> + .start_ctrl = PCS_START | PLL_READY_GATE_EN,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .mask_com_pcs_ready = PCS_READY,
> + .phy_status = PHYSTATUS,
> +
> + .has_phy_com_ctrl = true,
> + .has_lane_rst = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg msm8996_ufs_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8996_ufs_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
> + .tx_tbl = msm8996_ufs_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
> + .rx_tbl = msm8996_ufs_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
> +
> + .clk_list = msm8996_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
> +
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> +
> + .regs = msm8996_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .no_pcs_sw_reset = true,
> +};
> +
> +static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8996_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
> + .tx_tbl = msm8996_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
> + .rx_tbl = msm8996_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
> + .pcs_tbl = msm8996_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +};
> +
> +static const char * const ipq8074_pciephy_clk_l[] = {
> + "aux", "cfg_ahb",
> +};
> +/* list of resets */
> +static const char * const ipq8074_pciephy_reset_l[] = {
> + "phy", "common",
> +};
> +
> +static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = ipq8074_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
> + .tx_tbl = ipq8074_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
> + .rx_tbl = ipq8074_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
> + .pcs_tbl = ipq8074_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
> + .clk_list = ipq8074_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
> + .reset_list = ipq8074_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
> + .vreg_list = NULL,
> + .num_vregs = 0,
> + .regs = pciephy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_phy_com_ctrl = false,
> + .has_lane_rst = false,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = ipq6018_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
> + .tx_tbl = ipq6018_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
> + .rx_tbl = ipq6018_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
> + .pcs_tbl = ipq6018_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
> + .clk_list = ipq8074_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
> + .reset_list = ipq8074_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
> + .vreg_list = NULL,
> + .num_vregs = 0,
> + .regs = ipq_pciephy_gen3_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> +
> + .has_phy_com_ctrl = false,
> + .has_lane_rst = false,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
> + .tx_tbl = sdm845_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
> + .rx_tbl = sdm845_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
> + .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
> + .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sdm845_qmp_pciephy_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
> + .tx_tbl = sdm845_qhp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
> + .rx_tbl = sdm845_qhp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
> + .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sdm845_qhp_pciephy_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
> + .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
> + .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
> + .tx_tbl = sm8250_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
> + .rx_tbl = sm8250_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
> + .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
> + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
> + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
> + .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
> + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
> + .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
> + .tx_tbl = sm8250_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
> + .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
> + .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
> + .rx_tbl = sm8250_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
> + .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
> + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
> + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
> + .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
> + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
> + .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
> + .tx_tbl = qmp_v3_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
> + .rx_tbl = qmp_v3_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
> + .pcs_tbl = qmp_v3_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
> + .tx_tbl = qmp_v3_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
> + .rx_tbl = qmp_v3_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
> + .pcs_tbl = qmp_v3_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = sc7180_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
> + .type = PHY_TYPE_DP,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_dp_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
> + .tx_tbl = qmp_v3_dp_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
> +
> + .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
> + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
> + .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
> + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
> + .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
> + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
> + .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
> + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
> +
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = sc7180_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +
> + .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
> + .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
> + .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
> + .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
> +};
> +
> +static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
> + .usb_cfg = &sc7180_usb3phy_cfg,
> + .dp_cfg = &sc7180_dpphy_cfg,
> +};
> +
> +static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
> + .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
> + .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
> + .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sdm845_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
> + .tx_tbl = sdm845_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
> + .rx_tbl = sdm845_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
> + .pcs_tbl = sdm845_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sdm845_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> + .no_pcs_sw_reset = true,
> +};
> +
> +static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm6115_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
> + .tx_tbl = sm6115_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
> + .rx_tbl = sm6115_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
> + .pcs_tbl = sm6115_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm6115_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> +
> + .is_dual_lane_phy = false,
> + .no_pcs_sw_reset = true,
> +};
> +
> +static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8998_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
> + .tx_tbl = msm8998_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
> + .rx_tbl = msm8998_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
> + .pcs_tbl = msm8998_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = ipq8074_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = pciephy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +};
> +
> +static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8998_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
> + .tx_tbl = msm8998_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
> + .rx_tbl = msm8998_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
> + .pcs_tbl = msm8998_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8150_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
> + .tx_tbl = sm8150_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
> + .rx_tbl = sm8150_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
> + .pcs_tbl = sm8150_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8150_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
> + .tx_tbl = sm8150_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
> + .rx_tbl = sm8150_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
> + .pcs_tbl = sm8150_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
> + .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
> + .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
> + .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
> + .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
> + .type = PHY_TYPE_DP,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v4_dp_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
> + .tx_tbl = qmp_v4_dp_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
> +
> + .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
> + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
> + .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
> + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
> + .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
> + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
> + .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
> + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
> +
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = sc7180_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +
> + .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
> + .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
> + .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
> + .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
> +};
> +
> +static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
> + .usb_cfg = &sm8150_usb3phy_cfg,
> + .dp_cfg = &sc8180x_dpphy_cfg,
> +};
> +
> +static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
> + .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
> + .tx_tbl = sm8250_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
> + .rx_tbl = sm8250_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
> + .pcs_tbl = sm8250_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
> + .clk_list = qmp_v4_sm8250_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
> + .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
> + .type = PHY_TYPE_DP,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v4_dp_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
> + .tx_tbl = qmp_v4_dp_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
> +
> + .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
> + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
> + .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
> + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
> + .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
> + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
> + .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
> + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
> +
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +
> + .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
> + .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
> + .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
> + .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
> +};
> +
> +static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
> + .usb_cfg = &sm8250_usb3phy_cfg,
> + .dp_cfg = &sm8250_dpphy_cfg,
> +};
> +
> +static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
> + .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_sdx55_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 2,
> +
> + .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
> + .tx_tbl = sdx55_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
> + .rx_tbl = sdx55_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
> + .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
> + .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS_4_20,
> +
> + .is_dual_lane_phy = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
> + .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_sdx55_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8350_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8350_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
> + .tx_tbl = sm8350_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
> + .rx_tbl = sm8350_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
> + .pcs_tbl = sm8350_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8150_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
> + .tx_tbl = sm8350_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
> + .rx_tbl = sm8350_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
> + .pcs_tbl = sm8350_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
> + .clk_list = qmp_v4_sm8250_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
> + .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8350_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8350_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
> + .tx_tbl = sm8350_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
> + .rx_tbl = sm8350_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
> + .pcs_tbl = sm8350_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
> + .clk_list = sm8450_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8150_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
> + .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
> + .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
> + .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
> + .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
> + .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
> + .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS_4_20,
> +
> + .is_dual_lane_phy = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qcm2290_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
> + .tx_tbl = qcm2290_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
> + .rx_tbl = qcm2290_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
> + .pcs_tbl = qcm2290_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
> + .clk_list = qcm2290_usb3phy_clk_l,
> + .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
> + .reset_list = qcm2290_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qcm2290_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static void qcom_qmp_phy_configure_lane(void __iomem *base,
> + const unsigned int *regs,
> + const struct qmp_phy_init_tbl tbl[],
> + int num,
> + u8 lane_mask)
> +{
> + int i;
> + const struct qmp_phy_init_tbl *t = tbl;
> +
> + if (!t)
> + return;
> +
> + for (i = 0; i < num; i++, t++) {
> + if (!(t->lane_mask & lane_mask))
> + continue;
> +
> + if (t->in_layout)
> + writel(t->val, base + regs[t->offset]);
> + else
> + writel(t->val, base + t->offset);
> + }
> +}
> +
> +static void qcom_qmp_phy_configure(void __iomem *base,
> + const unsigned int *regs,
> + const struct qmp_phy_init_tbl tbl[],
> + int num)
> +{
> + qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
> +}
> +
> +static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
> +{
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
> + int serdes_tbl_num = cfg->serdes_tbl_num;
> + int ret;
> +
> + qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
> + if (cfg->serdes_tbl_sec)
> + qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
> + cfg->serdes_tbl_num_sec);
> +
> + if (cfg->type == PHY_TYPE_DP) {
> + switch (dp_opts->link_rate) {
> + case 1620:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_rbr,
> + cfg->serdes_tbl_rbr_num);
> + break;
> + case 2700:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_hbr,
> + cfg->serdes_tbl_hbr_num);
> + break;
> + case 5400:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_hbr2,
> + cfg->serdes_tbl_hbr2_num);
> + break;
> + case 8100:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_hbr3,
> + cfg->serdes_tbl_hbr3_num);
> + break;
> + default:
> + /* Other link rates aren't supported */
> + return -EINVAL;
> + }
> + }
> +
> +
> + if (cfg->has_phy_com_ctrl) {
> + void __iomem *status;
> + unsigned int mask, val;
> +
> + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
> + SERDES_START | PCS_START);
> +
> + status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
> + mask = cfg->mask_com_pcs_ready;
> +
> + ret = readl_poll_timeout(status, val, (val & mask), 10,
> + PHY_INIT_COMPLETE_TIMEOUT);
> + if (ret) {
> + dev_err(qmp->dev,
> + "phy common block init timed-out\n");
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
> +{
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
> + qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + /* Turn on BIAS current for PHY/PLL */
> + writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
> + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
> + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
> +
> + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_LANE_0_1_PWRDN |
> + DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
> + DP_PHY_PD_CTL_DP_CLAMP_EN,
> + qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + writel(QSERDES_V3_COM_BIAS_EN |
> + QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
> + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
> + QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
> + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
> +
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
> + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> + writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
> + writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
> + writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
> + qphy->dp_aux_cfg = 0;
> +
> + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
> + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
> + PHY_AUX_REQ_ERR_MASK,
> + qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
> +}
> +
> +static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
> + { 0x00, 0x0c, 0x15, 0x1a },
> + { 0x02, 0x0e, 0x16, 0xff },
> + { 0x02, 0x11, 0xff, 0xff },
> + { 0x04, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
> + { 0x02, 0x12, 0x16, 0x1a },
> + { 0x09, 0x19, 0x1f, 0xff },
> + { 0x10, 0x1f, 0xff, 0xff },
> + { 0x1f, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
> + { 0x00, 0x0c, 0x14, 0x19 },
> + { 0x00, 0x0b, 0x12, 0xff },
> + { 0x00, 0x0b, 0xff, 0xff },
> + { 0x04, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
> + { 0x08, 0x0f, 0x16, 0x1f },
> + { 0x11, 0x1e, 0x1f, 0xff },
> + { 0x19, 0x1f, 0xff, 0xff },
> + { 0x1f, 0xff, 0xff, 0xff }
> +};
> +
> +static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
> + unsigned int drv_lvl_reg, unsigned int emp_post_reg)
> +{
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + unsigned int v_level = 0, p_level = 0;
> + u8 voltage_swing_cfg, pre_emphasis_cfg;
> + int i;
> +
> + for (i = 0; i < dp_opts->lanes; i++) {
> + v_level = max(v_level, dp_opts->voltage[i]);
> + p_level = max(p_level, dp_opts->pre[i]);
> + }
> +
> + if (dp_opts->link_rate <= 2700) {
> + voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
> + pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
> + } else {
> + voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
> + pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
> + }
> +
> + /* TODO: Move check to config check */
> + if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
> + return -EINVAL;
> +
> + /* Enable MUX to use Cursor values from these registers */
> + voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
> + pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
> +
> + writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
> + writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
> + writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
> + writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
> +{
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + u32 bias_en, drvr_en;
> +
> + if (qcom_qmp_phy_configure_dp_swing(qphy,
> + QSERDES_V3_TX_TX_DRV_LVL,
> + QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
> + return;
> +
> + if (dp_opts->lanes == 1) {
> + bias_en = 0x3e;
> + drvr_en = 0x13;
> + } else {
> + bias_en = 0x3f;
> + drvr_en = 0x10;
> + }
> +
> + writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
> + writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
> + writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
> + writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
> +}
> +
> +static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
> +{
> + u32 val;
> + bool reverse = false;
> +
> + val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
> +
> + /*
> + * TODO: Assume orientation is CC1 for now and two lanes, need to
> + * use type-c connector to understand orientation and lanes.
> + *
> + * Otherwise val changes to be like below if this code understood
> + * the orientation of the type-c cable.
> + *
> + * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
> + * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
> + * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
> + * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
> + * if (orientation == ORIENTATION_CC2)
> + * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
> + */
> + val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
> + writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
> +
> + return reverse;
> +}
> +
> +static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + u32 phy_vco_div, status;
> + unsigned long pixel_freq;
> +
> + qcom_qmp_phy_configure_dp_mode(qphy);
> +
> + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
> + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + phy_vco_div = 0x1;
> + pixel_freq = 1620000000UL / 2;
> + break;
> + case 2700:
> + phy_vco_div = 0x1;
> + pixel_freq = 2700000000UL / 2;
> + break;
> + case 5400:
> + phy_vco_div = 0x2;
> + pixel_freq = 5400000000UL / 4;
> + break;
> + case 8100:
> + phy_vco_div = 0x0;
> + pixel_freq = 8100000000UL / 6;
> + break;
> + default:
> + /* Other link rates aren't supported */
> + return -EINVAL;
> + }
> + writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
> +
> + clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
> + clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
> +
> + writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
> + udelay(2000);
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000);
> +}
> +
> +/*
> + * We need to calibrate the aux setting here as many times
> + * as the caller tries
> + */
> +static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
> +{
> + static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
> + u8 val;
> +
> + qphy->dp_aux_cfg++;
> + qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
> + val = cfg1_settings[qphy->dp_aux_cfg];
> +
> + writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
> +{
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
> + qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + /* Turn on BIAS current for PHY/PLL */
> + writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
> +
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
> + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> + writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
> + writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
> + writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
> + qphy->dp_aux_cfg = 0;
> +
> + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
> + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
> + PHY_AUX_REQ_ERR_MASK,
> + qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
> +}
> +
> +static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
> +{
> + /* Program default values before writing proper values */
> + writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
> + writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
> +
> + writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> + writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> +
> + qcom_qmp_phy_configure_dp_swing(qphy,
> + QSERDES_V4_TX_TX_DRV_LVL,
> + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> +}
> +
> +static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + u32 phy_vco_div, status;
> + unsigned long pixel_freq;
> + u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
> + bool reverse;
> +
> + writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
> +
> + reverse = qcom_qmp_phy_configure_dp_mode(qphy);
> +
> + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> + writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> +
> + writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
> + writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + phy_vco_div = 0x1;
> + pixel_freq = 1620000000UL / 2;
> + break;
> + case 2700:
> + phy_vco_div = 0x1;
> + pixel_freq = 2700000000UL / 2;
> + break;
> + case 5400:
> + phy_vco_div = 0x2;
> + pixel_freq = 5400000000UL / 4;
> + break;
> + case 8100:
> + phy_vco_div = 0x0;
> + pixel_freq = 8100000000UL / 6;
> + break;
> + default:
> + /* Other link rates aren't supported */
> + return -EINVAL;
> + }
> + writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
> +
> + clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
> + clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
> +
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + /*
> + * At least for 7nm DP PHY this has to be done after enabling link
> + * clock.
> + */
> +
> + if (dp_opts->lanes == 1) {
> + bias0_en = reverse ? 0x3e : 0x15;
> + bias1_en = reverse ? 0x15 : 0x3e;
> + drvr0_en = reverse ? 0x13 : 0x10;
> + drvr1_en = reverse ? 0x10 : 0x13;
> + } else if (dp_opts->lanes == 2) {
> + bias0_en = reverse ? 0x3f : 0x15;
> + bias1_en = reverse ? 0x15 : 0x3f;
> + drvr0_en = 0x10;
> + drvr1_en = 0x10;
> + } else {
> + bias0_en = 0x3f;
> + bias1_en = 0x3f;
> + drvr0_en = 0x10;
> + drvr1_en = 0x10;
> + }
> +
> + writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
> + writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
> + writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
> + writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
> +
> + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
> + udelay(2000);
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
> + writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
> +
> + writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
> + writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
> +
> + writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> + writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> +
> + return 0;
> +}
> +
> +/*
> + * We need to calibrate the aux setting here as many times
> + * as the caller tries
> + */
> +static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
> +{
> + static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
> + u8 val;
> +
> + qphy->dp_aux_cfg++;
> + qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
> + val = cfg1_settings[qphy->dp_aux_cfg];
> +
> + writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
> +{
> + const struct phy_configure_opts_dp *dp_opts = &opts->dp;
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
> + if (qphy->dp_opts.set_voltages) {
> + cfg->configure_dp_tx(qphy);
> + qphy->dp_opts.set_voltages = 0;
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + if (cfg->calibrate_dp_phy)
> + return cfg->calibrate_dp_phy(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
> +{
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *dp_com = qmp->dp_com;
> + int ret, i;
> +
> + mutex_lock(&qmp->phy_mutex);
> + if (qmp->init_count++) {
> + mutex_unlock(&qmp->phy_mutex);
> + return 0;
> + }
> +
> + /* turn on regulator supplies */
> + ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
> + if (ret) {
> + dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
> + goto err_unlock;
> + }
> +
> + for (i = 0; i < cfg->num_resets; i++) {
> + ret = reset_control_assert(qmp->resets[i]);
> + if (ret) {
> + dev_err(qmp->dev, "%s reset assert failed\n",
> + cfg->reset_list[i]);
> + goto err_disable_regulators;
> + }
> + }
> +
> + for (i = cfg->num_resets - 1; i >= 0; i--) {
> + ret = reset_control_deassert(qmp->resets[i]);
> + if (ret) {
> + dev_err(qmp->dev, "%s reset deassert failed\n",
> + qphy->cfg->reset_list[i]);
> + goto err_assert_reset;
> + }
> + }
> +
> + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
> + if (ret)
> + goto err_assert_reset;
> +
> + if (cfg->has_phy_dp_com_ctrl) {
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
> + SW_PWRDN);
> + /* override hardware control for reset of qmp phy */
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
> + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
> + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
> +
> + /* Default type-c orientation, i.e CC1 */
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
> +
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
> + USB3_MODE | DP_MODE);
> +
> + /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
> + qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
> + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
> + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
> +
> + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
> + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
> + }
> +
> + if (cfg->has_phy_com_ctrl) {
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
> + SW_PWRDN);
> + } else {
> + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
> + qphy_setbits(pcs,
> + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
> + cfg->pwrdn_ctrl);
> + else
> + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
> + cfg->pwrdn_ctrl);
> + }
> +
> + mutex_unlock(&qmp->phy_mutex);
> +
> + return 0;
> +
> +err_assert_reset:
> + while (++i < cfg->num_resets)
> + reset_control_assert(qmp->resets[i]);
> +err_disable_regulators:
> + regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
> +err_unlock:
> + mutex_unlock(&qmp->phy_mutex);
> +
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
> +{
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + int i = cfg->num_resets;
> +
> + mutex_lock(&qmp->phy_mutex);
> + if (--qmp->init_count) {
> + mutex_unlock(&qmp->phy_mutex);
> + return 0;
> + }
> +
> + reset_control_assert(qmp->ufs_reset);
> + if (cfg->has_phy_com_ctrl) {
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
> + SERDES_START | PCS_START);
> + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
> + SW_RESET);
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
> + SW_PWRDN);
> + }
> +
> + while (--i >= 0)
> + reset_control_assert(qmp->resets[i]);
> +
> + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
> +
> + regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
> +
> + mutex_unlock(&qmp->phy_mutex);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_init(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + int ret;
> + dev_vdbg(qmp->dev, "Initializing QMP phy\n");
> +
> + if (cfg->no_pcs_sw_reset) {
> + /*
> + * Get UFS reset, which is delayed until now to avoid a
> + * circular dependency where UFS needs its PHY, but the PHY
> + * needs this UFS reset.
> + */
> + if (!qmp->ufs_reset) {
> + qmp->ufs_reset =
> + devm_reset_control_get_exclusive(qmp->dev,
> + "ufsphy");
> +
> + if (IS_ERR(qmp->ufs_reset)) {
> + ret = PTR_ERR(qmp->ufs_reset);
> + dev_err(qmp->dev,
> + "failed to get UFS reset: %d\n",
> + ret);
> +
> + qmp->ufs_reset = NULL;
> + return ret;
> + }
> + }
> +
> + ret = reset_control_assert(qmp->ufs_reset);
> + if (ret)
> + return ret;
> + }
> +
> + ret = qcom_qmp_phy_com_init(qphy);
> + if (ret)
> + return ret;
> +
> + if (cfg->type == PHY_TYPE_DP)
> + cfg->dp_aux_init(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_power_on(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *tx = qphy->tx;
> + void __iomem *rx = qphy->rx;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *pcs_misc = qphy->pcs_misc;
> + void __iomem *status;
> + unsigned int mask, val, ready;
> + int ret;
> +
> + qcom_qmp_phy_serdes_init(qphy);
> +
> + if (cfg->has_lane_rst) {
> + ret = reset_control_deassert(qphy->lane_rst);
> + if (ret) {
> + dev_err(qmp->dev, "lane%d reset deassert failed\n",
> + qphy->index);
> + return ret;
> + }
> + }
> +
> + ret = clk_prepare_enable(qphy->pipe_clk);
> + if (ret) {
> + dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
> + goto err_reset_lane;
> + }
> +
> + /* Tx, Rx, and PCS configurations */
> + qcom_qmp_phy_configure_lane(tx, cfg->regs,
> + cfg->tx_tbl, cfg->tx_tbl_num, 1);
> + if (cfg->tx_tbl_sec)
> + qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
> + cfg->tx_tbl_num_sec, 1);
> +
> + /* Configuration for other LANE for USB-DP combo PHY */
> + if (cfg->is_dual_lane_phy) {
> + qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
> + cfg->tx_tbl, cfg->tx_tbl_num, 2);
> + if (cfg->tx_tbl_sec)
> + qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
> + cfg->tx_tbl_sec,
> + cfg->tx_tbl_num_sec, 2);
> + }
> +
> + /* Configure special DP tx tunings */
> + if (cfg->type == PHY_TYPE_DP)
> + cfg->configure_dp_tx(qphy);
> +
> + qcom_qmp_phy_configure_lane(rx, cfg->regs,
> + cfg->rx_tbl, cfg->rx_tbl_num, 1);
> + if (cfg->rx_tbl_sec)
> + qcom_qmp_phy_configure_lane(rx, cfg->regs,
> + cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
> +
> + if (cfg->is_dual_lane_phy) {
> + qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
> + cfg->rx_tbl, cfg->rx_tbl_num, 2);
> + if (cfg->rx_tbl_sec)
> + qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
> + cfg->rx_tbl_sec,
> + cfg->rx_tbl_num_sec, 2);
> + }
> +
> + /* Configure link rate, swing, etc. */
> + if (cfg->type == PHY_TYPE_DP) {
> + cfg->configure_dp_phy(qphy);
> + } else {
> + qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
> + if (cfg->pcs_tbl_sec)
> + qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
> + cfg->pcs_tbl_num_sec);
> + }
> +
> + ret = reset_control_deassert(qmp->ufs_reset);
> + if (ret)
> + goto err_disable_pipe_clk;
> +
> + qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
> + cfg->pcs_misc_tbl_num);
> + if (cfg->pcs_misc_tbl_sec)
> + qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
> + cfg->pcs_misc_tbl_num_sec);
> +
> + /*
> + * Pull out PHY from POWER DOWN state.
> + * This is active low enable signal to power-down PHY.
> + */
> + if(cfg->type == PHY_TYPE_PCIE)
> + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
> +
> + if (cfg->has_pwrdn_delay)
> + usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
> +
> + if (cfg->type != PHY_TYPE_DP) {
> + /* Pull PHY out of reset state */
> + if (!cfg->no_pcs_sw_reset)
> + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
> + /* start SerDes and Phy-Coding-Sublayer */
> + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
> +
> + if (cfg->type == PHY_TYPE_UFS) {
> + status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
> + mask = PCS_READY;
> + ready = PCS_READY;
> + } else {
> + status = pcs + cfg->regs[QPHY_PCS_STATUS];
> + mask = cfg->phy_status;
> + ready = 0;
> + }
> +
> + ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
> + PHY_INIT_COMPLETE_TIMEOUT);
> + if (ret) {
> + dev_err(qmp->dev, "phy initialization timed-out\n");
> + goto err_disable_pipe_clk;
> + }
> + }
> + return 0;
> +
> +err_disable_pipe_clk:
> + clk_disable_unprepare(qphy->pipe_clk);
> +err_reset_lane:
> + if (cfg->has_lane_rst)
> + reset_control_assert(qphy->lane_rst);
> +
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_power_off(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + clk_disable_unprepare(qphy->pipe_clk);
> +
> + if (cfg->type == PHY_TYPE_DP) {
> + /* Assert DP PHY power down */
> + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> + } else {
> + /* PHY reset */
> + if (!cfg->no_pcs_sw_reset)
> + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
> +
> + /* stop SerDes and Phy-Coding-Sublayer */
> + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
> +
> + /* Put PHY into POWER DOWN state: active low */
> + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
> + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
> + cfg->pwrdn_ctrl);
> + } else {
> + qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
> + cfg->pwrdn_ctrl);
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_exit(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + if (cfg->has_lane_rst)
> + reset_control_assert(qphy->lane_rst);
> +
> + qcom_qmp_phy_com_exit(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_enable(struct phy *phy)
> +{
> + int ret;
> +
> + ret = qcom_qmp_phy_init(phy);
> + if (ret)
> + return ret;
> +
> + ret = qcom_qmp_phy_power_on(phy);
> + if (ret)
> + qcom_qmp_phy_exit(phy);
> +
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_disable(struct phy *phy)
> +{
> + int ret;
> +
> + ret = qcom_qmp_phy_power_off(phy);
> + if (ret)
> + return ret;
> + return qcom_qmp_phy_exit(phy);
> +}
> +
> +static int qcom_qmp_phy_set_mode(struct phy *phy,
> + enum phy_mode mode, int submode)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> +
> + qphy->mode = mode;
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *pcs_misc = qphy->pcs_misc;
> + u32 intr_mask;
> +
> + if (qphy->mode == PHY_MODE_USB_HOST_SS ||
> + qphy->mode == PHY_MODE_USB_DEVICE_SS)
> + intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
> + else
> + intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
> +
> + /* Clear any pending interrupts status */
> + qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> + /* Writing 1 followed by 0 clears the interrupt */
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> +
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
> + ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
> +
> + /* Enable required PHY autonomous mode interrupts */
> + qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
> +
> + /* Enable i/o clamp_n for autonomous mode */
> + if (pcs_misc)
> + qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
> +}
> +
> +static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *pcs_misc = qphy->pcs_misc;
> +
> + /* Disable i/o clamp_n on resume for normal mode */
> + if (pcs_misc)
> + qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
> +
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
> + ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
> +
> + qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> + /* Writing 1 followed by 0 clears the interrupt */
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> +}
> +
> +static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + struct qmp_phy *qphy = qmp->phys[0];
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
> +
> + /* Supported only for USB3 PHY and luckily USB3 is the first phy */
> + if (cfg->type != PHY_TYPE_USB3)
> + return 0;
> +
> + if (!qmp->init_count) {
> + dev_vdbg(dev, "PHY not initialized, bailing out\n");
> + return 0;
> + }
> +
> + qcom_qmp_phy_enable_autonomous_mode(qphy);
> +
> + clk_disable_unprepare(qphy->pipe_clk);
> + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
> +
> + return 0;
> +}
> +
> +static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + struct qmp_phy *qphy = qmp->phys[0];
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + int ret = 0;
> +
> + dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
> +
> + /* Supported only for USB3 PHY and luckily USB3 is the first phy */
> + if (cfg->type != PHY_TYPE_USB3)
> + return 0;
> +
> + if (!qmp->init_count) {
> + dev_vdbg(dev, "PHY not initialized, bailing out\n");
> + return 0;
> + }
> +
> + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(qphy->pipe_clk);
> + if (ret) {
> + dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
> + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
> + return ret;
> + }
> +
> + qcom_qmp_phy_disable_autonomous_mode(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + int num = cfg->num_vregs;
> + int i;
> +
> + qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
> + if (!qmp->vregs)
> + return -ENOMEM;
> +
> + for (i = 0; i < num; i++)
> + qmp->vregs[i].supply = cfg->vreg_list[i];
> +
> + return devm_regulator_bulk_get(dev, num, qmp->vregs);
> +}
> +
> +static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + int i;
> +
> + qmp->resets = devm_kcalloc(dev, cfg->num_resets,
> + sizeof(*qmp->resets), GFP_KERNEL);
> + if (!qmp->resets)
> + return -ENOMEM;
> +
> + for (i = 0; i < cfg->num_resets; i++) {
> + struct reset_control *rst;
> + const char *name = cfg->reset_list[i];
> +
> + rst = devm_reset_control_get_exclusive(dev, name);
> + if (IS_ERR(rst)) {
> + dev_err(dev, "failed to get %s reset\n", name);
> + return PTR_ERR(rst);
> + }
> + qmp->resets[i] = rst;
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + int num = cfg->num_clks;
> + int i;
> +
> + qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
> + if (!qmp->clks)
> + return -ENOMEM;
> +
> + for (i = 0; i < num; i++)
> + qmp->clks[i].id = cfg->clk_list[i];
> +
> + return devm_clk_bulk_get(dev, num, qmp->clks);
> +}
> +
> +static void phy_clk_release_provider(void *res)
> +{
> + of_clk_del_provider(res);
> +}
> +
> +/*
> + * Register a fixed rate pipe clock.
> + *
> + * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
> + * controls it. The <s>_pipe_clk coming out of the GCC is requested
> + * by the PHY driver for its operations.
> + * We register the <s>_pipe_clksrc here. The gcc driver takes care
> + * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
> + * Below picture shows this relationship.
> + *
> + * +---------------+
> + * | PHY block |<<---------------------------------------+
> + * | | |
> + * | +-------+ | +-----+ |
> + * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
> + * clk | +-------+ | +-----+
> + * +---------------+
> + */
> +static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
> +{
> + struct clk_fixed_rate *fixed;
> + struct clk_init_data init = { };
> + int ret;
> +
> + ret = of_property_read_string(np, "clock-output-names", &init.name);
> + if (ret) {
> + dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
> + return ret;
> + }
> +
> + fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
> + if (!fixed)
> + return -ENOMEM;
> +
> + init.ops = &clk_fixed_rate_ops;
> +
> + /* controllers using QMP phys use 125MHz pipe clock interface */
> + fixed->fixed_rate = 125000000;
> + fixed->hw.init = &init;
> +
> + ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
> + if (ret)
> + return ret;
> +
> + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
> + if (ret)
> + return ret;
> +
> + /*
> + * Roll a devm action because the clock provider is the child node, but
> + * the child node is not actually a device.
> + */
> + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
> +}
> +
> +/*
> + * Display Port PLL driver block diagram for branch clocks
> + *
> + * +------------------------------+
> + * | DP_VCO_CLK |
> + * | |
> + * | +-------------------+ |
> + * | | (DP PLL/VCO) | |
> + * | +---------+---------+ |
> + * | v |
> + * | +----------+-----------+ |
> + * | | hsclk_divsel_clk_src | |
> + * | +----------+-----------+ |
> + * +------------------------------+
> + * |
> + * +---------<---------v------------>----------+
> + * | |
> + * +--------v----------------+ |
> + * | dp_phy_pll_link_clk | |
> + * | link_clk | |
> + * +--------+----------------+ |
> + * | |
> + * | |
> + * v v
> + * Input to DISPCC block |
> + * for link clk, crypto clk |
> + * and interface clock |
> + * |
> + * |
> + * +--------<------------+-----------------+---<---+
> + * | | |
> + * +----v---------+ +--------v-----+ +--------v------+
> + * | vco_divided | | vco_divided | | vco_divided |
> + * | _clk_src | | _clk_src | | _clk_src |
> + * | | | | | |
> + * |divsel_six | | divsel_two | | divsel_four |
> + * +-------+------+ +-----+--------+ +--------+------+
> + * | | |
> + * v---->----------v-------------<------v
> + * |
> + * +----------+-----------------+
> + * | dp_phy_pll_vco_div_clk |
> + * +---------+------------------+
> + * |
> + * v
> + * Input to DISPCC block
> + * for DP pixel clock
> + *
> + */
> +static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + switch (req->rate) {
> + case 1620000000UL / 2:
> + case 2700000000UL / 2:
> + /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
> + return 0;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static unsigned long
> +qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + const struct qmp_phy_dp_clks *dp_clks;
> + const struct qmp_phy *qphy;
> + const struct phy_configure_opts_dp *dp_opts;
> +
> + dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
> + qphy = dp_clks->qphy;
> + dp_opts = &qphy->dp_opts;
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + return 1620000000UL / 2;
> + case 2700:
> + return 2700000000UL / 2;
> + case 5400:
> + return 5400000000UL / 4;
> + case 8100:
> + return 8100000000UL / 6;
> + default:
> + return 0;
> + }
> +}
> +
> +static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
> + .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
> + .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
> +};
> +
> +static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + switch (req->rate) {
> + case 162000000:
> + case 270000000:
> + case 540000000:
> + case 810000000:
> + return 0;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static unsigned long
> +qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + const struct qmp_phy_dp_clks *dp_clks;
> + const struct qmp_phy *qphy;
> + const struct phy_configure_opts_dp *dp_opts;
> +
> + dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
> + qphy = dp_clks->qphy;
> + dp_opts = &qphy->dp_opts;
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + case 2700:
> + case 5400:
> + case 8100:
> + return dp_opts->link_rate * 100000;
> + default:
> + return 0;
> + }
> +}
> +
> +static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
> + .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
> + .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
> +};
> +
> +static struct clk_hw *
> +qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
> +{
> + struct qmp_phy_dp_clks *dp_clks = data;
> + unsigned int idx = clkspec->args[0];
> +
> + if (idx >= 2) {
> + pr_err("%s: invalid index %u\n", __func__, idx);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + if (idx == 0)
> + return &dp_clks->dp_link_hw;
> +
> + return &dp_clks->dp_pixel_hw;
> +}
> +
> +static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
> + struct device_node *np)
> +{
> + struct clk_init_data init = { };
> + struct qmp_phy_dp_clks *dp_clks;
> + char name[64];
> + int ret;
> +
> + dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
> + if (!dp_clks)
> + return -ENOMEM;
> +
> + dp_clks->qphy = qphy;
> + qphy->dp_clks = dp_clks;
> +
> + snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
> + init.ops = &qcom_qmp_dp_link_clk_ops;
> + init.name = name;
> + dp_clks->dp_link_hw.init = &init;
> + ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
> + if (ret)
> + return ret;
> +
> + snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
> + init.ops = &qcom_qmp_dp_pixel_clk_ops;
> + init.name = name;
> + dp_clks->dp_pixel_hw.init = &init;
> + ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
> + if (ret)
> + return ret;
> +
> + ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
> + if (ret)
> + return ret;
> +
> + /*
> + * Roll a devm action because the clock provider is the child node, but
> + * the child node is not actually a device.
> + */
> + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
> +}
> +
> +static const struct phy_ops qcom_qmp_phy_gen_ops = {
> + .init = qcom_qmp_phy_enable,
> + .exit = qcom_qmp_phy_disable,
> + .set_mode = qcom_qmp_phy_set_mode,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct phy_ops qcom_qmp_phy_dp_ops = {
> + .init = qcom_qmp_phy_init,
> + .configure = qcom_qmp_dp_phy_configure,
> + .power_on = qcom_qmp_phy_power_on,
> + .calibrate = qcom_qmp_dp_phy_calibrate,
> + .power_off = qcom_qmp_phy_power_off,
> + .exit = qcom_qmp_phy_exit,
> + .set_mode = qcom_qmp_phy_set_mode,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
> + .power_on = qcom_qmp_phy_enable,
> + .power_off = qcom_qmp_phy_disable,
> + .set_mode = qcom_qmp_phy_set_mode,
> + .owner = THIS_MODULE,
> +};
> +
> +static void qcom_qmp_reset_control_put(void *data)
> +{
> + reset_control_put(data);
> +}
> +
> +static
> +int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
> + void __iomem *serdes, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + struct phy *generic_phy;
> + struct qmp_phy *qphy;
> + const struct phy_ops *ops;
> + char prop_name[MAX_PROP_NAME];
> + int ret;
> +
> + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
> + if (!qphy)
> + return -ENOMEM;
> +
> + qphy->cfg = cfg;
> + qphy->serdes = serdes;
> + /*
> + * Get memory resources for each phy lane:
> + * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
> + * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
> + * For single lane PHYs: pcs_misc (optional) -> 3.
> + */
> + qphy->tx = of_iomap(np, 0);
> + if (!qphy->tx)
> + return -ENOMEM;
> +
> + qphy->rx = of_iomap(np, 1);
> + if (!qphy->rx)
> + return -ENOMEM;
> +
> + qphy->pcs = of_iomap(np, 2);
> + if (!qphy->pcs)
> + return -ENOMEM;
> +
> + /*
> + * If this is a dual-lane PHY, then there should be registers for the
> + * second lane. Some old device trees did not specify this, so fall
> + * back to old legacy behavior of assuming they can be reached at an
> + * offset from the first lane.
> + */
> + if (cfg->is_dual_lane_phy) {
> + qphy->tx2 = of_iomap(np, 3);
> + qphy->rx2 = of_iomap(np, 4);
> + if (!qphy->tx2 || !qphy->rx2) {
> + dev_warn(dev,
> + "Underspecified device tree, falling back to legacy register regions\n");
> +
> + /* In the old version, pcs_misc is at index 3. */
> + qphy->pcs_misc = qphy->tx2;
> + qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
> + qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
> +
> + } else {
> + qphy->pcs_misc = of_iomap(np, 5);
> + }
> +
> + } else {
> + qphy->pcs_misc = of_iomap(np, 3);
> + }
> +
> + if (!qphy->pcs_misc)
> + dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
> +
> + /*
> + * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
> + * based phys, so they essentially have pipe clock. So,
> + * we return error in case phy is USB3 or PIPE type.
> + * Otherwise, we initialize pipe clock to NULL for
> + * all phys that don't need this.
> + */
> + snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
> + qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
> + if (IS_ERR(qphy->pipe_clk)) {
> + if (cfg->type == PHY_TYPE_PCIE ||
> + cfg->type == PHY_TYPE_USB3) {
> + ret = PTR_ERR(qphy->pipe_clk);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev,
> + "failed to get lane%d pipe_clk, %d\n",
> + id, ret);
> + return ret;
> + }
> + qphy->pipe_clk = NULL;
> + }
> +
> + /* Get lane reset, if any */
> + if (cfg->has_lane_rst) {
> + snprintf(prop_name, sizeof(prop_name), "lane%d", id);
> + qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
> + if (IS_ERR(qphy->lane_rst)) {
> + dev_err(dev, "failed to get lane%d reset\n", id);
> + return PTR_ERR(qphy->lane_rst);
> + }
> + ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
> + qphy->lane_rst);
> + if (ret)
> + return ret;
> + }
> +
> + if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
> + ops = &qcom_qmp_pcie_ufs_ops;
> + else if (cfg->type == PHY_TYPE_DP)
> + ops = &qcom_qmp_phy_dp_ops;
> + else
> + ops = &qcom_qmp_phy_gen_ops;
> +
> + generic_phy = devm_phy_create(dev, np, ops);
> + if (IS_ERR(generic_phy)) {
> + ret = PTR_ERR(generic_phy);
> + dev_err(dev, "failed to create qphy %d\n", ret);
> + return ret;
> + }
> +
> + qphy->phy = generic_phy;
> + qphy->index = id;
> + qphy->qmp = qmp;
> + qmp->phys[id] = qphy;
> + phy_set_drvdata(generic_phy, qphy);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
> + {
> + .compatible = "qcom,ipq8074-qmp-usb3-phy",
> + .data = &ipq8074_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,msm8996-qmp-pcie-phy",
> + .data = &msm8996_pciephy_cfg,
> + }, {
> + .compatible = "qcom,msm8996-qmp-ufs-phy",
> + .data = &msm8996_ufs_cfg,
> + }, {
> + .compatible = "qcom,msm8996-qmp-usb3-phy",
> + .data = &msm8996_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,msm8998-qmp-pcie-phy",
> + .data = &msm8998_pciephy_cfg,
> + }, {
> + .compatible = "qcom,msm8998-qmp-ufs-phy",
> + .data = &sdm845_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,ipq8074-qmp-pcie-phy",
> + .data = &ipq8074_pciephy_cfg,
> + }, {
> + .compatible = "qcom,ipq6018-qmp-pcie-phy",
> + .data = &ipq6018_pciephy_cfg,
> + }, {
> + .compatible = "qcom,ipq6018-qmp-usb3-phy",
> + .data = &ipq8074_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sc7180-qmp-usb3-phy",
> + .data = &sc7180_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
> + /* It's a combo phy */
> + }, {
> + .compatible = "qcom,sc8180x-qmp-pcie-phy",
> + .data = &sc8180x_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sc8180x-qmp-ufs-phy",
> + .data = &sm8150_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sc8280xp-qmp-ufs-phy",
> + .data = &sm8350_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sc8180x-qmp-usb3-phy",
> + .data = &sm8150_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
> + /* It's a combo phy */
> + }, {
> + .compatible = "qcom,sdm845-qhp-pcie-phy",
> + .data = &sdm845_qhp_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-pcie-phy",
> + .data = &sdm845_qmp_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-usb3-phy",
> + .data = &qmp_v3_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
> + .data = &qmp_v3_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-ufs-phy",
> + .data = &sdm845_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,msm8998-qmp-usb3-phy",
> + .data = &msm8998_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm6115-qmp-ufs-phy",
> + .data = &sm6115_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm6350-qmp-ufs-phy",
> + .data = &sdm845_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8150-qmp-ufs-phy",
> + .data = &sm8150_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-ufs-phy",
> + .data = &sm8150_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8150-qmp-usb3-phy",
> + .data = &sm8150_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
> + .data = &sm8150_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-usb3-phy",
> + .data = &sm8250_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
> + /* It's a combo phy */
> + }, {
> + .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
> + .data = &sm8250_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
> + .data = &sm8250_qmp_gen3x1_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
> + .data = &sm8250_qmp_gen3x2_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8350-qmp-ufs-phy",
> + .data = &sm8350_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
> + .data = &sm8250_qmp_gen3x2_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdx55-qmp-pcie-phy",
> + .data = &sdx55_qmp_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
> + .data = &sdx55_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
> + .data = &sdx65_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8350-qmp-usb3-phy",
> + .data = &sm8350_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
> + .data = &sm8350_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
> + .data = &sm8450_qmp_gen3x1_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
> + .data = &sm8450_qmp_gen4x2_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-ufs-phy",
> + .data = &sm8450_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-usb3-phy",
> + .data = &sm8350_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,qcm2290-qmp-usb3-phy",
> + .data = &qcm2290_usb3phy_cfg,
> + },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
> +
> +static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
> + {
> + .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
> + .data = &sc7180_usb3dpphy_cfg,
> + },
> + {
> + .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
> + .data = &sm8250_usb3dpphy_cfg,
> + },
> + {
> + .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
> + .data = &sc8180x_usb3dpphy_cfg,
> + },
> + { }
> +};
> +
> +static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
> + SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
> + qcom_qmp_phy_runtime_resume, NULL)
> +};
> +
> +static int qcom_qmp_phy_probe(struct platform_device *pdev)
> +{
> + struct qcom_qmp *qmp;
> + struct device *dev = &pdev->dev;
> + struct device_node *child;
> + struct phy_provider *phy_provider;
> + void __iomem *serdes;
> + void __iomem *usb_serdes;
> + void __iomem *dp_serdes = NULL;
> + const struct qmp_phy_combo_cfg *combo_cfg = NULL;
> + const struct qmp_phy_cfg *cfg = NULL;
> + const struct qmp_phy_cfg *usb_cfg = NULL;
> + const struct qmp_phy_cfg *dp_cfg = NULL;
> + int num, id, expected_phys;
> + int ret;
> +
> + qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
> + if (!qmp)
> + return -ENOMEM;
> +
> + qmp->dev = dev;
> + dev_set_drvdata(dev, qmp);
> +
> + /* Get the specific init parameters of QMP phy */
> + cfg = of_device_get_match_data(dev);
> + if (!cfg) {
> + const struct of_device_id *match;
> +
> + match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
> + if (!match)
> + return -EINVAL;
> +
> + combo_cfg = match->data;
> + if (!combo_cfg)
> + return -EINVAL;
> +
> + usb_cfg = combo_cfg->usb_cfg;
> + cfg = usb_cfg; /* Setup clks and regulators */
> + }
> +
> + /* per PHY serdes; usually located at base address */
> + usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(serdes))
> + return PTR_ERR(serdes);
> +
> + /* per PHY dp_com; if PHY has dp_com control block */
> + if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
> + qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
> + if (IS_ERR(qmp->dp_com))
> + return PTR_ERR(qmp->dp_com);
> + }
> +
> + if (combo_cfg) {
> + /* Only two serdes for combo PHY */
> + dp_serdes = devm_platform_ioremap_resource(pdev, 2);
> + if (IS_ERR(dp_serdes))
> + return PTR_ERR(dp_serdes);
> +
> + dp_cfg = combo_cfg->dp_cfg;
> + expected_phys = 2;
> + } else {
> + expected_phys = cfg->nlanes;
> + }
> +
> + mutex_init(&qmp->phy_mutex);
> +
> + ret = qcom_qmp_phy_clk_init(dev, cfg);
> + if (ret)
> + return ret;
> +
> + ret = qcom_qmp_phy_reset_init(dev, cfg);
> + if (ret)
> + return ret;
> +
> + ret = qcom_qmp_phy_vreg_init(dev, cfg);
> + if (ret) {
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "failed to get regulator supplies: %d\n",
> + ret);
> + return ret;
> + }
> +
> + num = of_get_available_child_count(dev->of_node);
> + /* do we have a rogue child node ? */
> + if (num > expected_phys)
> + return -EINVAL;
> +
> + qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
> + if (!qmp->phys)
> + return -ENOMEM;
> +
> + pm_runtime_set_active(dev);
> + pm_runtime_enable(dev);
> + /*
> + * Prevent runtime pm from being ON by default. Users can enable
> + * it using power/control in sysfs.
> + */
> + pm_runtime_forbid(dev);
> +
> + id = 0;
> + for_each_available_child_of_node(dev->of_node, child) {
> + if (of_node_name_eq(child, "dp-phy")) {
> + cfg = dp_cfg;
> + serdes = dp_serdes;
> + } else if (of_node_name_eq(child, "usb3-phy")) {
> + cfg = usb_cfg;
> + serdes = usb_serdes;
> + }
> +
> + /* Create per-lane phy */
> + ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
> + if (ret) {
> + dev_err(dev, "failed to create lane%d phy, %d\n",
> + id, ret);
> + goto err_node_put;
> + }
> +
> + /*
> + * Register the pipe clock provided by phy.
> + * See function description to see details of this pipe clock.
> + */
> + if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
> + ret = phy_pipe_clk_register(qmp, child);
> + if (ret) {
> + dev_err(qmp->dev,
> + "failed to register pipe clock source\n");
> + goto err_node_put;
> + }
> + } else if (cfg->type == PHY_TYPE_DP) {
> + ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
> + if (ret) {
> + dev_err(qmp->dev,
> + "failed to register DP clock source\n");
> + goto err_node_put;
> + }
> + }
> + id++;
> + }
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (!IS_ERR(phy_provider))
> + dev_info(dev, "Registered Qcom-QMP phy\n");
> + else
> + pm_runtime_disable(dev);
> +
> + return PTR_ERR_OR_ZERO(phy_provider);
> +
> +err_node_put:
> + pm_runtime_disable(dev);
> + of_node_put(child);
> + return ret;
> +}
> +
> +static struct platform_driver qcom_qmp_phy_driver = {
> + .probe = qcom_qmp_phy_probe,
> + .driver = {
> + .name = "qcom-qmp-phy",
> + .pm = &qcom_qmp_phy_pm_ops,
> + .of_match_table = qcom_qmp_phy_of_match_table,
> + },
> +};
> +
> +module_platform_driver(qcom_qmp_phy_driver);
> +
> +MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
> +MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> new file mode 100644
> index 000000000000..c7309e981bfb
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -0,0 +1,6350 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2017, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +
> +#include <dt-bindings/phy/phy.h>
> +
> +#include "phy-qcom-qmp.h"
> +
> +/* QPHY_SW_RESET bit */
> +#define SW_RESET BIT(0)
> +/* QPHY_POWER_DOWN_CONTROL */
> +#define SW_PWRDN BIT(0)
> +#define REFCLK_DRV_DSBL BIT(1)
> +/* QPHY_START_CONTROL bits */
> +#define SERDES_START BIT(0)
> +#define PCS_START BIT(1)
> +#define PLL_READY_GATE_EN BIT(3)
> +/* QPHY_PCS_STATUS bit */
> +#define PHYSTATUS BIT(6)
> +#define PHYSTATUS_4_20 BIT(7)
> +/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
> +#define PCS_READY BIT(0)
> +
> +/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
> +/* DP PHY soft reset */
> +#define SW_DPPHY_RESET BIT(0)
> +/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
> +#define SW_DPPHY_RESET_MUX BIT(1)
> +/* USB3 PHY soft reset */
> +#define SW_USB3PHY_RESET BIT(2)
> +/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
> +#define SW_USB3PHY_RESET_MUX BIT(3)
> +
> +/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
> +#define USB3_MODE BIT(0) /* enables USB3 mode */
> +#define DP_MODE BIT(1) /* enables DP mode */
> +
> +/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
> +#define ARCVR_DTCT_EN BIT(0)
> +#define ALFPS_DTCT_EN BIT(1)
> +#define ARCVR_DTCT_EVENT_SEL BIT(4)
> +
> +/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
> +#define IRQ_CLEAR BIT(0)
> +
> +/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
> +#define RCVR_DETECT BIT(0)
> +
> +/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
> +#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
> +
> +#define PHY_INIT_COMPLETE_TIMEOUT 10000
> +#define POWER_DOWN_DELAY_US_MIN 10
> +#define POWER_DOWN_DELAY_US_MAX 11
> +
> +#define MAX_PROP_NAME 32
> +
> +/* Define the assumed distance between lanes for underspecified device trees. */
> +#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
> +
> +struct qmp_phy_init_tbl {
> + unsigned int offset;
> + unsigned int val;
> + /*
> + * register part of layout ?
> + * if yes, then offset gives index in the reg-layout
> + */
> + bool in_layout;
> + /*
> + * mask of lanes for which this register is written
> + * for cases when second lane needs different values
> + */
> + u8 lane_mask;
> +};
> +
> +#define QMP_PHY_INIT_CFG(o, v) \
> + { \
> + .offset = o, \
> + .val = v, \
> + .lane_mask = 0xff, \
> + }
> +
> +#define QMP_PHY_INIT_CFG_L(o, v) \
> + { \
> + .offset = o, \
> + .val = v, \
> + .in_layout = true, \
> + .lane_mask = 0xff, \
> + }
> +
> +#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
> + { \
> + .offset = o, \
> + .val = v, \
> + .lane_mask = l, \
> + }
> +
> +/* set of registers with offsets different per-PHY */
> +enum qphy_reg_layout {
> + /* Common block control registers */
> + QPHY_COM_SW_RESET,
> + QPHY_COM_POWER_DOWN_CONTROL,
> + QPHY_COM_START_CONTROL,
> + QPHY_COM_PCS_READY_STATUS,
> + /* PCS registers */
> + QPHY_PLL_LOCK_CHK_DLY_TIME,
> + QPHY_FLL_CNTRL1,
> + QPHY_FLL_CNTRL2,
> + QPHY_FLL_CNT_VAL_L,
> + QPHY_FLL_CNT_VAL_H_TOL,
> + QPHY_FLL_MAN_CODE,
> + QPHY_SW_RESET,
> + QPHY_START_CTRL,
> + QPHY_PCS_READY_STATUS,
> + QPHY_PCS_STATUS,
> + QPHY_PCS_AUTONOMOUS_MODE_CTRL,
> + QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
> + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
> + QPHY_PCS_POWER_DOWN_CONTROL,
> + /* PCS_MISC registers */
> + QPHY_PCS_MISC_TYPEC_CTRL,
> + /* Keep last to ensure regs_layout arrays are properly initialized */
> + QPHY_LAYOUT_SIZE
> +};
> +
> +static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = 0x00,
> + [QPHY_PCS_READY_STATUS] = 0x168,
> +};
> +
> +static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> +};
> +
> +static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_COM_SW_RESET] = 0x400,
> + [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
> + [QPHY_COM_START_CONTROL] = 0x408,
> + [QPHY_COM_PCS_READY_STATUS] = 0x448,
> + [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
> + [QPHY_FLL_CNTRL1] = 0xc4,
> + [QPHY_FLL_CNTRL2] = 0xc8,
> + [QPHY_FLL_CNT_VAL_L] = 0xcc,
> + [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
> + [QPHY_FLL_MAN_CODE] = 0xd4,
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x174,
> +};
> +
> +static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_FLL_CNTRL1] = 0xc0,
> + [QPHY_FLL_CNTRL2] = 0xc4,
> + [QPHY_FLL_CNT_VAL_L] = 0xc8,
> + [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
> + [QPHY_FLL_MAN_CODE] = 0xd0,
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x17c,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
> +};
> +
> +static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x174,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
> +};
> +
> +static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x174,
> +};
> +
> +static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x2ac,
> +};
> +
> +static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
> +};
> +
> +static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
> +};
> +
> +static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
> +};
> +
> +static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
> + [QPHY_PCS_STATUS] = 0x174,
> + [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
> +};
> +
> +static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = 0x00,
> + [QPHY_PCS_READY_STATUS] = 0x160,
> +};
> +
> +static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = 0x00,
> + [QPHY_PCS_READY_STATUS] = 0x168,
> +};
> +
> +static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> +};
> +
> +static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
> + [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
> + [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + /* PLL and Loop filter settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + /* SSC settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
> + QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
> +
> + QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
> +
> + QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
> + QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
> + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
> + /* PLL and Loop filter settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + /* SSC settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
> + /* FLL settings */
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
> +
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
> + QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
> + QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
> + QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
> + QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
> + QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
> + QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
> + QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> + QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
> + QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
> + QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
> + QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
> + QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
> + QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
> + QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
> + QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
> + QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
> + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
> + QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
> + QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
> + /* FLL settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> +
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
> + /* FLL settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> +
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
> + QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
> + QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
> + QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
> +
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> +
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
> +};
> +
> +/* Register names should be validated, they might be different for this PHY */
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
> +};
> +
> +struct qmp_phy;
> +
> +/* struct qmp_phy_cfg - per-PHY initialization config */
> +struct qmp_phy_cfg {
> + /* phy-type - PCIE/UFS/USB */
> + unsigned int type;
> + /* number of lanes provided by phy */
> + int nlanes;
> +
> + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
> + const struct qmp_phy_init_tbl *serdes_tbl;
> + int serdes_tbl_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_sec;
> + int serdes_tbl_num_sec;
> + const struct qmp_phy_init_tbl *tx_tbl;
> + int tx_tbl_num;
> + const struct qmp_phy_init_tbl *tx_tbl_sec;
> + int tx_tbl_num_sec;
> + const struct qmp_phy_init_tbl *rx_tbl;
> + int rx_tbl_num;
> + const struct qmp_phy_init_tbl *rx_tbl_sec;
> + int rx_tbl_num_sec;
> + const struct qmp_phy_init_tbl *pcs_tbl;
> + int pcs_tbl_num;
> + const struct qmp_phy_init_tbl *pcs_tbl_sec;
> + int pcs_tbl_num_sec;
> + const struct qmp_phy_init_tbl *pcs_misc_tbl;
> + int pcs_misc_tbl_num;
> + const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
> + int pcs_misc_tbl_num_sec;
> +
> + /* Init sequence for DP PHY block link rates */
> + const struct qmp_phy_init_tbl *serdes_tbl_rbr;
> + int serdes_tbl_rbr_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_hbr;
> + int serdes_tbl_hbr_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
> + int serdes_tbl_hbr2_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
> + int serdes_tbl_hbr3_num;
> +
> + /* DP PHY callbacks */
> + int (*configure_dp_phy)(struct qmp_phy *qphy);
> + void (*configure_dp_tx)(struct qmp_phy *qphy);
> + int (*calibrate_dp_phy)(struct qmp_phy *qphy);
> + void (*dp_aux_init)(struct qmp_phy *qphy);
> +
> + /* clock ids to be requested */
> + const char * const *clk_list;
> + int num_clks;
> + /* resets to be requested */
> + const char * const *reset_list;
> + int num_resets;
> + /* regulators to be requested */
> + const char * const *vreg_list;
> + int num_vregs;
> +
> + /* array of registers with different offsets */
> + const unsigned int *regs;
> +
> + unsigned int start_ctrl;
> + unsigned int pwrdn_ctrl;
> + unsigned int mask_com_pcs_ready;
> + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
> + unsigned int phy_status;
> +
> + /* true, if PHY has a separate PHY_COM control block */
> + bool has_phy_com_ctrl;
> + /* true, if PHY has a reset for individual lanes */
> + bool has_lane_rst;
> + /* true, if PHY needs delay after POWER_DOWN */
> + bool has_pwrdn_delay;
> + /* power_down delay in usec */
> + int pwrdn_delay_min;
> + int pwrdn_delay_max;
> +
> + /* true, if PHY has a separate DP_COM control block */
> + bool has_phy_dp_com_ctrl;
> + /* true, if PHY has secondary tx/rx lanes to be configured */
> + bool is_dual_lane_phy;
> +
> + /* true, if PCS block has no separate SW_RESET register */
> + bool no_pcs_sw_reset;
> +};
> +
> +struct qmp_phy_combo_cfg {
> + const struct qmp_phy_cfg *usb_cfg;
> + const struct qmp_phy_cfg *dp_cfg;
> +};
> +
> +/**
> + * struct qmp_phy - per-lane phy descriptor
> + *
> + * @phy: generic phy
> + * @cfg: phy specific configuration
> + * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
> + * @tx: iomapped memory space for lane's tx
> + * @rx: iomapped memory space for lane's rx
> + * @pcs: iomapped memory space for lane's pcs
> + * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
> + * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
> + * @pcs_misc: iomapped memory space for lane's pcs_misc
> + * @pipe_clk: pipe clock
> + * @index: lane index
> + * @qmp: QMP phy to which this lane belongs
> + * @lane_rst: lane's reset controller
> + * @mode: current PHY mode
> + * @dp_aux_cfg: Display port aux config
> + * @dp_opts: Display port optional config
> + * @dp_clks: Display port clocks
> + */
> +struct qmp_phy {
> + struct phy *phy;
> + const struct qmp_phy_cfg *cfg;
> + void __iomem *serdes;
> + void __iomem *tx;
> + void __iomem *rx;
> + void __iomem *pcs;
> + void __iomem *tx2;
> + void __iomem *rx2;
> + void __iomem *pcs_misc;
> + struct clk *pipe_clk;
> + unsigned int index;
> + struct qcom_qmp *qmp;
> + struct reset_control *lane_rst;
> + enum phy_mode mode;
> + unsigned int dp_aux_cfg;
> + struct phy_configure_opts_dp dp_opts;
> + struct qmp_phy_dp_clks *dp_clks;
> +};
> +
> +struct qmp_phy_dp_clks {
> + struct qmp_phy *qphy;
> + struct clk_hw dp_link_hw;
> + struct clk_hw dp_pixel_hw;
> +};
> +
> +/**
> + * struct qcom_qmp - structure holding QMP phy block attributes
> + *
> + * @dev: device
> + * @dp_com: iomapped memory space for phy's dp_com control block
> + *
> + * @clks: array of clocks required by phy
> + * @resets: array of resets required by phy
> + * @vregs: regulator supplies bulk data
> + *
> + * @phys: array of per-lane phy descriptors
> + * @phy_mutex: mutex lock for PHY common block initialization
> + * @init_count: phy common block initialization count
> + * @ufs_reset: optional UFS PHY reset handle
> + */
> +struct qcom_qmp {
> + struct device *dev;
> + void __iomem *dp_com;
> +
> + struct clk_bulk_data *clks;
> + struct reset_control **resets;
> + struct regulator_bulk_data *vregs;
> +
> + struct qmp_phy **phys;
> +
> + struct mutex phy_mutex;
> + int init_count;
> +
> + struct reset_control *ufs_reset;
> +};
> +
> +static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
> +static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
> +static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
> +static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
> +
> +static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
> +static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
> +static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
> +static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
> +
> +static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
> +{
> + u32 reg;
> +
> + reg = readl(base + offset);
> + reg |= val;
> + writel(reg, base + offset);
> +
> + /* ensure that above write is through */
> + readl(base + offset);
> +}
> +
> +static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
> +{
> + u32 reg;
> +
> + reg = readl(base + offset);
> + reg &= ~val;
> + writel(reg, base + offset);
> +
> + /* ensure that above write is through */
> + readl(base + offset);
> +}
> +
> +/* list of clocks required by phy */
> +static const char * const msm8996_phy_clk_l[] = {
> + "aux", "cfg_ahb", "ref",
> +};
> +
> +static const char * const msm8996_ufs_phy_clk_l[] = {
> + "ref",
> +};
> +
> +static const char * const qmp_v3_phy_clk_l[] = {
> + "aux", "cfg_ahb", "ref", "com_aux",
> +};
> +
> +static const char * const sdm845_pciephy_clk_l[] = {
> + "aux", "cfg_ahb", "ref", "refgen",
> +};
> +
> +static const char * const qmp_v4_phy_clk_l[] = {
> + "aux", "ref_clk_src", "ref", "com_aux",
> +};
> +
> +/* the primary usb3 phy on sm8250 doesn't have a ref clock */
> +static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
> + "aux", "ref_clk_src", "com_aux"
> +};
> +
> +static const char * const sm8450_ufs_phy_clk_l[] = {
> + "qref", "ref", "ref_aux",
> +};
> +
> +static const char * const sdm845_ufs_phy_clk_l[] = {
> + "ref", "ref_aux",
> +};
> +
> +/* usb3 phy on sdx55 doesn't have com_aux clock */
> +static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
> + "aux", "cfg_ahb", "ref"
> +};
> +
> +static const char * const qcm2290_usb3phy_clk_l[] = {
> + "cfg_ahb", "ref", "com_aux",
> +};
> +
> +/* list of resets */
> +static const char * const msm8996_pciephy_reset_l[] = {
> + "phy", "common", "cfg",
> +};
> +
> +static const char * const msm8996_usb3phy_reset_l[] = {
> + "phy", "common",
> +};
> +
> +static const char * const sc7180_usb3phy_reset_l[] = {
> + "phy",
> +};
> +
> +static const char * const qcm2290_usb3phy_reset_l[] = {
> + "phy_phy", "phy",
> +};
> +
> +static const char * const sdm845_pciephy_reset_l[] = {
> + "phy",
> +};
> +
> +/* list of regulators */
> +static const char * const qmp_phy_vreg_l[] = {
> + "vdda-phy", "vdda-pll",
> +};
> +
> +static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = ipq8074_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
> + .tx_tbl = msm8996_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
> + .rx_tbl = ipq8074_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
> + .pcs_tbl = ipq8074_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +};
> +
> +static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 3,
> +
> + .serdes_tbl = msm8996_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
> + .tx_tbl = msm8996_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
> + .rx_tbl = msm8996_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
> + .pcs_tbl = msm8996_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = pciephy_regs_layout,
> +
> + .start_ctrl = PCS_START | PLL_READY_GATE_EN,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .mask_com_pcs_ready = PCS_READY,
> + .phy_status = PHYSTATUS,
> +
> + .has_phy_com_ctrl = true,
> + .has_lane_rst = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg msm8996_ufs_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8996_ufs_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
> + .tx_tbl = msm8996_ufs_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
> + .rx_tbl = msm8996_ufs_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
> +
> + .clk_list = msm8996_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
> +
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> +
> + .regs = msm8996_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .no_pcs_sw_reset = true,
> +};
> +
> +static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8996_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
> + .tx_tbl = msm8996_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
> + .rx_tbl = msm8996_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
> + .pcs_tbl = msm8996_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +};
> +
> +static const char * const ipq8074_pciephy_clk_l[] = {
> + "aux", "cfg_ahb",
> +};
> +/* list of resets */
> +static const char * const ipq8074_pciephy_reset_l[] = {
> + "phy", "common",
> +};
> +
> +static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = ipq8074_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
> + .tx_tbl = ipq8074_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
> + .rx_tbl = ipq8074_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
> + .pcs_tbl = ipq8074_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
> + .clk_list = ipq8074_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
> + .reset_list = ipq8074_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
> + .vreg_list = NULL,
> + .num_vregs = 0,
> + .regs = pciephy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_phy_com_ctrl = false,
> + .has_lane_rst = false,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = ipq6018_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
> + .tx_tbl = ipq6018_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
> + .rx_tbl = ipq6018_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
> + .pcs_tbl = ipq6018_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
> + .clk_list = ipq8074_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
> + .reset_list = ipq8074_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
> + .vreg_list = NULL,
> + .num_vregs = 0,
> + .regs = ipq_pciephy_gen3_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> +
> + .has_phy_com_ctrl = false,
> + .has_lane_rst = false,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
> + .tx_tbl = sdm845_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
> + .rx_tbl = sdm845_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
> + .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
> + .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sdm845_qmp_pciephy_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
> + .tx_tbl = sdm845_qhp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
> + .rx_tbl = sdm845_qhp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
> + .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sdm845_qhp_pciephy_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
> + .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
> + .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
> + .tx_tbl = sm8250_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
> + .rx_tbl = sm8250_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
> + .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
> + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
> + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
> + .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
> + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
> + .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
> + .tx_tbl = sm8250_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
> + .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
> + .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
> + .rx_tbl = sm8250_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
> + .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
> + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
> + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
> + .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
> + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
> + .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
> + .tx_tbl = qmp_v3_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
> + .rx_tbl = qmp_v3_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
> + .pcs_tbl = qmp_v3_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
> + .tx_tbl = qmp_v3_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
> + .rx_tbl = qmp_v3_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
> + .pcs_tbl = qmp_v3_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = sc7180_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
> + .type = PHY_TYPE_DP,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_dp_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
> + .tx_tbl = qmp_v3_dp_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
> +
> + .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
> + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
> + .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
> + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
> + .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
> + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
> + .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
> + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
> +
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = sc7180_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +
> + .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
> + .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
> + .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
> + .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
> +};
> +
> +static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
> + .usb_cfg = &sc7180_usb3phy_cfg,
> + .dp_cfg = &sc7180_dpphy_cfg,
> +};
> +
> +static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
> + .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
> + .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
> + .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sdm845_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
> + .tx_tbl = sdm845_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
> + .rx_tbl = sdm845_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
> + .pcs_tbl = sdm845_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sdm845_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> + .no_pcs_sw_reset = true,
> +};
> +
> +static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm6115_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
> + .tx_tbl = sm6115_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
> + .rx_tbl = sm6115_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
> + .pcs_tbl = sm6115_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm6115_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> +
> + .is_dual_lane_phy = false,
> + .no_pcs_sw_reset = true,
> +};
> +
> +static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8998_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
> + .tx_tbl = msm8998_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
> + .rx_tbl = msm8998_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
> + .pcs_tbl = msm8998_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = ipq8074_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = pciephy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +};
> +
> +static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8998_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
> + .tx_tbl = msm8998_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
> + .rx_tbl = msm8998_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
> + .pcs_tbl = msm8998_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8150_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
> + .tx_tbl = sm8150_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
> + .rx_tbl = sm8150_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
> + .pcs_tbl = sm8150_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8150_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
> + .tx_tbl = sm8150_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
> + .rx_tbl = sm8150_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
> + .pcs_tbl = sm8150_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
> + .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
> + .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
> + .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
> + .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
> + .type = PHY_TYPE_DP,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v4_dp_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
> + .tx_tbl = qmp_v4_dp_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
> +
> + .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
> + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
> + .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
> + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
> + .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
> + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
> + .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
> + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
> +
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = sc7180_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +
> + .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
> + .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
> + .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
> + .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
> +};
> +
> +static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
> + .usb_cfg = &sm8150_usb3phy_cfg,
> + .dp_cfg = &sc8180x_dpphy_cfg,
> +};
> +
> +static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
> + .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
> + .tx_tbl = sm8250_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
> + .rx_tbl = sm8250_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
> + .pcs_tbl = sm8250_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
> + .clk_list = qmp_v4_sm8250_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
> + .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
> + .type = PHY_TYPE_DP,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v4_dp_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
> + .tx_tbl = qmp_v4_dp_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
> +
> + .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
> + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
> + .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
> + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
> + .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
> + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
> + .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
> + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
> +
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +
> + .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
> + .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
> + .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
> + .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
> +};
> +
> +static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
> + .usb_cfg = &sm8250_usb3phy_cfg,
> + .dp_cfg = &sm8250_dpphy_cfg,
> +};
> +
> +static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
> + .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_sdx55_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 2,
> +
> + .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
> + .tx_tbl = sdx55_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
> + .rx_tbl = sdx55_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
> + .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
> + .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS_4_20,
> +
> + .is_dual_lane_phy = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
> + .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_sdx55_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8350_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8350_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
> + .tx_tbl = sm8350_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
> + .rx_tbl = sm8350_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
> + .pcs_tbl = sm8350_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8150_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
> + .tx_tbl = sm8350_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
> + .rx_tbl = sm8350_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
> + .pcs_tbl = sm8350_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
> + .clk_list = qmp_v4_sm8250_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
> + .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8350_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8350_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
> + .tx_tbl = sm8350_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
> + .rx_tbl = sm8350_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
> + .pcs_tbl = sm8350_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
> + .clk_list = sm8450_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8150_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
> + .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
> + .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
> + .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
> + .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
> + .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
> + .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS_4_20,
> +
> + .is_dual_lane_phy = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qcm2290_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
> + .tx_tbl = qcm2290_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
> + .rx_tbl = qcm2290_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
> + .pcs_tbl = qcm2290_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
> + .clk_list = qcm2290_usb3phy_clk_l,
> + .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
> + .reset_list = qcm2290_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qcm2290_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static void qcom_qmp_phy_configure_lane(void __iomem *base,
> + const unsigned int *regs,
> + const struct qmp_phy_init_tbl tbl[],
> + int num,
> + u8 lane_mask)
> +{
> + int i;
> + const struct qmp_phy_init_tbl *t = tbl;
> +
> + if (!t)
> + return;
> +
> + for (i = 0; i < num; i++, t++) {
> + if (!(t->lane_mask & lane_mask))
> + continue;
> +
> + if (t->in_layout)
> + writel(t->val, base + regs[t->offset]);
> + else
> + writel(t->val, base + t->offset);
> + }
> +}
> +
> +static void qcom_qmp_phy_configure(void __iomem *base,
> + const unsigned int *regs,
> + const struct qmp_phy_init_tbl tbl[],
> + int num)
> +{
> + qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
> +}
> +
> +static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
> +{
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
> + int serdes_tbl_num = cfg->serdes_tbl_num;
> + int ret;
> +
> + qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
> + if (cfg->serdes_tbl_sec)
> + qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
> + cfg->serdes_tbl_num_sec);
> +
> + if (cfg->type == PHY_TYPE_DP) {
> + switch (dp_opts->link_rate) {
> + case 1620:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_rbr,
> + cfg->serdes_tbl_rbr_num);
> + break;
> + case 2700:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_hbr,
> + cfg->serdes_tbl_hbr_num);
> + break;
> + case 5400:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_hbr2,
> + cfg->serdes_tbl_hbr2_num);
> + break;
> + case 8100:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_hbr3,
> + cfg->serdes_tbl_hbr3_num);
> + break;
> + default:
> + /* Other link rates aren't supported */
> + return -EINVAL;
> + }
> + }
> +
> +
> + if (cfg->has_phy_com_ctrl) {
> + void __iomem *status;
> + unsigned int mask, val;
> +
> + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
> + SERDES_START | PCS_START);
> +
> + status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
> + mask = cfg->mask_com_pcs_ready;
> +
> + ret = readl_poll_timeout(status, val, (val & mask), 10,
> + PHY_INIT_COMPLETE_TIMEOUT);
> + if (ret) {
> + dev_err(qmp->dev,
> + "phy common block init timed-out\n");
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
> +{
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
> + qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + /* Turn on BIAS current for PHY/PLL */
> + writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
> + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
> + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
> +
> + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_LANE_0_1_PWRDN |
> + DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
> + DP_PHY_PD_CTL_DP_CLAMP_EN,
> + qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + writel(QSERDES_V3_COM_BIAS_EN |
> + QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
> + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
> + QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
> + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
> +
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
> + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> + writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
> + writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
> + writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
> + qphy->dp_aux_cfg = 0;
> +
> + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
> + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
> + PHY_AUX_REQ_ERR_MASK,
> + qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
> +}
> +
> +static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
> + { 0x00, 0x0c, 0x15, 0x1a },
> + { 0x02, 0x0e, 0x16, 0xff },
> + { 0x02, 0x11, 0xff, 0xff },
> + { 0x04, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
> + { 0x02, 0x12, 0x16, 0x1a },
> + { 0x09, 0x19, 0x1f, 0xff },
> + { 0x10, 0x1f, 0xff, 0xff },
> + { 0x1f, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
> + { 0x00, 0x0c, 0x14, 0x19 },
> + { 0x00, 0x0b, 0x12, 0xff },
> + { 0x00, 0x0b, 0xff, 0xff },
> + { 0x04, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
> + { 0x08, 0x0f, 0x16, 0x1f },
> + { 0x11, 0x1e, 0x1f, 0xff },
> + { 0x19, 0x1f, 0xff, 0xff },
> + { 0x1f, 0xff, 0xff, 0xff }
> +};
> +
> +static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
> + unsigned int drv_lvl_reg, unsigned int emp_post_reg)
> +{
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + unsigned int v_level = 0, p_level = 0;
> + u8 voltage_swing_cfg, pre_emphasis_cfg;
> + int i;
> +
> + for (i = 0; i < dp_opts->lanes; i++) {
> + v_level = max(v_level, dp_opts->voltage[i]);
> + p_level = max(p_level, dp_opts->pre[i]);
> + }
> +
> + if (dp_opts->link_rate <= 2700) {
> + voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
> + pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
> + } else {
> + voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
> + pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
> + }
> +
> + /* TODO: Move check to config check */
> + if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
> + return -EINVAL;
> +
> + /* Enable MUX to use Cursor values from these registers */
> + voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
> + pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
> +
> + writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
> + writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
> + writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
> + writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
> +{
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + u32 bias_en, drvr_en;
> +
> + if (qcom_qmp_phy_configure_dp_swing(qphy,
> + QSERDES_V3_TX_TX_DRV_LVL,
> + QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
> + return;
> +
> + if (dp_opts->lanes == 1) {
> + bias_en = 0x3e;
> + drvr_en = 0x13;
> + } else {
> + bias_en = 0x3f;
> + drvr_en = 0x10;
> + }
> +
> + writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
> + writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
> + writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
> + writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
> +}
> +
> +static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
> +{
> + u32 val;
> + bool reverse = false;
> +
> + val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
> +
> + /*
> + * TODO: Assume orientation is CC1 for now and two lanes, need to
> + * use type-c connector to understand orientation and lanes.
> + *
> + * Otherwise val changes to be like below if this code understood
> + * the orientation of the type-c cable.
> + *
> + * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
> + * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
> + * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
> + * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
> + * if (orientation == ORIENTATION_CC2)
> + * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
> + */
> + val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
> + writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
> +
> + return reverse;
> +}
> +
> +static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + u32 phy_vco_div, status;
> + unsigned long pixel_freq;
> +
> + qcom_qmp_phy_configure_dp_mode(qphy);
> +
> + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
> + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + phy_vco_div = 0x1;
> + pixel_freq = 1620000000UL / 2;
> + break;
> + case 2700:
> + phy_vco_div = 0x1;
> + pixel_freq = 2700000000UL / 2;
> + break;
> + case 5400:
> + phy_vco_div = 0x2;
> + pixel_freq = 5400000000UL / 4;
> + break;
> + case 8100:
> + phy_vco_div = 0x0;
> + pixel_freq = 8100000000UL / 6;
> + break;
> + default:
> + /* Other link rates aren't supported */
> + return -EINVAL;
> + }
> + writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
> +
> + clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
> + clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
> +
> + writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
> + udelay(2000);
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000);
> +}
> +
> +/*
> + * We need to calibrate the aux setting here as many times
> + * as the caller tries
> + */
> +static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
> +{
> + static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
> + u8 val;
> +
> + qphy->dp_aux_cfg++;
> + qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
> + val = cfg1_settings[qphy->dp_aux_cfg];
> +
> + writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
> +{
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
> + qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + /* Turn on BIAS current for PHY/PLL */
> + writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
> +
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
> + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> + writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
> + writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
> + writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
> + qphy->dp_aux_cfg = 0;
> +
> + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
> + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
> + PHY_AUX_REQ_ERR_MASK,
> + qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
> +}
> +
> +static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
> +{
> + /* Program default values before writing proper values */
> + writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
> + writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
> +
> + writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> + writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> +
> + qcom_qmp_phy_configure_dp_swing(qphy,
> + QSERDES_V4_TX_TX_DRV_LVL,
> + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> +}
> +
> +static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + u32 phy_vco_div, status;
> + unsigned long pixel_freq;
> + u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
> + bool reverse;
> +
> + writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
> +
> + reverse = qcom_qmp_phy_configure_dp_mode(qphy);
> +
> + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> + writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> +
> + writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
> + writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + phy_vco_div = 0x1;
> + pixel_freq = 1620000000UL / 2;
> + break;
> + case 2700:
> + phy_vco_div = 0x1;
> + pixel_freq = 2700000000UL / 2;
> + break;
> + case 5400:
> + phy_vco_div = 0x2;
> + pixel_freq = 5400000000UL / 4;
> + break;
> + case 8100:
> + phy_vco_div = 0x0;
> + pixel_freq = 8100000000UL / 6;
> + break;
> + default:
> + /* Other link rates aren't supported */
> + return -EINVAL;
> + }
> + writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
> +
> + clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
> + clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
> +
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + /*
> + * At least for 7nm DP PHY this has to be done after enabling link
> + * clock.
> + */
> +
> + if (dp_opts->lanes == 1) {
> + bias0_en = reverse ? 0x3e : 0x15;
> + bias1_en = reverse ? 0x15 : 0x3e;
> + drvr0_en = reverse ? 0x13 : 0x10;
> + drvr1_en = reverse ? 0x10 : 0x13;
> + } else if (dp_opts->lanes == 2) {
> + bias0_en = reverse ? 0x3f : 0x15;
> + bias1_en = reverse ? 0x15 : 0x3f;
> + drvr0_en = 0x10;
> + drvr1_en = 0x10;
> + } else {
> + bias0_en = 0x3f;
> + bias1_en = 0x3f;
> + drvr0_en = 0x10;
> + drvr1_en = 0x10;
> + }
> +
> + writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
> + writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
> + writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
> + writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
> +
> + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
> + udelay(2000);
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
> + writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
> +
> + writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
> + writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
> +
> + writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> + writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> +
> + return 0;
> +}
> +
> +/*
> + * We need to calibrate the aux setting here as many times
> + * as the caller tries
> + */
> +static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
> +{
> + static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
> + u8 val;
> +
> + qphy->dp_aux_cfg++;
> + qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
> + val = cfg1_settings[qphy->dp_aux_cfg];
> +
> + writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
> +{
> + const struct phy_configure_opts_dp *dp_opts = &opts->dp;
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
> + if (qphy->dp_opts.set_voltages) {
> + cfg->configure_dp_tx(qphy);
> + qphy->dp_opts.set_voltages = 0;
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + if (cfg->calibrate_dp_phy)
> + return cfg->calibrate_dp_phy(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
> +{
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *dp_com = qmp->dp_com;
> + int ret, i;
> +
> + mutex_lock(&qmp->phy_mutex);
> + if (qmp->init_count++) {
> + mutex_unlock(&qmp->phy_mutex);
> + return 0;
> + }
> +
> + /* turn on regulator supplies */
> + ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
> + if (ret) {
> + dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
> + goto err_unlock;
> + }
> +
> + for (i = 0; i < cfg->num_resets; i++) {
> + ret = reset_control_assert(qmp->resets[i]);
> + if (ret) {
> + dev_err(qmp->dev, "%s reset assert failed\n",
> + cfg->reset_list[i]);
> + goto err_disable_regulators;
> + }
> + }
> +
> + for (i = cfg->num_resets - 1; i >= 0; i--) {
> + ret = reset_control_deassert(qmp->resets[i]);
> + if (ret) {
> + dev_err(qmp->dev, "%s reset deassert failed\n",
> + qphy->cfg->reset_list[i]);
> + goto err_assert_reset;
> + }
> + }
> +
> + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
> + if (ret)
> + goto err_assert_reset;
> +
> + if (cfg->has_phy_dp_com_ctrl) {
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
> + SW_PWRDN);
> + /* override hardware control for reset of qmp phy */
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
> + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
> + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
> +
> + /* Default type-c orientation, i.e CC1 */
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
> +
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
> + USB3_MODE | DP_MODE);
> +
> + /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
> + qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
> + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
> + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
> +
> + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
> + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
> + }
> +
> + if (cfg->has_phy_com_ctrl) {
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
> + SW_PWRDN);
> + } else {
> + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
> + qphy_setbits(pcs,
> + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
> + cfg->pwrdn_ctrl);
> + else
> + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
> + cfg->pwrdn_ctrl);
> + }
> +
> + mutex_unlock(&qmp->phy_mutex);
> +
> + return 0;
> +
> +err_assert_reset:
> + while (++i < cfg->num_resets)
> + reset_control_assert(qmp->resets[i]);
> +err_disable_regulators:
> + regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
> +err_unlock:
> + mutex_unlock(&qmp->phy_mutex);
> +
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
> +{
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + int i = cfg->num_resets;
> +
> + mutex_lock(&qmp->phy_mutex);
> + if (--qmp->init_count) {
> + mutex_unlock(&qmp->phy_mutex);
> + return 0;
> + }
> +
> + reset_control_assert(qmp->ufs_reset);
> + if (cfg->has_phy_com_ctrl) {
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
> + SERDES_START | PCS_START);
> + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
> + SW_RESET);
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
> + SW_PWRDN);
> + }
> +
> + while (--i >= 0)
> + reset_control_assert(qmp->resets[i]);
> +
> + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
> +
> + regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
> +
> + mutex_unlock(&qmp->phy_mutex);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_init(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + int ret;
> + dev_vdbg(qmp->dev, "Initializing QMP phy\n");
> +
> + if (cfg->no_pcs_sw_reset) {
> + /*
> + * Get UFS reset, which is delayed until now to avoid a
> + * circular dependency where UFS needs its PHY, but the PHY
> + * needs this UFS reset.
> + */
> + if (!qmp->ufs_reset) {
> + qmp->ufs_reset =
> + devm_reset_control_get_exclusive(qmp->dev,
> + "ufsphy");
> +
> + if (IS_ERR(qmp->ufs_reset)) {
> + ret = PTR_ERR(qmp->ufs_reset);
> + dev_err(qmp->dev,
> + "failed to get UFS reset: %d\n",
> + ret);
> +
> + qmp->ufs_reset = NULL;
> + return ret;
> + }
> + }
> +
> + ret = reset_control_assert(qmp->ufs_reset);
> + if (ret)
> + return ret;
> + }
> +
> + ret = qcom_qmp_phy_com_init(qphy);
> + if (ret)
> + return ret;
> +
> + if (cfg->type == PHY_TYPE_DP)
> + cfg->dp_aux_init(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_power_on(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *tx = qphy->tx;
> + void __iomem *rx = qphy->rx;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *pcs_misc = qphy->pcs_misc;
> + void __iomem *status;
> + unsigned int mask, val, ready;
> + int ret;
> +
> + qcom_qmp_phy_serdes_init(qphy);
> +
> + if (cfg->has_lane_rst) {
> + ret = reset_control_deassert(qphy->lane_rst);
> + if (ret) {
> + dev_err(qmp->dev, "lane%d reset deassert failed\n",
> + qphy->index);
> + return ret;
> + }
> + }
> +
> + ret = clk_prepare_enable(qphy->pipe_clk);
> + if (ret) {
> + dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
> + goto err_reset_lane;
> + }
> +
> + /* Tx, Rx, and PCS configurations */
> + qcom_qmp_phy_configure_lane(tx, cfg->regs,
> + cfg->tx_tbl, cfg->tx_tbl_num, 1);
> + if (cfg->tx_tbl_sec)
> + qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
> + cfg->tx_tbl_num_sec, 1);
> +
> + /* Configuration for other LANE for USB-DP combo PHY */
> + if (cfg->is_dual_lane_phy) {
> + qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
> + cfg->tx_tbl, cfg->tx_tbl_num, 2);
> + if (cfg->tx_tbl_sec)
> + qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
> + cfg->tx_tbl_sec,
> + cfg->tx_tbl_num_sec, 2);
> + }
> +
> + /* Configure special DP tx tunings */
> + if (cfg->type == PHY_TYPE_DP)
> + cfg->configure_dp_tx(qphy);
> +
> + qcom_qmp_phy_configure_lane(rx, cfg->regs,
> + cfg->rx_tbl, cfg->rx_tbl_num, 1);
> + if (cfg->rx_tbl_sec)
> + qcom_qmp_phy_configure_lane(rx, cfg->regs,
> + cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
> +
> + if (cfg->is_dual_lane_phy) {
> + qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
> + cfg->rx_tbl, cfg->rx_tbl_num, 2);
> + if (cfg->rx_tbl_sec)
> + qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
> + cfg->rx_tbl_sec,
> + cfg->rx_tbl_num_sec, 2);
> + }
> +
> + /* Configure link rate, swing, etc. */
> + if (cfg->type == PHY_TYPE_DP) {
> + cfg->configure_dp_phy(qphy);
> + } else {
> + qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
> + if (cfg->pcs_tbl_sec)
> + qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
> + cfg->pcs_tbl_num_sec);
> + }
> +
> + ret = reset_control_deassert(qmp->ufs_reset);
> + if (ret)
> + goto err_disable_pipe_clk;
> +
> + qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
> + cfg->pcs_misc_tbl_num);
> + if (cfg->pcs_misc_tbl_sec)
> + qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
> + cfg->pcs_misc_tbl_num_sec);
> +
> + /*
> + * Pull out PHY from POWER DOWN state.
> + * This is active low enable signal to power-down PHY.
> + */
> + if(cfg->type == PHY_TYPE_PCIE)
> + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
> +
> + if (cfg->has_pwrdn_delay)
> + usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
> +
> + if (cfg->type != PHY_TYPE_DP) {
> + /* Pull PHY out of reset state */
> + if (!cfg->no_pcs_sw_reset)
> + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
> + /* start SerDes and Phy-Coding-Sublayer */
> + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
> +
> + if (cfg->type == PHY_TYPE_UFS) {
> + status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
> + mask = PCS_READY;
> + ready = PCS_READY;
> + } else {
> + status = pcs + cfg->regs[QPHY_PCS_STATUS];
> + mask = cfg->phy_status;
> + ready = 0;
> + }
> +
> + ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
> + PHY_INIT_COMPLETE_TIMEOUT);
> + if (ret) {
> + dev_err(qmp->dev, "phy initialization timed-out\n");
> + goto err_disable_pipe_clk;
> + }
> + }
> + return 0;
> +
> +err_disable_pipe_clk:
> + clk_disable_unprepare(qphy->pipe_clk);
> +err_reset_lane:
> + if (cfg->has_lane_rst)
> + reset_control_assert(qphy->lane_rst);
> +
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_power_off(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + clk_disable_unprepare(qphy->pipe_clk);
> +
> + if (cfg->type == PHY_TYPE_DP) {
> + /* Assert DP PHY power down */
> + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> + } else {
> + /* PHY reset */
> + if (!cfg->no_pcs_sw_reset)
> + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
> +
> + /* stop SerDes and Phy-Coding-Sublayer */
> + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
> +
> + /* Put PHY into POWER DOWN state: active low */
> + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
> + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
> + cfg->pwrdn_ctrl);
> + } else {
> + qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
> + cfg->pwrdn_ctrl);
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_exit(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + if (cfg->has_lane_rst)
> + reset_control_assert(qphy->lane_rst);
> +
> + qcom_qmp_phy_com_exit(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_enable(struct phy *phy)
> +{
> + int ret;
> +
> + ret = qcom_qmp_phy_init(phy);
> + if (ret)
> + return ret;
> +
> + ret = qcom_qmp_phy_power_on(phy);
> + if (ret)
> + qcom_qmp_phy_exit(phy);
> +
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_disable(struct phy *phy)
> +{
> + int ret;
> +
> + ret = qcom_qmp_phy_power_off(phy);
> + if (ret)
> + return ret;
> + return qcom_qmp_phy_exit(phy);
> +}
> +
> +static int qcom_qmp_phy_set_mode(struct phy *phy,
> + enum phy_mode mode, int submode)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> +
> + qphy->mode = mode;
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *pcs_misc = qphy->pcs_misc;
> + u32 intr_mask;
> +
> + if (qphy->mode == PHY_MODE_USB_HOST_SS ||
> + qphy->mode == PHY_MODE_USB_DEVICE_SS)
> + intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
> + else
> + intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
> +
> + /* Clear any pending interrupts status */
> + qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> + /* Writing 1 followed by 0 clears the interrupt */
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> +
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
> + ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
> +
> + /* Enable required PHY autonomous mode interrupts */
> + qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
> +
> + /* Enable i/o clamp_n for autonomous mode */
> + if (pcs_misc)
> + qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
> +}
> +
> +static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *pcs_misc = qphy->pcs_misc;
> +
> + /* Disable i/o clamp_n on resume for normal mode */
> + if (pcs_misc)
> + qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
> +
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
> + ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
> +
> + qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> + /* Writing 1 followed by 0 clears the interrupt */
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> +}
> +
> +static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + struct qmp_phy *qphy = qmp->phys[0];
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
> +
> + /* Supported only for USB3 PHY and luckily USB3 is the first phy */
> + if (cfg->type != PHY_TYPE_USB3)
> + return 0;
> +
> + if (!qmp->init_count) {
> + dev_vdbg(dev, "PHY not initialized, bailing out\n");
> + return 0;
> + }
> +
> + qcom_qmp_phy_enable_autonomous_mode(qphy);
> +
> + clk_disable_unprepare(qphy->pipe_clk);
> + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
> +
> + return 0;
> +}
> +
> +static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + struct qmp_phy *qphy = qmp->phys[0];
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + int ret = 0;
> +
> + dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
> +
> + /* Supported only for USB3 PHY and luckily USB3 is the first phy */
> + if (cfg->type != PHY_TYPE_USB3)
> + return 0;
> +
> + if (!qmp->init_count) {
> + dev_vdbg(dev, "PHY not initialized, bailing out\n");
> + return 0;
> + }
> +
> + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(qphy->pipe_clk);
> + if (ret) {
> + dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
> + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
> + return ret;
> + }
> +
> + qcom_qmp_phy_disable_autonomous_mode(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + int num = cfg->num_vregs;
> + int i;
> +
> + qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
> + if (!qmp->vregs)
> + return -ENOMEM;
> +
> + for (i = 0; i < num; i++)
> + qmp->vregs[i].supply = cfg->vreg_list[i];
> +
> + return devm_regulator_bulk_get(dev, num, qmp->vregs);
> +}
> +
> +static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + int i;
> +
> + qmp->resets = devm_kcalloc(dev, cfg->num_resets,
> + sizeof(*qmp->resets), GFP_KERNEL);
> + if (!qmp->resets)
> + return -ENOMEM;
> +
> + for (i = 0; i < cfg->num_resets; i++) {
> + struct reset_control *rst;
> + const char *name = cfg->reset_list[i];
> +
> + rst = devm_reset_control_get_exclusive(dev, name);
> + if (IS_ERR(rst)) {
> + dev_err(dev, "failed to get %s reset\n", name);
> + return PTR_ERR(rst);
> + }
> + qmp->resets[i] = rst;
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + int num = cfg->num_clks;
> + int i;
> +
> + qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
> + if (!qmp->clks)
> + return -ENOMEM;
> +
> + for (i = 0; i < num; i++)
> + qmp->clks[i].id = cfg->clk_list[i];
> +
> + return devm_clk_bulk_get(dev, num, qmp->clks);
> +}
> +
> +static void phy_clk_release_provider(void *res)
> +{
> + of_clk_del_provider(res);
> +}
> +
> +/*
> + * Register a fixed rate pipe clock.
> + *
> + * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
> + * controls it. The <s>_pipe_clk coming out of the GCC is requested
> + * by the PHY driver for its operations.
> + * We register the <s>_pipe_clksrc here. The gcc driver takes care
> + * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
> + * Below picture shows this relationship.
> + *
> + * +---------------+
> + * | PHY block |<<---------------------------------------+
> + * | | |
> + * | +-------+ | +-----+ |
> + * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
> + * clk | +-------+ | +-----+
> + * +---------------+
> + */
> +static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
> +{
> + struct clk_fixed_rate *fixed;
> + struct clk_init_data init = { };
> + int ret;
> +
> + ret = of_property_read_string(np, "clock-output-names", &init.name);
> + if (ret) {
> + dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
> + return ret;
> + }
> +
> + fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
> + if (!fixed)
> + return -ENOMEM;
> +
> + init.ops = &clk_fixed_rate_ops;
> +
> + /* controllers using QMP phys use 125MHz pipe clock interface */
> + fixed->fixed_rate = 125000000;
> + fixed->hw.init = &init;
> +
> + ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
> + if (ret)
> + return ret;
> +
> + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
> + if (ret)
> + return ret;
> +
> + /*
> + * Roll a devm action because the clock provider is the child node, but
> + * the child node is not actually a device.
> + */
> + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
> +}
> +
> +/*
> + * Display Port PLL driver block diagram for branch clocks
> + *
> + * +------------------------------+
> + * | DP_VCO_CLK |
> + * | |
> + * | +-------------------+ |
> + * | | (DP PLL/VCO) | |
> + * | +---------+---------+ |
> + * | v |
> + * | +----------+-----------+ |
> + * | | hsclk_divsel_clk_src | |
> + * | +----------+-----------+ |
> + * +------------------------------+
> + * |
> + * +---------<---------v------------>----------+
> + * | |
> + * +--------v----------------+ |
> + * | dp_phy_pll_link_clk | |
> + * | link_clk | |
> + * +--------+----------------+ |
> + * | |
> + * | |
> + * v v
> + * Input to DISPCC block |
> + * for link clk, crypto clk |
> + * and interface clock |
> + * |
> + * |
> + * +--------<------------+-----------------+---<---+
> + * | | |
> + * +----v---------+ +--------v-----+ +--------v------+
> + * | vco_divided | | vco_divided | | vco_divided |
> + * | _clk_src | | _clk_src | | _clk_src |
> + * | | | | | |
> + * |divsel_six | | divsel_two | | divsel_four |
> + * +-------+------+ +-----+--------+ +--------+------+
> + * | | |
> + * v---->----------v-------------<------v
> + * |
> + * +----------+-----------------+
> + * | dp_phy_pll_vco_div_clk |
> + * +---------+------------------+
> + * |
> + * v
> + * Input to DISPCC block
> + * for DP pixel clock
> + *
> + */
> +static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + switch (req->rate) {
> + case 1620000000UL / 2:
> + case 2700000000UL / 2:
> + /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
> + return 0;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static unsigned long
> +qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + const struct qmp_phy_dp_clks *dp_clks;
> + const struct qmp_phy *qphy;
> + const struct phy_configure_opts_dp *dp_opts;
> +
> + dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
> + qphy = dp_clks->qphy;
> + dp_opts = &qphy->dp_opts;
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + return 1620000000UL / 2;
> + case 2700:
> + return 2700000000UL / 2;
> + case 5400:
> + return 5400000000UL / 4;
> + case 8100:
> + return 8100000000UL / 6;
> + default:
> + return 0;
> + }
> +}
> +
> +static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
> + .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
> + .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
> +};
> +
> +static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + switch (req->rate) {
> + case 162000000:
> + case 270000000:
> + case 540000000:
> + case 810000000:
> + return 0;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static unsigned long
> +qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + const struct qmp_phy_dp_clks *dp_clks;
> + const struct qmp_phy *qphy;
> + const struct phy_configure_opts_dp *dp_opts;
> +
> + dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
> + qphy = dp_clks->qphy;
> + dp_opts = &qphy->dp_opts;
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + case 2700:
> + case 5400:
> + case 8100:
> + return dp_opts->link_rate * 100000;
> + default:
> + return 0;
> + }
> +}
> +
> +static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
> + .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
> + .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
> +};
> +
> +static struct clk_hw *
> +qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
> +{
> + struct qmp_phy_dp_clks *dp_clks = data;
> + unsigned int idx = clkspec->args[0];
> +
> + if (idx >= 2) {
> + pr_err("%s: invalid index %u\n", __func__, idx);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + if (idx == 0)
> + return &dp_clks->dp_link_hw;
> +
> + return &dp_clks->dp_pixel_hw;
> +}
> +
> +static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
> + struct device_node *np)
> +{
> + struct clk_init_data init = { };
> + struct qmp_phy_dp_clks *dp_clks;
> + char name[64];
> + int ret;
> +
> + dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
> + if (!dp_clks)
> + return -ENOMEM;
> +
> + dp_clks->qphy = qphy;
> + qphy->dp_clks = dp_clks;
> +
> + snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
> + init.ops = &qcom_qmp_dp_link_clk_ops;
> + init.name = name;
> + dp_clks->dp_link_hw.init = &init;
> + ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
> + if (ret)
> + return ret;
> +
> + snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
> + init.ops = &qcom_qmp_dp_pixel_clk_ops;
> + init.name = name;
> + dp_clks->dp_pixel_hw.init = &init;
> + ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
> + if (ret)
> + return ret;
> +
> + ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
> + if (ret)
> + return ret;
> +
> + /*
> + * Roll a devm action because the clock provider is the child node, but
> + * the child node is not actually a device.
> + */
> + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
> +}
> +
> +static const struct phy_ops qcom_qmp_phy_gen_ops = {
> + .init = qcom_qmp_phy_enable,
> + .exit = qcom_qmp_phy_disable,
> + .set_mode = qcom_qmp_phy_set_mode,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct phy_ops qcom_qmp_phy_dp_ops = {
> + .init = qcom_qmp_phy_init,
> + .configure = qcom_qmp_dp_phy_configure,
> + .power_on = qcom_qmp_phy_power_on,
> + .calibrate = qcom_qmp_dp_phy_calibrate,
> + .power_off = qcom_qmp_phy_power_off,
> + .exit = qcom_qmp_phy_exit,
> + .set_mode = qcom_qmp_phy_set_mode,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
> + .power_on = qcom_qmp_phy_enable,
> + .power_off = qcom_qmp_phy_disable,
> + .set_mode = qcom_qmp_phy_set_mode,
> + .owner = THIS_MODULE,
> +};
> +
> +static void qcom_qmp_reset_control_put(void *data)
> +{
> + reset_control_put(data);
> +}
> +
> +static
> +int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
> + void __iomem *serdes, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + struct phy *generic_phy;
> + struct qmp_phy *qphy;
> + const struct phy_ops *ops;
> + char prop_name[MAX_PROP_NAME];
> + int ret;
> +
> + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
> + if (!qphy)
> + return -ENOMEM;
> +
> + qphy->cfg = cfg;
> + qphy->serdes = serdes;
> + /*
> + * Get memory resources for each phy lane:
> + * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
> + * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
> + * For single lane PHYs: pcs_misc (optional) -> 3.
> + */
> + qphy->tx = of_iomap(np, 0);
> + if (!qphy->tx)
> + return -ENOMEM;
> +
> + qphy->rx = of_iomap(np, 1);
> + if (!qphy->rx)
> + return -ENOMEM;
> +
> + qphy->pcs = of_iomap(np, 2);
> + if (!qphy->pcs)
> + return -ENOMEM;
> +
> + /*
> + * If this is a dual-lane PHY, then there should be registers for the
> + * second lane. Some old device trees did not specify this, so fall
> + * back to old legacy behavior of assuming they can be reached at an
> + * offset from the first lane.
> + */
> + if (cfg->is_dual_lane_phy) {
> + qphy->tx2 = of_iomap(np, 3);
> + qphy->rx2 = of_iomap(np, 4);
> + if (!qphy->tx2 || !qphy->rx2) {
> + dev_warn(dev,
> + "Underspecified device tree, falling back to legacy register regions\n");
> +
> + /* In the old version, pcs_misc is at index 3. */
> + qphy->pcs_misc = qphy->tx2;
> + qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
> + qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
> +
> + } else {
> + qphy->pcs_misc = of_iomap(np, 5);
> + }
> +
> + } else {
> + qphy->pcs_misc = of_iomap(np, 3);
> + }
> +
> + if (!qphy->pcs_misc)
> + dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
> +
> + /*
> + * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
> + * based phys, so they essentially have pipe clock. So,
> + * we return error in case phy is USB3 or PIPE type.
> + * Otherwise, we initialize pipe clock to NULL for
> + * all phys that don't need this.
> + */
> + snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
> + qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
> + if (IS_ERR(qphy->pipe_clk)) {
> + if (cfg->type == PHY_TYPE_PCIE ||
> + cfg->type == PHY_TYPE_USB3) {
> + ret = PTR_ERR(qphy->pipe_clk);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev,
> + "failed to get lane%d pipe_clk, %d\n",
> + id, ret);
> + return ret;
> + }
> + qphy->pipe_clk = NULL;
> + }
> +
> + /* Get lane reset, if any */
> + if (cfg->has_lane_rst) {
> + snprintf(prop_name, sizeof(prop_name), "lane%d", id);
> + qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
> + if (IS_ERR(qphy->lane_rst)) {
> + dev_err(dev, "failed to get lane%d reset\n", id);
> + return PTR_ERR(qphy->lane_rst);
> + }
> + ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
> + qphy->lane_rst);
> + if (ret)
> + return ret;
> + }
> +
> + if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
> + ops = &qcom_qmp_pcie_ufs_ops;
> + else if (cfg->type == PHY_TYPE_DP)
> + ops = &qcom_qmp_phy_dp_ops;
> + else
> + ops = &qcom_qmp_phy_gen_ops;
> +
> + generic_phy = devm_phy_create(dev, np, ops);
> + if (IS_ERR(generic_phy)) {
> + ret = PTR_ERR(generic_phy);
> + dev_err(dev, "failed to create qphy %d\n", ret);
> + return ret;
> + }
> +
> + qphy->phy = generic_phy;
> + qphy->index = id;
> + qphy->qmp = qmp;
> + qmp->phys[id] = qphy;
> + phy_set_drvdata(generic_phy, qphy);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
> + {
> + .compatible = "qcom,ipq8074-qmp-usb3-phy",
> + .data = &ipq8074_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,msm8996-qmp-pcie-phy",
> + .data = &msm8996_pciephy_cfg,
> + }, {
> + .compatible = "qcom,msm8996-qmp-ufs-phy",
> + .data = &msm8996_ufs_cfg,
> + }, {
> + .compatible = "qcom,msm8996-qmp-usb3-phy",
> + .data = &msm8996_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,msm8998-qmp-pcie-phy",
> + .data = &msm8998_pciephy_cfg,
> + }, {
> + .compatible = "qcom,msm8998-qmp-ufs-phy",
> + .data = &sdm845_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,ipq8074-qmp-pcie-phy",
> + .data = &ipq8074_pciephy_cfg,
> + }, {
> + .compatible = "qcom,ipq6018-qmp-pcie-phy",
> + .data = &ipq6018_pciephy_cfg,
> + }, {
> + .compatible = "qcom,ipq6018-qmp-usb3-phy",
> + .data = &ipq8074_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sc7180-qmp-usb3-phy",
> + .data = &sc7180_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
> + /* It's a combo phy */
> + }, {
> + .compatible = "qcom,sc8180x-qmp-pcie-phy",
> + .data = &sc8180x_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sc8180x-qmp-ufs-phy",
> + .data = &sm8150_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sc8280xp-qmp-ufs-phy",
> + .data = &sm8350_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sc8180x-qmp-usb3-phy",
> + .data = &sm8150_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
> + /* It's a combo phy */
> + }, {
> + .compatible = "qcom,sdm845-qhp-pcie-phy",
> + .data = &sdm845_qhp_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-pcie-phy",
> + .data = &sdm845_qmp_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-usb3-phy",
> + .data = &qmp_v3_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
> + .data = &qmp_v3_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-ufs-phy",
> + .data = &sdm845_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,msm8998-qmp-usb3-phy",
> + .data = &msm8998_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm6115-qmp-ufs-phy",
> + .data = &sm6115_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm6350-qmp-ufs-phy",
> + .data = &sdm845_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8150-qmp-ufs-phy",
> + .data = &sm8150_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-ufs-phy",
> + .data = &sm8150_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8150-qmp-usb3-phy",
> + .data = &sm8150_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
> + .data = &sm8150_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-usb3-phy",
> + .data = &sm8250_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
> + /* It's a combo phy */
> + }, {
> + .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
> + .data = &sm8250_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
> + .data = &sm8250_qmp_gen3x1_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
> + .data = &sm8250_qmp_gen3x2_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8350-qmp-ufs-phy",
> + .data = &sm8350_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
> + .data = &sm8250_qmp_gen3x2_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdx55-qmp-pcie-phy",
> + .data = &sdx55_qmp_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
> + .data = &sdx55_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
> + .data = &sdx65_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8350-qmp-usb3-phy",
> + .data = &sm8350_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
> + .data = &sm8350_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
> + .data = &sm8450_qmp_gen3x1_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
> + .data = &sm8450_qmp_gen4x2_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-ufs-phy",
> + .data = &sm8450_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-usb3-phy",
> + .data = &sm8350_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,qcm2290-qmp-usb3-phy",
> + .data = &qcm2290_usb3phy_cfg,
> + },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
> +
> +static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
> + {
> + .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
> + .data = &sc7180_usb3dpphy_cfg,
> + },
> + {
> + .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
> + .data = &sm8250_usb3dpphy_cfg,
> + },
> + {
> + .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
> + .data = &sc8180x_usb3dpphy_cfg,
> + },
> + { }
> +};
> +
> +static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
> + SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
> + qcom_qmp_phy_runtime_resume, NULL)
> +};
> +
> +static int qcom_qmp_phy_probe(struct platform_device *pdev)
> +{
> + struct qcom_qmp *qmp;
> + struct device *dev = &pdev->dev;
> + struct device_node *child;
> + struct phy_provider *phy_provider;
> + void __iomem *serdes;
> + void __iomem *usb_serdes;
> + void __iomem *dp_serdes = NULL;
> + const struct qmp_phy_combo_cfg *combo_cfg = NULL;
> + const struct qmp_phy_cfg *cfg = NULL;
> + const struct qmp_phy_cfg *usb_cfg = NULL;
> + const struct qmp_phy_cfg *dp_cfg = NULL;
> + int num, id, expected_phys;
> + int ret;
> +
> + qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
> + if (!qmp)
> + return -ENOMEM;
> +
> + qmp->dev = dev;
> + dev_set_drvdata(dev, qmp);
> +
> + /* Get the specific init parameters of QMP phy */
> + cfg = of_device_get_match_data(dev);
> + if (!cfg) {
> + const struct of_device_id *match;
> +
> + match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
> + if (!match)
> + return -EINVAL;
> +
> + combo_cfg = match->data;
> + if (!combo_cfg)
> + return -EINVAL;
> +
> + usb_cfg = combo_cfg->usb_cfg;
> + cfg = usb_cfg; /* Setup clks and regulators */
> + }
> +
> + /* per PHY serdes; usually located at base address */
> + usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(serdes))
> + return PTR_ERR(serdes);
> +
> + /* per PHY dp_com; if PHY has dp_com control block */
> + if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
> + qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
> + if (IS_ERR(qmp->dp_com))
> + return PTR_ERR(qmp->dp_com);
> + }
> +
> + if (combo_cfg) {
> + /* Only two serdes for combo PHY */
> + dp_serdes = devm_platform_ioremap_resource(pdev, 2);
> + if (IS_ERR(dp_serdes))
> + return PTR_ERR(dp_serdes);
> +
> + dp_cfg = combo_cfg->dp_cfg;
> + expected_phys = 2;
> + } else {
> + expected_phys = cfg->nlanes;
> + }
> +
> + mutex_init(&qmp->phy_mutex);
> +
> + ret = qcom_qmp_phy_clk_init(dev, cfg);
> + if (ret)
> + return ret;
> +
> + ret = qcom_qmp_phy_reset_init(dev, cfg);
> + if (ret)
> + return ret;
> +
> + ret = qcom_qmp_phy_vreg_init(dev, cfg);
> + if (ret) {
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "failed to get regulator supplies: %d\n",
> + ret);
> + return ret;
> + }
> +
> + num = of_get_available_child_count(dev->of_node);
> + /* do we have a rogue child node ? */
> + if (num > expected_phys)
> + return -EINVAL;
> +
> + qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
> + if (!qmp->phys)
> + return -ENOMEM;
> +
> + pm_runtime_set_active(dev);
> + pm_runtime_enable(dev);
> + /*
> + * Prevent runtime pm from being ON by default. Users can enable
> + * it using power/control in sysfs.
> + */
> + pm_runtime_forbid(dev);
> +
> + id = 0;
> + for_each_available_child_of_node(dev->of_node, child) {
> + if (of_node_name_eq(child, "dp-phy")) {
> + cfg = dp_cfg;
> + serdes = dp_serdes;
> + } else if (of_node_name_eq(child, "usb3-phy")) {
> + cfg = usb_cfg;
> + serdes = usb_serdes;
> + }
> +
> + /* Create per-lane phy */
> + ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
> + if (ret) {
> + dev_err(dev, "failed to create lane%d phy, %d\n",
> + id, ret);
> + goto err_node_put;
> + }
> +
> + /*
> + * Register the pipe clock provided by phy.
> + * See function description to see details of this pipe clock.
> + */
> + if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
> + ret = phy_pipe_clk_register(qmp, child);
> + if (ret) {
> + dev_err(qmp->dev,
> + "failed to register pipe clock source\n");
> + goto err_node_put;
> + }
> + } else if (cfg->type == PHY_TYPE_DP) {
> + ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
> + if (ret) {
> + dev_err(qmp->dev,
> + "failed to register DP clock source\n");
> + goto err_node_put;
> + }
> + }
> + id++;
> + }
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (!IS_ERR(phy_provider))
> + dev_info(dev, "Registered Qcom-QMP phy\n");
> + else
> + pm_runtime_disable(dev);
> +
> + return PTR_ERR_OR_ZERO(phy_provider);
> +
> +err_node_put:
> + pm_runtime_disable(dev);
> + of_node_put(child);
> + return ret;
> +}
> +
> +static struct platform_driver qcom_qmp_phy_driver = {
> + .probe = qcom_qmp_phy_probe,
> + .driver = {
> + .name = "qcom-qmp-phy",
> + .pm = &qcom_qmp_phy_pm_ops,
> + .of_match_table = qcom_qmp_phy_of_match_table,
> + },
> +};
> +
> +module_platform_driver(qcom_qmp_phy_driver);
> +
> +MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
> +MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> new file mode 100644
> index 000000000000..c7309e981bfb
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> @@ -0,0 +1,6350 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2017, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +
> +#include <dt-bindings/phy/phy.h>
> +
> +#include "phy-qcom-qmp.h"
> +
> +/* QPHY_SW_RESET bit */
> +#define SW_RESET BIT(0)
> +/* QPHY_POWER_DOWN_CONTROL */
> +#define SW_PWRDN BIT(0)
> +#define REFCLK_DRV_DSBL BIT(1)
> +/* QPHY_START_CONTROL bits */
> +#define SERDES_START BIT(0)
> +#define PCS_START BIT(1)
> +#define PLL_READY_GATE_EN BIT(3)
> +/* QPHY_PCS_STATUS bit */
> +#define PHYSTATUS BIT(6)
> +#define PHYSTATUS_4_20 BIT(7)
> +/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
> +#define PCS_READY BIT(0)
> +
> +/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
> +/* DP PHY soft reset */
> +#define SW_DPPHY_RESET BIT(0)
> +/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
> +#define SW_DPPHY_RESET_MUX BIT(1)
> +/* USB3 PHY soft reset */
> +#define SW_USB3PHY_RESET BIT(2)
> +/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
> +#define SW_USB3PHY_RESET_MUX BIT(3)
> +
> +/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
> +#define USB3_MODE BIT(0) /* enables USB3 mode */
> +#define DP_MODE BIT(1) /* enables DP mode */
> +
> +/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
> +#define ARCVR_DTCT_EN BIT(0)
> +#define ALFPS_DTCT_EN BIT(1)
> +#define ARCVR_DTCT_EVENT_SEL BIT(4)
> +
> +/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
> +#define IRQ_CLEAR BIT(0)
> +
> +/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
> +#define RCVR_DETECT BIT(0)
> +
> +/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
> +#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
> +
> +#define PHY_INIT_COMPLETE_TIMEOUT 10000
> +#define POWER_DOWN_DELAY_US_MIN 10
> +#define POWER_DOWN_DELAY_US_MAX 11
> +
> +#define MAX_PROP_NAME 32
> +
> +/* Define the assumed distance between lanes for underspecified device trees. */
> +#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
> +
> +struct qmp_phy_init_tbl {
> + unsigned int offset;
> + unsigned int val;
> + /*
> + * register part of layout ?
> + * if yes, then offset gives index in the reg-layout
> + */
> + bool in_layout;
> + /*
> + * mask of lanes for which this register is written
> + * for cases when second lane needs different values
> + */
> + u8 lane_mask;
> +};
> +
> +#define QMP_PHY_INIT_CFG(o, v) \
> + { \
> + .offset = o, \
> + .val = v, \
> + .lane_mask = 0xff, \
> + }
> +
> +#define QMP_PHY_INIT_CFG_L(o, v) \
> + { \
> + .offset = o, \
> + .val = v, \
> + .in_layout = true, \
> + .lane_mask = 0xff, \
> + }
> +
> +#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
> + { \
> + .offset = o, \
> + .val = v, \
> + .lane_mask = l, \
> + }
> +
> +/* set of registers with offsets different per-PHY */
> +enum qphy_reg_layout {
> + /* Common block control registers */
> + QPHY_COM_SW_RESET,
> + QPHY_COM_POWER_DOWN_CONTROL,
> + QPHY_COM_START_CONTROL,
> + QPHY_COM_PCS_READY_STATUS,
> + /* PCS registers */
> + QPHY_PLL_LOCK_CHK_DLY_TIME,
> + QPHY_FLL_CNTRL1,
> + QPHY_FLL_CNTRL2,
> + QPHY_FLL_CNT_VAL_L,
> + QPHY_FLL_CNT_VAL_H_TOL,
> + QPHY_FLL_MAN_CODE,
> + QPHY_SW_RESET,
> + QPHY_START_CTRL,
> + QPHY_PCS_READY_STATUS,
> + QPHY_PCS_STATUS,
> + QPHY_PCS_AUTONOMOUS_MODE_CTRL,
> + QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
> + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
> + QPHY_PCS_POWER_DOWN_CONTROL,
> + /* PCS_MISC registers */
> + QPHY_PCS_MISC_TYPEC_CTRL,
> + /* Keep last to ensure regs_layout arrays are properly initialized */
> + QPHY_LAYOUT_SIZE
> +};
> +
> +static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = 0x00,
> + [QPHY_PCS_READY_STATUS] = 0x168,
> +};
> +
> +static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> +};
> +
> +static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_COM_SW_RESET] = 0x400,
> + [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
> + [QPHY_COM_START_CONTROL] = 0x408,
> + [QPHY_COM_PCS_READY_STATUS] = 0x448,
> + [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
> + [QPHY_FLL_CNTRL1] = 0xc4,
> + [QPHY_FLL_CNTRL2] = 0xc8,
> + [QPHY_FLL_CNT_VAL_L] = 0xcc,
> + [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
> + [QPHY_FLL_MAN_CODE] = 0xd4,
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x174,
> +};
> +
> +static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_FLL_CNTRL1] = 0xc0,
> + [QPHY_FLL_CNTRL2] = 0xc4,
> + [QPHY_FLL_CNT_VAL_L] = 0xc8,
> + [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
> + [QPHY_FLL_MAN_CODE] = 0xd0,
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x17c,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
> +};
> +
> +static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x174,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
> +};
> +
> +static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x174,
> +};
> +
> +static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x2ac,
> +};
> +
> +static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
> +};
> +
> +static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
> +};
> +
> +static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
> +};
> +
> +static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
> + [QPHY_PCS_STATUS] = 0x174,
> + [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
> +};
> +
> +static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = 0x00,
> + [QPHY_PCS_READY_STATUS] = 0x160,
> +};
> +
> +static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = 0x00,
> + [QPHY_PCS_READY_STATUS] = 0x168,
> +};
> +
> +static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x44,
> + [QPHY_PCS_STATUS] = 0x14,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
> +};
> +
> +static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
> + [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
> + [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + /* PLL and Loop filter settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + /* SSC settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
> + QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
> +
> + QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
> +
> + QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
> + QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
> + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
> + /* PLL and Loop filter settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + /* SSC settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
> + /* FLL settings */
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
> + QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
> +
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
> + QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
> + QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
> + QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
> + QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
> + QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
> + QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
> + QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> + QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
> + QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
> + QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
> + QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
> + QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
> + QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
> + QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
> + QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
> + QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
> + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
> + QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
> + QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
> + QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
> + /* FLL settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> +
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
> + /* FLL settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> +
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> +
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
> +};
> +
> +static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
> + QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
> + QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
> + QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
> +};
> +
> +static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
> +
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
> + /* Lock Det settings */
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> +
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
> +};
> +
> +static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
> + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
> +};
> +
> +static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
> +};
> +
> +/* Register names should be validated, they might be different for this PHY */
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
> + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
> +};
> +
> +struct qmp_phy;
> +
> +/* struct qmp_phy_cfg - per-PHY initialization config */
> +struct qmp_phy_cfg {
> + /* phy-type - PCIE/UFS/USB */
> + unsigned int type;
> + /* number of lanes provided by phy */
> + int nlanes;
> +
> + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
> + const struct qmp_phy_init_tbl *serdes_tbl;
> + int serdes_tbl_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_sec;
> + int serdes_tbl_num_sec;
> + const struct qmp_phy_init_tbl *tx_tbl;
> + int tx_tbl_num;
> + const struct qmp_phy_init_tbl *tx_tbl_sec;
> + int tx_tbl_num_sec;
> + const struct qmp_phy_init_tbl *rx_tbl;
> + int rx_tbl_num;
> + const struct qmp_phy_init_tbl *rx_tbl_sec;
> + int rx_tbl_num_sec;
> + const struct qmp_phy_init_tbl *pcs_tbl;
> + int pcs_tbl_num;
> + const struct qmp_phy_init_tbl *pcs_tbl_sec;
> + int pcs_tbl_num_sec;
> + const struct qmp_phy_init_tbl *pcs_misc_tbl;
> + int pcs_misc_tbl_num;
> + const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
> + int pcs_misc_tbl_num_sec;
> +
> + /* Init sequence for DP PHY block link rates */
> + const struct qmp_phy_init_tbl *serdes_tbl_rbr;
> + int serdes_tbl_rbr_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_hbr;
> + int serdes_tbl_hbr_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
> + int serdes_tbl_hbr2_num;
> + const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
> + int serdes_tbl_hbr3_num;
> +
> + /* DP PHY callbacks */
> + int (*configure_dp_phy)(struct qmp_phy *qphy);
> + void (*configure_dp_tx)(struct qmp_phy *qphy);
> + int (*calibrate_dp_phy)(struct qmp_phy *qphy);
> + void (*dp_aux_init)(struct qmp_phy *qphy);
> +
> + /* clock ids to be requested */
> + const char * const *clk_list;
> + int num_clks;
> + /* resets to be requested */
> + const char * const *reset_list;
> + int num_resets;
> + /* regulators to be requested */
> + const char * const *vreg_list;
> + int num_vregs;
> +
> + /* array of registers with different offsets */
> + const unsigned int *regs;
> +
> + unsigned int start_ctrl;
> + unsigned int pwrdn_ctrl;
> + unsigned int mask_com_pcs_ready;
> + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
> + unsigned int phy_status;
> +
> + /* true, if PHY has a separate PHY_COM control block */
> + bool has_phy_com_ctrl;
> + /* true, if PHY has a reset for individual lanes */
> + bool has_lane_rst;
> + /* true, if PHY needs delay after POWER_DOWN */
> + bool has_pwrdn_delay;
> + /* power_down delay in usec */
> + int pwrdn_delay_min;
> + int pwrdn_delay_max;
> +
> + /* true, if PHY has a separate DP_COM control block */
> + bool has_phy_dp_com_ctrl;
> + /* true, if PHY has secondary tx/rx lanes to be configured */
> + bool is_dual_lane_phy;
> +
> + /* true, if PCS block has no separate SW_RESET register */
> + bool no_pcs_sw_reset;
> +};
> +
> +struct qmp_phy_combo_cfg {
> + const struct qmp_phy_cfg *usb_cfg;
> + const struct qmp_phy_cfg *dp_cfg;
> +};
> +
> +/**
> + * struct qmp_phy - per-lane phy descriptor
> + *
> + * @phy: generic phy
> + * @cfg: phy specific configuration
> + * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
> + * @tx: iomapped memory space for lane's tx
> + * @rx: iomapped memory space for lane's rx
> + * @pcs: iomapped memory space for lane's pcs
> + * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
> + * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
> + * @pcs_misc: iomapped memory space for lane's pcs_misc
> + * @pipe_clk: pipe clock
> + * @index: lane index
> + * @qmp: QMP phy to which this lane belongs
> + * @lane_rst: lane's reset controller
> + * @mode: current PHY mode
> + * @dp_aux_cfg: Display port aux config
> + * @dp_opts: Display port optional config
> + * @dp_clks: Display port clocks
> + */
> +struct qmp_phy {
> + struct phy *phy;
> + const struct qmp_phy_cfg *cfg;
> + void __iomem *serdes;
> + void __iomem *tx;
> + void __iomem *rx;
> + void __iomem *pcs;
> + void __iomem *tx2;
> + void __iomem *rx2;
> + void __iomem *pcs_misc;
> + struct clk *pipe_clk;
> + unsigned int index;
> + struct qcom_qmp *qmp;
> + struct reset_control *lane_rst;
> + enum phy_mode mode;
> + unsigned int dp_aux_cfg;
> + struct phy_configure_opts_dp dp_opts;
> + struct qmp_phy_dp_clks *dp_clks;
> +};
> +
> +struct qmp_phy_dp_clks {
> + struct qmp_phy *qphy;
> + struct clk_hw dp_link_hw;
> + struct clk_hw dp_pixel_hw;
> +};
> +
> +/**
> + * struct qcom_qmp - structure holding QMP phy block attributes
> + *
> + * @dev: device
> + * @dp_com: iomapped memory space for phy's dp_com control block
> + *
> + * @clks: array of clocks required by phy
> + * @resets: array of resets required by phy
> + * @vregs: regulator supplies bulk data
> + *
> + * @phys: array of per-lane phy descriptors
> + * @phy_mutex: mutex lock for PHY common block initialization
> + * @init_count: phy common block initialization count
> + * @ufs_reset: optional UFS PHY reset handle
> + */
> +struct qcom_qmp {
> + struct device *dev;
> + void __iomem *dp_com;
> +
> + struct clk_bulk_data *clks;
> + struct reset_control **resets;
> + struct regulator_bulk_data *vregs;
> +
> + struct qmp_phy **phys;
> +
> + struct mutex phy_mutex;
> + int init_count;
> +
> + struct reset_control *ufs_reset;
> +};
> +
> +static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
> +static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
> +static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
> +static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
> +
> +static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
> +static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
> +static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
> +static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
> +
> +static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
> +{
> + u32 reg;
> +
> + reg = readl(base + offset);
> + reg |= val;
> + writel(reg, base + offset);
> +
> + /* ensure that above write is through */
> + readl(base + offset);
> +}
> +
> +static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
> +{
> + u32 reg;
> +
> + reg = readl(base + offset);
> + reg &= ~val;
> + writel(reg, base + offset);
> +
> + /* ensure that above write is through */
> + readl(base + offset);
> +}
> +
> +/* list of clocks required by phy */
> +static const char * const msm8996_phy_clk_l[] = {
> + "aux", "cfg_ahb", "ref",
> +};
> +
> +static const char * const msm8996_ufs_phy_clk_l[] = {
> + "ref",
> +};
> +
> +static const char * const qmp_v3_phy_clk_l[] = {
> + "aux", "cfg_ahb", "ref", "com_aux",
> +};
> +
> +static const char * const sdm845_pciephy_clk_l[] = {
> + "aux", "cfg_ahb", "ref", "refgen",
> +};
> +
> +static const char * const qmp_v4_phy_clk_l[] = {
> + "aux", "ref_clk_src", "ref", "com_aux",
> +};
> +
> +/* the primary usb3 phy on sm8250 doesn't have a ref clock */
> +static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
> + "aux", "ref_clk_src", "com_aux"
> +};
> +
> +static const char * const sm8450_ufs_phy_clk_l[] = {
> + "qref", "ref", "ref_aux",
> +};
> +
> +static const char * const sdm845_ufs_phy_clk_l[] = {
> + "ref", "ref_aux",
> +};
> +
> +/* usb3 phy on sdx55 doesn't have com_aux clock */
> +static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
> + "aux", "cfg_ahb", "ref"
> +};
> +
> +static const char * const qcm2290_usb3phy_clk_l[] = {
> + "cfg_ahb", "ref", "com_aux",
> +};
> +
> +/* list of resets */
> +static const char * const msm8996_pciephy_reset_l[] = {
> + "phy", "common", "cfg",
> +};
> +
> +static const char * const msm8996_usb3phy_reset_l[] = {
> + "phy", "common",
> +};
> +
> +static const char * const sc7180_usb3phy_reset_l[] = {
> + "phy",
> +};
> +
> +static const char * const qcm2290_usb3phy_reset_l[] = {
> + "phy_phy", "phy",
> +};
> +
> +static const char * const sdm845_pciephy_reset_l[] = {
> + "phy",
> +};
> +
> +/* list of regulators */
> +static const char * const qmp_phy_vreg_l[] = {
> + "vdda-phy", "vdda-pll",
> +};
> +
> +static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = ipq8074_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
> + .tx_tbl = msm8996_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
> + .rx_tbl = ipq8074_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
> + .pcs_tbl = ipq8074_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +};
> +
> +static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 3,
> +
> + .serdes_tbl = msm8996_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
> + .tx_tbl = msm8996_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
> + .rx_tbl = msm8996_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
> + .pcs_tbl = msm8996_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = pciephy_regs_layout,
> +
> + .start_ctrl = PCS_START | PLL_READY_GATE_EN,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .mask_com_pcs_ready = PCS_READY,
> + .phy_status = PHYSTATUS,
> +
> + .has_phy_com_ctrl = true,
> + .has_lane_rst = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg msm8996_ufs_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8996_ufs_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
> + .tx_tbl = msm8996_ufs_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
> + .rx_tbl = msm8996_ufs_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
> +
> + .clk_list = msm8996_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
> +
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> +
> + .regs = msm8996_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .no_pcs_sw_reset = true,
> +};
> +
> +static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8996_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
> + .tx_tbl = msm8996_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
> + .rx_tbl = msm8996_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
> + .pcs_tbl = msm8996_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +};
> +
> +static const char * const ipq8074_pciephy_clk_l[] = {
> + "aux", "cfg_ahb",
> +};
> +/* list of resets */
> +static const char * const ipq8074_pciephy_reset_l[] = {
> + "phy", "common",
> +};
> +
> +static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = ipq8074_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
> + .tx_tbl = ipq8074_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
> + .rx_tbl = ipq8074_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
> + .pcs_tbl = ipq8074_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
> + .clk_list = ipq8074_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
> + .reset_list = ipq8074_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
> + .vreg_list = NULL,
> + .num_vregs = 0,
> + .regs = pciephy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_phy_com_ctrl = false,
> + .has_lane_rst = false,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = ipq6018_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
> + .tx_tbl = ipq6018_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
> + .rx_tbl = ipq6018_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
> + .pcs_tbl = ipq6018_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
> + .clk_list = ipq8074_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
> + .reset_list = ipq8074_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
> + .vreg_list = NULL,
> + .num_vregs = 0,
> + .regs = ipq_pciephy_gen3_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> +
> + .has_phy_com_ctrl = false,
> + .has_lane_rst = false,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
> + .tx_tbl = sdm845_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
> + .rx_tbl = sdm845_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
> + .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
> + .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sdm845_qmp_pciephy_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
> + .tx_tbl = sdm845_qhp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
> + .rx_tbl = sdm845_qhp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
> + .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sdm845_qhp_pciephy_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
> + .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
> + .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
> + .tx_tbl = sm8250_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
> + .rx_tbl = sm8250_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
> + .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
> + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
> + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
> + .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
> + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
> + .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
> + .tx_tbl = sm8250_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
> + .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
> + .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
> + .rx_tbl = sm8250_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
> + .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
> + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
> + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
> + .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
> + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
> + .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
> + .tx_tbl = qmp_v3_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
> + .rx_tbl = qmp_v3_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
> + .pcs_tbl = qmp_v3_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
> + .tx_tbl = qmp_v3_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
> + .rx_tbl = qmp_v3_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
> + .pcs_tbl = qmp_v3_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = sc7180_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
> + .type = PHY_TYPE_DP,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_dp_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
> + .tx_tbl = qmp_v3_dp_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
> +
> + .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
> + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
> + .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
> + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
> + .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
> + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
> + .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
> + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
> +
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = sc7180_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +
> + .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
> + .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
> + .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
> + .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
> +};
> +
> +static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
> + .usb_cfg = &sc7180_usb3phy_cfg,
> + .dp_cfg = &sc7180_dpphy_cfg,
> +};
> +
> +static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
> + .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
> + .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
> + .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sdm845_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
> + .tx_tbl = sdm845_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
> + .rx_tbl = sdm845_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
> + .pcs_tbl = sdm845_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sdm845_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> + .no_pcs_sw_reset = true,
> +};
> +
> +static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm6115_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
> + .tx_tbl = sm6115_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
> + .rx_tbl = sm6115_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
> + .pcs_tbl = sm6115_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm6115_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> +
> + .is_dual_lane_phy = false,
> + .no_pcs_sw_reset = true,
> +};
> +
> +static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8998_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
> + .tx_tbl = msm8998_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
> + .rx_tbl = msm8998_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
> + .pcs_tbl = msm8998_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = ipq8074_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = pciephy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +};
> +
> +static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = msm8998_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
> + .tx_tbl = msm8998_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
> + .rx_tbl = msm8998_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
> + .pcs_tbl = msm8998_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
> + .clk_list = msm8996_phy_clk_l,
> + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8150_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
> + .tx_tbl = sm8150_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
> + .rx_tbl = sm8150_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
> + .pcs_tbl = sm8150_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8150_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
> + .tx_tbl = sm8150_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
> + .rx_tbl = sm8150_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
> + .pcs_tbl = sm8150_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
> + .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
> + .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
> + .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
> + .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
> + .type = PHY_TYPE_DP,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v4_dp_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
> + .tx_tbl = qmp_v4_dp_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
> +
> + .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
> + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
> + .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
> + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
> + .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
> + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
> + .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
> + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
> +
> + .clk_list = qmp_v3_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
> + .reset_list = sc7180_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +
> + .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
> + .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
> + .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
> + .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
> +};
> +
> +static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
> + .usb_cfg = &sm8150_usb3phy_cfg,
> + .dp_cfg = &sc8180x_dpphy_cfg,
> +};
> +
> +static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
> + .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
> + .tx_tbl = sm8250_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
> + .rx_tbl = sm8250_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
> + .pcs_tbl = sm8250_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
> + .clk_list = qmp_v4_sm8250_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
> + .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
> + .type = PHY_TYPE_DP,
> + .nlanes = 1,
> +
> + .serdes_tbl = qmp_v4_dp_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
> + .tx_tbl = qmp_v4_dp_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
> +
> + .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
> + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
> + .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
> + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
> + .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
> + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
> + .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
> + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
> +
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +
> + .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
> + .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
> + .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
> + .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
> +};
> +
> +static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
> + .usb_cfg = &sm8250_usb3phy_cfg,
> + .dp_cfg = &sm8250_dpphy_cfg,
> +};
> +
> +static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
> + .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_sdx55_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 2,
> +
> + .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
> + .tx_tbl = sdx55_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
> + .rx_tbl = sdx55_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
> + .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
> + .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS_4_20,
> +
> + .is_dual_lane_phy = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
> + .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_sdx55_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8350_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8350_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
> + .tx_tbl = sm8350_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
> + .rx_tbl = sm8350_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
> + .pcs_tbl = sm8350_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8150_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
> + .tx_tbl = sm8350_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
> + .rx_tbl = sm8350_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
> + .pcs_tbl = sm8350_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
> + .clk_list = qmp_v4_sm8250_usbphy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v4_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +
> + .has_phy_dp_com_ctrl = true,
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
> + .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
> + .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
> + .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8350_usb3_uniphy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> +};
> +
> +static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8350_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
> + .tx_tbl = sm8350_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
> + .rx_tbl = sm8350_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
> + .pcs_tbl = sm8350_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
> + .clk_list = sm8450_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8150_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
> + .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
> + .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
> + .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
> + .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
> + .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
> + .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS_4_20,
> +
> + .is_dual_lane_phy = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> +
> + .serdes_tbl = qcm2290_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
> + .tx_tbl = qcm2290_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
> + .rx_tbl = qcm2290_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
> + .pcs_tbl = qcm2290_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
> + .clk_list = qcm2290_usb3phy_clk_l,
> + .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
> + .reset_list = qcm2290_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qcm2290_usb3phy_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> +static void qcom_qmp_phy_configure_lane(void __iomem *base,
> + const unsigned int *regs,
> + const struct qmp_phy_init_tbl tbl[],
> + int num,
> + u8 lane_mask)
> +{
> + int i;
> + const struct qmp_phy_init_tbl *t = tbl;
> +
> + if (!t)
> + return;
> +
> + for (i = 0; i < num; i++, t++) {
> + if (!(t->lane_mask & lane_mask))
> + continue;
> +
> + if (t->in_layout)
> + writel(t->val, base + regs[t->offset]);
> + else
> + writel(t->val, base + t->offset);
> + }
> +}
> +
> +static void qcom_qmp_phy_configure(void __iomem *base,
> + const unsigned int *regs,
> + const struct qmp_phy_init_tbl tbl[],
> + int num)
> +{
> + qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
> +}
> +
> +static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
> +{
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
> + int serdes_tbl_num = cfg->serdes_tbl_num;
> + int ret;
> +
> + qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
> + if (cfg->serdes_tbl_sec)
> + qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
> + cfg->serdes_tbl_num_sec);
> +
> + if (cfg->type == PHY_TYPE_DP) {
> + switch (dp_opts->link_rate) {
> + case 1620:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_rbr,
> + cfg->serdes_tbl_rbr_num);
> + break;
> + case 2700:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_hbr,
> + cfg->serdes_tbl_hbr_num);
> + break;
> + case 5400:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_hbr2,
> + cfg->serdes_tbl_hbr2_num);
> + break;
> + case 8100:
> + qcom_qmp_phy_configure(serdes, cfg->regs,
> + cfg->serdes_tbl_hbr3,
> + cfg->serdes_tbl_hbr3_num);
> + break;
> + default:
> + /* Other link rates aren't supported */
> + return -EINVAL;
> + }
> + }
> +
> +
> + if (cfg->has_phy_com_ctrl) {
> + void __iomem *status;
> + unsigned int mask, val;
> +
> + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
> + SERDES_START | PCS_START);
> +
> + status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
> + mask = cfg->mask_com_pcs_ready;
> +
> + ret = readl_poll_timeout(status, val, (val & mask), 10,
> + PHY_INIT_COMPLETE_TIMEOUT);
> + if (ret) {
> + dev_err(qmp->dev,
> + "phy common block init timed-out\n");
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
> +{
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
> + qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + /* Turn on BIAS current for PHY/PLL */
> + writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
> + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
> + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
> +
> + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_LANE_0_1_PWRDN |
> + DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
> + DP_PHY_PD_CTL_DP_CLAMP_EN,
> + qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + writel(QSERDES_V3_COM_BIAS_EN |
> + QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
> + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
> + QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
> + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
> +
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
> + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> + writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
> + writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
> + writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
> + qphy->dp_aux_cfg = 0;
> +
> + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
> + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
> + PHY_AUX_REQ_ERR_MASK,
> + qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
> +}
> +
> +static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
> + { 0x00, 0x0c, 0x15, 0x1a },
> + { 0x02, 0x0e, 0x16, 0xff },
> + { 0x02, 0x11, 0xff, 0xff },
> + { 0x04, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
> + { 0x02, 0x12, 0x16, 0x1a },
> + { 0x09, 0x19, 0x1f, 0xff },
> + { 0x10, 0x1f, 0xff, 0xff },
> + { 0x1f, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
> + { 0x00, 0x0c, 0x14, 0x19 },
> + { 0x00, 0x0b, 0x12, 0xff },
> + { 0x00, 0x0b, 0xff, 0xff },
> + { 0x04, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
> + { 0x08, 0x0f, 0x16, 0x1f },
> + { 0x11, 0x1e, 0x1f, 0xff },
> + { 0x19, 0x1f, 0xff, 0xff },
> + { 0x1f, 0xff, 0xff, 0xff }
> +};
> +
> +static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
> + unsigned int drv_lvl_reg, unsigned int emp_post_reg)
> +{
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + unsigned int v_level = 0, p_level = 0;
> + u8 voltage_swing_cfg, pre_emphasis_cfg;
> + int i;
> +
> + for (i = 0; i < dp_opts->lanes; i++) {
> + v_level = max(v_level, dp_opts->voltage[i]);
> + p_level = max(p_level, dp_opts->pre[i]);
> + }
> +
> + if (dp_opts->link_rate <= 2700) {
> + voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
> + pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
> + } else {
> + voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
> + pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
> + }
> +
> + /* TODO: Move check to config check */
> + if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
> + return -EINVAL;
> +
> + /* Enable MUX to use Cursor values from these registers */
> + voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
> + pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
> +
> + writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
> + writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
> + writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
> + writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
> +{
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + u32 bias_en, drvr_en;
> +
> + if (qcom_qmp_phy_configure_dp_swing(qphy,
> + QSERDES_V3_TX_TX_DRV_LVL,
> + QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
> + return;
> +
> + if (dp_opts->lanes == 1) {
> + bias_en = 0x3e;
> + drvr_en = 0x13;
> + } else {
> + bias_en = 0x3f;
> + drvr_en = 0x10;
> + }
> +
> + writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
> + writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
> + writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
> + writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
> +}
> +
> +static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
> +{
> + u32 val;
> + bool reverse = false;
> +
> + val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
> +
> + /*
> + * TODO: Assume orientation is CC1 for now and two lanes, need to
> + * use type-c connector to understand orientation and lanes.
> + *
> + * Otherwise val changes to be like below if this code understood
> + * the orientation of the type-c cable.
> + *
> + * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
> + * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
> + * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
> + * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
> + * if (orientation == ORIENTATION_CC2)
> + * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
> + */
> + val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
> + writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
> +
> + return reverse;
> +}
> +
> +static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + u32 phy_vco_div, status;
> + unsigned long pixel_freq;
> +
> + qcom_qmp_phy_configure_dp_mode(qphy);
> +
> + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
> + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + phy_vco_div = 0x1;
> + pixel_freq = 1620000000UL / 2;
> + break;
> + case 2700:
> + phy_vco_div = 0x1;
> + pixel_freq = 2700000000UL / 2;
> + break;
> + case 5400:
> + phy_vco_div = 0x2;
> + pixel_freq = 5400000000UL / 4;
> + break;
> + case 8100:
> + phy_vco_div = 0x0;
> + pixel_freq = 8100000000UL / 6;
> + break;
> + default:
> + /* Other link rates aren't supported */
> + return -EINVAL;
> + }
> + writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
> +
> + clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
> + clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
> +
> + writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
> + udelay(2000);
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000);
> +}
> +
> +/*
> + * We need to calibrate the aux setting here as many times
> + * as the caller tries
> + */
> +static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
> +{
> + static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
> + u8 val;
> +
> + qphy->dp_aux_cfg++;
> + qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
> + val = cfg1_settings[qphy->dp_aux_cfg];
> +
> + writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
> +{
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
> + qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> +
> + /* Turn on BIAS current for PHY/PLL */
> + writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
> +
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
> + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> + writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
> + writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
> + writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
> + qphy->dp_aux_cfg = 0;
> +
> + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
> + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
> + PHY_AUX_REQ_ERR_MASK,
> + qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
> +}
> +
> +static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
> +{
> + /* Program default values before writing proper values */
> + writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
> + writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
> +
> + writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> + writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> +
> + qcom_qmp_phy_configure_dp_swing(qphy,
> + QSERDES_V4_TX_TX_DRV_LVL,
> + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> +}
> +
> +static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + u32 phy_vco_div, status;
> + unsigned long pixel_freq;
> + u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
> + bool reverse;
> +
> + writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
> +
> + reverse = qcom_qmp_phy_configure_dp_mode(qphy);
> +
> + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> + writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> +
> + writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
> + writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + phy_vco_div = 0x1;
> + pixel_freq = 1620000000UL / 2;
> + break;
> + case 2700:
> + phy_vco_div = 0x1;
> + pixel_freq = 2700000000UL / 2;
> + break;
> + case 5400:
> + phy_vco_div = 0x2;
> + pixel_freq = 5400000000UL / 4;
> + break;
> + case 8100:
> + phy_vco_div = 0x0;
> + pixel_freq = 8100000000UL / 6;
> + break;
> + default:
> + /* Other link rates aren't supported */
> + return -EINVAL;
> + }
> + writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
> +
> + clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
> + clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
> +
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + /*
> + * At least for 7nm DP PHY this has to be done after enabling link
> + * clock.
> + */
> +
> + if (dp_opts->lanes == 1) {
> + bias0_en = reverse ? 0x3e : 0x15;
> + bias1_en = reverse ? 0x15 : 0x3e;
> + drvr0_en = reverse ? 0x13 : 0x10;
> + drvr1_en = reverse ? 0x10 : 0x13;
> + } else if (dp_opts->lanes == 2) {
> + bias0_en = reverse ? 0x3f : 0x15;
> + bias1_en = reverse ? 0x15 : 0x3f;
> + drvr0_en = 0x10;
> + drvr1_en = 0x10;
> + } else {
> + bias0_en = 0x3f;
> + bias1_en = 0x3f;
> + drvr0_en = 0x10;
> + drvr1_en = 0x10;
> + }
> +
> + writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
> + writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
> + writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
> + writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
> +
> + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
> + udelay(2000);
> + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
> +
> + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000))
> + return -ETIMEDOUT;
> +
> + writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
> + writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
> +
> + writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
> + writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
> +
> + writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> + writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
> +
> + return 0;
> +}
> +
> +/*
> + * We need to calibrate the aux setting here as many times
> + * as the caller tries
> + */
> +static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
> +{
> + static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
> + u8 val;
> +
> + qphy->dp_aux_cfg++;
> + qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
> + val = cfg1_settings[qphy->dp_aux_cfg];
> +
> + writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
> +{
> + const struct phy_configure_opts_dp *dp_opts = &opts->dp;
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
> + if (qphy->dp_opts.set_voltages) {
> + cfg->configure_dp_tx(qphy);
> + qphy->dp_opts.set_voltages = 0;
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + if (cfg->calibrate_dp_phy)
> + return cfg->calibrate_dp_phy(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
> +{
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *dp_com = qmp->dp_com;
> + int ret, i;
> +
> + mutex_lock(&qmp->phy_mutex);
> + if (qmp->init_count++) {
> + mutex_unlock(&qmp->phy_mutex);
> + return 0;
> + }
> +
> + /* turn on regulator supplies */
> + ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
> + if (ret) {
> + dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
> + goto err_unlock;
> + }
> +
> + for (i = 0; i < cfg->num_resets; i++) {
> + ret = reset_control_assert(qmp->resets[i]);
> + if (ret) {
> + dev_err(qmp->dev, "%s reset assert failed\n",
> + cfg->reset_list[i]);
> + goto err_disable_regulators;
> + }
> + }
> +
> + for (i = cfg->num_resets - 1; i >= 0; i--) {
> + ret = reset_control_deassert(qmp->resets[i]);
> + if (ret) {
> + dev_err(qmp->dev, "%s reset deassert failed\n",
> + qphy->cfg->reset_list[i]);
> + goto err_assert_reset;
> + }
> + }
> +
> + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
> + if (ret)
> + goto err_assert_reset;
> +
> + if (cfg->has_phy_dp_com_ctrl) {
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
> + SW_PWRDN);
> + /* override hardware control for reset of qmp phy */
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
> + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
> + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
> +
> + /* Default type-c orientation, i.e CC1 */
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
> +
> + qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
> + USB3_MODE | DP_MODE);
> +
> + /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
> + qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
> + SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
> + SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
> +
> + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
> + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
> + }
> +
> + if (cfg->has_phy_com_ctrl) {
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
> + SW_PWRDN);
> + } else {
> + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
> + qphy_setbits(pcs,
> + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
> + cfg->pwrdn_ctrl);
> + else
> + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
> + cfg->pwrdn_ctrl);
> + }
> +
> + mutex_unlock(&qmp->phy_mutex);
> +
> + return 0;
> +
> +err_assert_reset:
> + while (++i < cfg->num_resets)
> + reset_control_assert(qmp->resets[i]);
> +err_disable_regulators:
> + regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
> +err_unlock:
> + mutex_unlock(&qmp->phy_mutex);
> +
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
> +{
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + int i = cfg->num_resets;
> +
> + mutex_lock(&qmp->phy_mutex);
> + if (--qmp->init_count) {
> + mutex_unlock(&qmp->phy_mutex);
> + return 0;
> + }
> +
> + reset_control_assert(qmp->ufs_reset);
> + if (cfg->has_phy_com_ctrl) {
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
> + SERDES_START | PCS_START);
> + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
> + SW_RESET);
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
> + SW_PWRDN);
> + }
> +
> + while (--i >= 0)
> + reset_control_assert(qmp->resets[i]);
> +
> + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
> +
> + regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
> +
> + mutex_unlock(&qmp->phy_mutex);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_init(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + int ret;
> + dev_vdbg(qmp->dev, "Initializing QMP phy\n");
> +
> + if (cfg->no_pcs_sw_reset) {
> + /*
> + * Get UFS reset, which is delayed until now to avoid a
> + * circular dependency where UFS needs its PHY, but the PHY
> + * needs this UFS reset.
> + */
> + if (!qmp->ufs_reset) {
> + qmp->ufs_reset =
> + devm_reset_control_get_exclusive(qmp->dev,
> + "ufsphy");
> +
> + if (IS_ERR(qmp->ufs_reset)) {
> + ret = PTR_ERR(qmp->ufs_reset);
> + dev_err(qmp->dev,
> + "failed to get UFS reset: %d\n",
> + ret);
> +
> + qmp->ufs_reset = NULL;
> + return ret;
> + }
> + }
> +
> + ret = reset_control_assert(qmp->ufs_reset);
> + if (ret)
> + return ret;
> + }
> +
> + ret = qcom_qmp_phy_com_init(qphy);
> + if (ret)
> + return ret;
> +
> + if (cfg->type == PHY_TYPE_DP)
> + cfg->dp_aux_init(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_power_on(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *tx = qphy->tx;
> + void __iomem *rx = qphy->rx;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *pcs_misc = qphy->pcs_misc;
> + void __iomem *status;
> + unsigned int mask, val, ready;
> + int ret;
> +
> + qcom_qmp_phy_serdes_init(qphy);
> +
> + if (cfg->has_lane_rst) {
> + ret = reset_control_deassert(qphy->lane_rst);
> + if (ret) {
> + dev_err(qmp->dev, "lane%d reset deassert failed\n",
> + qphy->index);
> + return ret;
> + }
> + }
> +
> + ret = clk_prepare_enable(qphy->pipe_clk);
> + if (ret) {
> + dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
> + goto err_reset_lane;
> + }
> +
> + /* Tx, Rx, and PCS configurations */
> + qcom_qmp_phy_configure_lane(tx, cfg->regs,
> + cfg->tx_tbl, cfg->tx_tbl_num, 1);
> + if (cfg->tx_tbl_sec)
> + qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
> + cfg->tx_tbl_num_sec, 1);
> +
> + /* Configuration for other LANE for USB-DP combo PHY */
> + if (cfg->is_dual_lane_phy) {
> + qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
> + cfg->tx_tbl, cfg->tx_tbl_num, 2);
> + if (cfg->tx_tbl_sec)
> + qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
> + cfg->tx_tbl_sec,
> + cfg->tx_tbl_num_sec, 2);
> + }
> +
> + /* Configure special DP tx tunings */
> + if (cfg->type == PHY_TYPE_DP)
> + cfg->configure_dp_tx(qphy);
> +
> + qcom_qmp_phy_configure_lane(rx, cfg->regs,
> + cfg->rx_tbl, cfg->rx_tbl_num, 1);
> + if (cfg->rx_tbl_sec)
> + qcom_qmp_phy_configure_lane(rx, cfg->regs,
> + cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
> +
> + if (cfg->is_dual_lane_phy) {
> + qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
> + cfg->rx_tbl, cfg->rx_tbl_num, 2);
> + if (cfg->rx_tbl_sec)
> + qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
> + cfg->rx_tbl_sec,
> + cfg->rx_tbl_num_sec, 2);
> + }
> +
> + /* Configure link rate, swing, etc. */
> + if (cfg->type == PHY_TYPE_DP) {
> + cfg->configure_dp_phy(qphy);
> + } else {
> + qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
> + if (cfg->pcs_tbl_sec)
> + qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
> + cfg->pcs_tbl_num_sec);
> + }
> +
> + ret = reset_control_deassert(qmp->ufs_reset);
> + if (ret)
> + goto err_disable_pipe_clk;
> +
> + qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
> + cfg->pcs_misc_tbl_num);
> + if (cfg->pcs_misc_tbl_sec)
> + qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
> + cfg->pcs_misc_tbl_num_sec);
> +
> + /*
> + * Pull out PHY from POWER DOWN state.
> + * This is active low enable signal to power-down PHY.
> + */
> + if(cfg->type == PHY_TYPE_PCIE)
> + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
> +
> + if (cfg->has_pwrdn_delay)
> + usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
> +
> + if (cfg->type != PHY_TYPE_DP) {
> + /* Pull PHY out of reset state */
> + if (!cfg->no_pcs_sw_reset)
> + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
> + /* start SerDes and Phy-Coding-Sublayer */
> + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
> +
> + if (cfg->type == PHY_TYPE_UFS) {
> + status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
> + mask = PCS_READY;
> + ready = PCS_READY;
> + } else {
> + status = pcs + cfg->regs[QPHY_PCS_STATUS];
> + mask = cfg->phy_status;
> + ready = 0;
> + }
> +
> + ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
> + PHY_INIT_COMPLETE_TIMEOUT);
> + if (ret) {
> + dev_err(qmp->dev, "phy initialization timed-out\n");
> + goto err_disable_pipe_clk;
> + }
> + }
> + return 0;
> +
> +err_disable_pipe_clk:
> + clk_disable_unprepare(qphy->pipe_clk);
> +err_reset_lane:
> + if (cfg->has_lane_rst)
> + reset_control_assert(qphy->lane_rst);
> +
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_power_off(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + clk_disable_unprepare(qphy->pipe_clk);
> +
> + if (cfg->type == PHY_TYPE_DP) {
> + /* Assert DP PHY power down */
> + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
> + } else {
> + /* PHY reset */
> + if (!cfg->no_pcs_sw_reset)
> + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
> +
> + /* stop SerDes and Phy-Coding-Sublayer */
> + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
> +
> + /* Put PHY into POWER DOWN state: active low */
> + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
> + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
> + cfg->pwrdn_ctrl);
> + } else {
> + qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
> + cfg->pwrdn_ctrl);
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_exit(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + if (cfg->has_lane_rst)
> + reset_control_assert(qphy->lane_rst);
> +
> + qcom_qmp_phy_com_exit(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_enable(struct phy *phy)
> +{
> + int ret;
> +
> + ret = qcom_qmp_phy_init(phy);
> + if (ret)
> + return ret;
> +
> + ret = qcom_qmp_phy_power_on(phy);
> + if (ret)
> + qcom_qmp_phy_exit(phy);
> +
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_disable(struct phy *phy)
> +{
> + int ret;
> +
> + ret = qcom_qmp_phy_power_off(phy);
> + if (ret)
> + return ret;
> + return qcom_qmp_phy_exit(phy);
> +}
> +
> +static int qcom_qmp_phy_set_mode(struct phy *phy,
> + enum phy_mode mode, int submode)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> +
> + qphy->mode = mode;
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *pcs_misc = qphy->pcs_misc;
> + u32 intr_mask;
> +
> + if (qphy->mode == PHY_MODE_USB_HOST_SS ||
> + qphy->mode == PHY_MODE_USB_DEVICE_SS)
> + intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
> + else
> + intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
> +
> + /* Clear any pending interrupts status */
> + qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> + /* Writing 1 followed by 0 clears the interrupt */
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> +
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
> + ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
> +
> + /* Enable required PHY autonomous mode interrupts */
> + qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
> +
> + /* Enable i/o clamp_n for autonomous mode */
> + if (pcs_misc)
> + qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
> +}
> +
> +static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
> +{
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *pcs = qphy->pcs;
> + void __iomem *pcs_misc = qphy->pcs_misc;
> +
> + /* Disable i/o clamp_n on resume for normal mode */
> + if (pcs_misc)
> + qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
> +
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
> + ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
> +
> + qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> + /* Writing 1 followed by 0 clears the interrupt */
> + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
> +}
> +
> +static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + struct qmp_phy *qphy = qmp->phys[0];
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> +
> + dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
> +
> + /* Supported only for USB3 PHY and luckily USB3 is the first phy */
> + if (cfg->type != PHY_TYPE_USB3)
> + return 0;
> +
> + if (!qmp->init_count) {
> + dev_vdbg(dev, "PHY not initialized, bailing out\n");
> + return 0;
> + }
> +
> + qcom_qmp_phy_enable_autonomous_mode(qphy);
> +
> + clk_disable_unprepare(qphy->pipe_clk);
> + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
> +
> + return 0;
> +}
> +
> +static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + struct qmp_phy *qphy = qmp->phys[0];
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + int ret = 0;
> +
> + dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
> +
> + /* Supported only for USB3 PHY and luckily USB3 is the first phy */
> + if (cfg->type != PHY_TYPE_USB3)
> + return 0;
> +
> + if (!qmp->init_count) {
> + dev_vdbg(dev, "PHY not initialized, bailing out\n");
> + return 0;
> + }
> +
> + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(qphy->pipe_clk);
> + if (ret) {
> + dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
> + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
> + return ret;
> + }
> +
> + qcom_qmp_phy_disable_autonomous_mode(qphy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + int num = cfg->num_vregs;
> + int i;
> +
> + qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
> + if (!qmp->vregs)
> + return -ENOMEM;
> +
> + for (i = 0; i < num; i++)
> + qmp->vregs[i].supply = cfg->vreg_list[i];
> +
> + return devm_regulator_bulk_get(dev, num, qmp->vregs);
> +}
> +
> +static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + int i;
> +
> + qmp->resets = devm_kcalloc(dev, cfg->num_resets,
> + sizeof(*qmp->resets), GFP_KERNEL);
> + if (!qmp->resets)
> + return -ENOMEM;
> +
> + for (i = 0; i < cfg->num_resets; i++) {
> + struct reset_control *rst;
> + const char *name = cfg->reset_list[i];
> +
> + rst = devm_reset_control_get_exclusive(dev, name);
> + if (IS_ERR(rst)) {
> + dev_err(dev, "failed to get %s reset\n", name);
> + return PTR_ERR(rst);
> + }
> + qmp->resets[i] = rst;
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + int num = cfg->num_clks;
> + int i;
> +
> + qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
> + if (!qmp->clks)
> + return -ENOMEM;
> +
> + for (i = 0; i < num; i++)
> + qmp->clks[i].id = cfg->clk_list[i];
> +
> + return devm_clk_bulk_get(dev, num, qmp->clks);
> +}
> +
> +static void phy_clk_release_provider(void *res)
> +{
> + of_clk_del_provider(res);
> +}
> +
> +/*
> + * Register a fixed rate pipe clock.
> + *
> + * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
> + * controls it. The <s>_pipe_clk coming out of the GCC is requested
> + * by the PHY driver for its operations.
> + * We register the <s>_pipe_clksrc here. The gcc driver takes care
> + * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
> + * Below picture shows this relationship.
> + *
> + * +---------------+
> + * | PHY block |<<---------------------------------------+
> + * | | |
> + * | +-------+ | +-----+ |
> + * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
> + * clk | +-------+ | +-----+
> + * +---------------+
> + */
> +static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
> +{
> + struct clk_fixed_rate *fixed;
> + struct clk_init_data init = { };
> + int ret;
> +
> + ret = of_property_read_string(np, "clock-output-names", &init.name);
> + if (ret) {
> + dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
> + return ret;
> + }
> +
> + fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
> + if (!fixed)
> + return -ENOMEM;
> +
> + init.ops = &clk_fixed_rate_ops;
> +
> + /* controllers using QMP phys use 125MHz pipe clock interface */
> + fixed->fixed_rate = 125000000;
> + fixed->hw.init = &init;
> +
> + ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
> + if (ret)
> + return ret;
> +
> + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
> + if (ret)
> + return ret;
> +
> + /*
> + * Roll a devm action because the clock provider is the child node, but
> + * the child node is not actually a device.
> + */
> + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
> +}
> +
> +/*
> + * Display Port PLL driver block diagram for branch clocks
> + *
> + * +------------------------------+
> + * | DP_VCO_CLK |
> + * | |
> + * | +-------------------+ |
> + * | | (DP PLL/VCO) | |
> + * | +---------+---------+ |
> + * | v |
> + * | +----------+-----------+ |
> + * | | hsclk_divsel_clk_src | |
> + * | +----------+-----------+ |
> + * +------------------------------+
> + * |
> + * +---------<---------v------------>----------+
> + * | |
> + * +--------v----------------+ |
> + * | dp_phy_pll_link_clk | |
> + * | link_clk | |
> + * +--------+----------------+ |
> + * | |
> + * | |
> + * v v
> + * Input to DISPCC block |
> + * for link clk, crypto clk |
> + * and interface clock |
> + * |
> + * |
> + * +--------<------------+-----------------+---<---+
> + * | | |
> + * +----v---------+ +--------v-----+ +--------v------+
> + * | vco_divided | | vco_divided | | vco_divided |
> + * | _clk_src | | _clk_src | | _clk_src |
> + * | | | | | |
> + * |divsel_six | | divsel_two | | divsel_four |
> + * +-------+------+ +-----+--------+ +--------+------+
> + * | | |
> + * v---->----------v-------------<------v
> + * |
> + * +----------+-----------------+
> + * | dp_phy_pll_vco_div_clk |
> + * +---------+------------------+
> + * |
> + * v
> + * Input to DISPCC block
> + * for DP pixel clock
> + *
> + */
> +static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + switch (req->rate) {
> + case 1620000000UL / 2:
> + case 2700000000UL / 2:
> + /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
> + return 0;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static unsigned long
> +qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + const struct qmp_phy_dp_clks *dp_clks;
> + const struct qmp_phy *qphy;
> + const struct phy_configure_opts_dp *dp_opts;
> +
> + dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
> + qphy = dp_clks->qphy;
> + dp_opts = &qphy->dp_opts;
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + return 1620000000UL / 2;
> + case 2700:
> + return 2700000000UL / 2;
> + case 5400:
> + return 5400000000UL / 4;
> + case 8100:
> + return 8100000000UL / 6;
> + default:
> + return 0;
> + }
> +}
> +
> +static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
> + .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
> + .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
> +};
> +
> +static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + switch (req->rate) {
> + case 162000000:
> + case 270000000:
> + case 540000000:
> + case 810000000:
> + return 0;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static unsigned long
> +qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + const struct qmp_phy_dp_clks *dp_clks;
> + const struct qmp_phy *qphy;
> + const struct phy_configure_opts_dp *dp_opts;
> +
> + dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
> + qphy = dp_clks->qphy;
> + dp_opts = &qphy->dp_opts;
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + case 2700:
> + case 5400:
> + case 8100:
> + return dp_opts->link_rate * 100000;
> + default:
> + return 0;
> + }
> +}
> +
> +static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
> + .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
> + .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
> +};
> +
> +static struct clk_hw *
> +qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
> +{
> + struct qmp_phy_dp_clks *dp_clks = data;
> + unsigned int idx = clkspec->args[0];
> +
> + if (idx >= 2) {
> + pr_err("%s: invalid index %u\n", __func__, idx);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + if (idx == 0)
> + return &dp_clks->dp_link_hw;
> +
> + return &dp_clks->dp_pixel_hw;
> +}
> +
> +static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
> + struct device_node *np)
> +{
> + struct clk_init_data init = { };
> + struct qmp_phy_dp_clks *dp_clks;
> + char name[64];
> + int ret;
> +
> + dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
> + if (!dp_clks)
> + return -ENOMEM;
> +
> + dp_clks->qphy = qphy;
> + qphy->dp_clks = dp_clks;
> +
> + snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
> + init.ops = &qcom_qmp_dp_link_clk_ops;
> + init.name = name;
> + dp_clks->dp_link_hw.init = &init;
> + ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
> + if (ret)
> + return ret;
> +
> + snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
> + init.ops = &qcom_qmp_dp_pixel_clk_ops;
> + init.name = name;
> + dp_clks->dp_pixel_hw.init = &init;
> + ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
> + if (ret)
> + return ret;
> +
> + ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
> + if (ret)
> + return ret;
> +
> + /*
> + * Roll a devm action because the clock provider is the child node, but
> + * the child node is not actually a device.
> + */
> + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
> +}
> +
> +static const struct phy_ops qcom_qmp_phy_gen_ops = {
> + .init = qcom_qmp_phy_enable,
> + .exit = qcom_qmp_phy_disable,
> + .set_mode = qcom_qmp_phy_set_mode,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct phy_ops qcom_qmp_phy_dp_ops = {
> + .init = qcom_qmp_phy_init,
> + .configure = qcom_qmp_dp_phy_configure,
> + .power_on = qcom_qmp_phy_power_on,
> + .calibrate = qcom_qmp_dp_phy_calibrate,
> + .power_off = qcom_qmp_phy_power_off,
> + .exit = qcom_qmp_phy_exit,
> + .set_mode = qcom_qmp_phy_set_mode,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
> + .power_on = qcom_qmp_phy_enable,
> + .power_off = qcom_qmp_phy_disable,
> + .set_mode = qcom_qmp_phy_set_mode,
> + .owner = THIS_MODULE,
> +};
> +
> +static void qcom_qmp_reset_control_put(void *data)
> +{
> + reset_control_put(data);
> +}
> +
> +static
> +int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
> + void __iomem *serdes, const struct qmp_phy_cfg *cfg)
> +{
> + struct qcom_qmp *qmp = dev_get_drvdata(dev);
> + struct phy *generic_phy;
> + struct qmp_phy *qphy;
> + const struct phy_ops *ops;
> + char prop_name[MAX_PROP_NAME];
> + int ret;
> +
> + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
> + if (!qphy)
> + return -ENOMEM;
> +
> + qphy->cfg = cfg;
> + qphy->serdes = serdes;
> + /*
> + * Get memory resources for each phy lane:
> + * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
> + * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
> + * For single lane PHYs: pcs_misc (optional) -> 3.
> + */
> + qphy->tx = of_iomap(np, 0);
> + if (!qphy->tx)
> + return -ENOMEM;
> +
> + qphy->rx = of_iomap(np, 1);
> + if (!qphy->rx)
> + return -ENOMEM;
> +
> + qphy->pcs = of_iomap(np, 2);
> + if (!qphy->pcs)
> + return -ENOMEM;
> +
> + /*
> + * If this is a dual-lane PHY, then there should be registers for the
> + * second lane. Some old device trees did not specify this, so fall
> + * back to old legacy behavior of assuming they can be reached at an
> + * offset from the first lane.
> + */
> + if (cfg->is_dual_lane_phy) {
> + qphy->tx2 = of_iomap(np, 3);
> + qphy->rx2 = of_iomap(np, 4);
> + if (!qphy->tx2 || !qphy->rx2) {
> + dev_warn(dev,
> + "Underspecified device tree, falling back to legacy register regions\n");
> +
> + /* In the old version, pcs_misc is at index 3. */
> + qphy->pcs_misc = qphy->tx2;
> + qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
> + qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
> +
> + } else {
> + qphy->pcs_misc = of_iomap(np, 5);
> + }
> +
> + } else {
> + qphy->pcs_misc = of_iomap(np, 3);
> + }
> +
> + if (!qphy->pcs_misc)
> + dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
> +
> + /*
> + * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
> + * based phys, so they essentially have pipe clock. So,
> + * we return error in case phy is USB3 or PIPE type.
> + * Otherwise, we initialize pipe clock to NULL for
> + * all phys that don't need this.
> + */
> + snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
> + qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
> + if (IS_ERR(qphy->pipe_clk)) {
> + if (cfg->type == PHY_TYPE_PCIE ||
> + cfg->type == PHY_TYPE_USB3) {
> + ret = PTR_ERR(qphy->pipe_clk);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev,
> + "failed to get lane%d pipe_clk, %d\n",
> + id, ret);
> + return ret;
> + }
> + qphy->pipe_clk = NULL;
> + }
> +
> + /* Get lane reset, if any */
> + if (cfg->has_lane_rst) {
> + snprintf(prop_name, sizeof(prop_name), "lane%d", id);
> + qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
> + if (IS_ERR(qphy->lane_rst)) {
> + dev_err(dev, "failed to get lane%d reset\n", id);
> + return PTR_ERR(qphy->lane_rst);
> + }
> + ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
> + qphy->lane_rst);
> + if (ret)
> + return ret;
> + }
> +
> + if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
> + ops = &qcom_qmp_pcie_ufs_ops;
> + else if (cfg->type == PHY_TYPE_DP)
> + ops = &qcom_qmp_phy_dp_ops;
> + else
> + ops = &qcom_qmp_phy_gen_ops;
> +
> + generic_phy = devm_phy_create(dev, np, ops);
> + if (IS_ERR(generic_phy)) {
> + ret = PTR_ERR(generic_phy);
> + dev_err(dev, "failed to create qphy %d\n", ret);
> + return ret;
> + }
> +
> + qphy->phy = generic_phy;
> + qphy->index = id;
> + qphy->qmp = qmp;
> + qmp->phys[id] = qphy;
> + phy_set_drvdata(generic_phy, qphy);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
> + {
> + .compatible = "qcom,ipq8074-qmp-usb3-phy",
> + .data = &ipq8074_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,msm8996-qmp-pcie-phy",
> + .data = &msm8996_pciephy_cfg,
> + }, {
> + .compatible = "qcom,msm8996-qmp-ufs-phy",
> + .data = &msm8996_ufs_cfg,
> + }, {
> + .compatible = "qcom,msm8996-qmp-usb3-phy",
> + .data = &msm8996_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,msm8998-qmp-pcie-phy",
> + .data = &msm8998_pciephy_cfg,
> + }, {
> + .compatible = "qcom,msm8998-qmp-ufs-phy",
> + .data = &sdm845_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,ipq8074-qmp-pcie-phy",
> + .data = &ipq8074_pciephy_cfg,
> + }, {
> + .compatible = "qcom,ipq6018-qmp-pcie-phy",
> + .data = &ipq6018_pciephy_cfg,
> + }, {
> + .compatible = "qcom,ipq6018-qmp-usb3-phy",
> + .data = &ipq8074_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sc7180-qmp-usb3-phy",
> + .data = &sc7180_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
> + /* It's a combo phy */
> + }, {
> + .compatible = "qcom,sc8180x-qmp-pcie-phy",
> + .data = &sc8180x_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sc8180x-qmp-ufs-phy",
> + .data = &sm8150_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sc8280xp-qmp-ufs-phy",
> + .data = &sm8350_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sc8180x-qmp-usb3-phy",
> + .data = &sm8150_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
> + /* It's a combo phy */
> + }, {
> + .compatible = "qcom,sdm845-qhp-pcie-phy",
> + .data = &sdm845_qhp_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-pcie-phy",
> + .data = &sdm845_qmp_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-usb3-phy",
> + .data = &qmp_v3_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
> + .data = &qmp_v3_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sdm845-qmp-ufs-phy",
> + .data = &sdm845_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,msm8998-qmp-usb3-phy",
> + .data = &msm8998_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm6115-qmp-ufs-phy",
> + .data = &sm6115_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm6350-qmp-ufs-phy",
> + .data = &sdm845_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8150-qmp-ufs-phy",
> + .data = &sm8150_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-ufs-phy",
> + .data = &sm8150_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8150-qmp-usb3-phy",
> + .data = &sm8150_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
> + .data = &sm8150_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-usb3-phy",
> + .data = &sm8250_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
> + /* It's a combo phy */
> + }, {
> + .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
> + .data = &sm8250_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
> + .data = &sm8250_qmp_gen3x1_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
> + .data = &sm8250_qmp_gen3x2_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8350-qmp-ufs-phy",
> + .data = &sm8350_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
> + .data = &sm8250_qmp_gen3x2_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdx55-qmp-pcie-phy",
> + .data = &sdx55_qmp_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
> + .data = &sdx55_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
> + .data = &sdx65_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8350-qmp-usb3-phy",
> + .data = &sm8350_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
> + .data = &sm8350_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
> + .data = &sm8450_qmp_gen3x1_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
> + .data = &sm8450_qmp_gen4x2_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-ufs-phy",
> + .data = &sm8450_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-usb3-phy",
> + .data = &sm8350_usb3phy_cfg,
> + }, {
> + .compatible = "qcom,qcm2290-qmp-usb3-phy",
> + .data = &qcm2290_usb3phy_cfg,
> + },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
> +
> +static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
> + {
> + .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
> + .data = &sc7180_usb3dpphy_cfg,
> + },
> + {
> + .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
> + .data = &sm8250_usb3dpphy_cfg,
> + },
> + {
> + .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
> + .data = &sc8180x_usb3dpphy_cfg,
> + },
> + { }
> +};
> +
> +static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
> + SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
> + qcom_qmp_phy_runtime_resume, NULL)
> +};
> +
> +static int qcom_qmp_phy_probe(struct platform_device *pdev)
> +{
> + struct qcom_qmp *qmp;
> + struct device *dev = &pdev->dev;
> + struct device_node *child;
> + struct phy_provider *phy_provider;
> + void __iomem *serdes;
> + void __iomem *usb_serdes;
> + void __iomem *dp_serdes = NULL;
> + const struct qmp_phy_combo_cfg *combo_cfg = NULL;
> + const struct qmp_phy_cfg *cfg = NULL;
> + const struct qmp_phy_cfg *usb_cfg = NULL;
> + const struct qmp_phy_cfg *dp_cfg = NULL;
> + int num, id, expected_phys;
> + int ret;
> +
> + qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
> + if (!qmp)
> + return -ENOMEM;
> +
> + qmp->dev = dev;
> + dev_set_drvdata(dev, qmp);
> +
> + /* Get the specific init parameters of QMP phy */
> + cfg = of_device_get_match_data(dev);
> + if (!cfg) {
> + const struct of_device_id *match;
> +
> + match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
> + if (!match)
> + return -EINVAL;
> +
> + combo_cfg = match->data;
> + if (!combo_cfg)
> + return -EINVAL;
> +
> + usb_cfg = combo_cfg->usb_cfg;
> + cfg = usb_cfg; /* Setup clks and regulators */
> + }
> +
> + /* per PHY serdes; usually located at base address */
> + usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(serdes))
> + return PTR_ERR(serdes);
> +
> + /* per PHY dp_com; if PHY has dp_com control block */
> + if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
> + qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
> + if (IS_ERR(qmp->dp_com))
> + return PTR_ERR(qmp->dp_com);
> + }
> +
> + if (combo_cfg) {
> + /* Only two serdes for combo PHY */
> + dp_serdes = devm_platform_ioremap_resource(pdev, 2);
> + if (IS_ERR(dp_serdes))
> + return PTR_ERR(dp_serdes);
> +
> + dp_cfg = combo_cfg->dp_cfg;
> + expected_phys = 2;
> + } else {
> + expected_phys = cfg->nlanes;
> + }
> +
> + mutex_init(&qmp->phy_mutex);
> +
> + ret = qcom_qmp_phy_clk_init(dev, cfg);
> + if (ret)
> + return ret;
> +
> + ret = qcom_qmp_phy_reset_init(dev, cfg);
> + if (ret)
> + return ret;
> +
> + ret = qcom_qmp_phy_vreg_init(dev, cfg);
> + if (ret) {
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "failed to get regulator supplies: %d\n",
> + ret);
> + return ret;
> + }
> +
> + num = of_get_available_child_count(dev->of_node);
> + /* do we have a rogue child node ? */
> + if (num > expected_phys)
> + return -EINVAL;
> +
> + qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
> + if (!qmp->phys)
> + return -ENOMEM;
> +
> + pm_runtime_set_active(dev);
> + pm_runtime_enable(dev);
> + /*
> + * Prevent runtime pm from being ON by default. Users can enable
> + * it using power/control in sysfs.
> + */
> + pm_runtime_forbid(dev);
> +
> + id = 0;
> + for_each_available_child_of_node(dev->of_node, child) {
> + if (of_node_name_eq(child, "dp-phy")) {
> + cfg = dp_cfg;
> + serdes = dp_serdes;
> + } else if (of_node_name_eq(child, "usb3-phy")) {
> + cfg = usb_cfg;
> + serdes = usb_serdes;
> + }
> +
> + /* Create per-lane phy */
> + ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
> + if (ret) {
> + dev_err(dev, "failed to create lane%d phy, %d\n",
> + id, ret);
> + goto err_node_put;
> + }
> +
> + /*
> + * Register the pipe clock provided by phy.
> + * See function description to see details of this pipe clock.
> + */
> + if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
> + ret = phy_pipe_clk_register(qmp, child);
> + if (ret) {
> + dev_err(qmp->dev,
> + "failed to register pipe clock source\n");
> + goto err_node_put;
> + }
> + } else if (cfg->type == PHY_TYPE_DP) {
> + ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
> + if (ret) {
> + dev_err(qmp->dev,
> + "failed to register DP clock source\n");
> + goto err_node_put;
> + }
> + }
> + id++;
> + }
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (!IS_ERR(phy_provider))
> + dev_info(dev, "Registered Qcom-QMP phy\n");
> + else
> + pm_runtime_disable(dev);
> +
> + return PTR_ERR_OR_ZERO(phy_provider);
> +
> +err_node_put:
> + pm_runtime_disable(dev);
> + of_node_put(child);
> + return ret;
> +}
> +
> +static struct platform_driver qcom_qmp_phy_driver = {
> + .probe = qcom_qmp_phy_probe,
> + .driver = {
> + .name = "qcom-qmp-phy",
> + .pm = &qcom_qmp_phy_pm_ops,
> + .of_match_table = qcom_qmp_phy_of_match_table,
> + },
> +};
> +
> +module_platform_driver(qcom_qmp_phy_driver);
> +
> +MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
> +MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.35.1
>
>
--
~Vinod
next prev parent reply other threads:[~2022-12-28 16:55 UTC|newest]
Thread overview: 754+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-28 14:31 [PATCH 5.15 000/731] 5.15.86-rc1 review Greg Kroah-Hartman
2022-12-28 14:31 ` [PATCH 5.15 001/731] drm/amd/display: Manually adjust strobe for DCN303 Greg Kroah-Hartman
2022-12-28 14:31 ` [PATCH 5.15 002/731] usb: musb: remove extra check in musb_gadget_vbus_draw Greg Kroah-Hartman
2022-12-28 14:31 ` [PATCH 5.15 003/731] arm64: dts: qcom: ipq6018-cp01-c1: use BLSPI1 pins Greg Kroah-Hartman
2022-12-28 14:31 ` [PATCH 5.15 004/731] arm64: dts: qcom: sm8250-sony-xperia-edo: fix touchscreen bias-disable Greg Kroah-Hartman
2022-12-28 14:31 ` [PATCH 5.15 005/731] arm64: dts: qcom: msm8996: Add MSM8996 Pro support Greg Kroah-Hartman
2022-12-28 14:31 ` [PATCH 5.15 006/731] arm64: dts: qcom: msm8996: fix supported-hw in cpufreq OPP tables Greg Kroah-Hartman
2022-12-28 14:31 ` [PATCH 5.15 007/731] arm64: dts: qcom: msm8996: fix GPU OPP table Greg Kroah-Hartman
2022-12-28 14:31 ` [PATCH 5.15 008/731] ARM: dts: qcom: apq8064: fix coresight compatible Greg Kroah-Hartman
2022-12-28 14:31 ` [PATCH 5.15 009/731] arm64: dts: qcom: sdm630: fix UART1 pin bias Greg Kroah-Hartman
2022-12-28 14:31 ` [PATCH 5.15 010/731] arm64: dts: qcom: sdm845-cheza: fix AP suspend " Greg Kroah-Hartman
2022-12-28 14:31 ` [PATCH 5.15 011/731] arm64: dts: qcom: msm8916: Drop MSS fallback compatible Greg Kroah-Hartman
2022-12-28 14:31 ` [PATCH 5.15 012/731] objtool, kcsan: Add volatile read/write instrumentation to whitelist Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 013/731] ARM: dts: stm32: Drop stm32mp15xc.dtsi from Avenger96 Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 014/731] ARM: dts: stm32: Fix AV96 WLAN regulator gpio property Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 015/731] drivers: soc: ti: knav_qmss_queue: Mark knav_acc_firmwares as static Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 016/731] arm64: dts: qcom: pm660: Use unique ADC5_VCOIN address in node name Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 017/731] arm64: dts: qcom: sm8250: correct LPASS pin pull down Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 018/731] soc: qcom: llcc: make irq truly optional Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 019/731] arm64: dts: qcom: Correct QMP PHY child node name Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 020/731] arm64: dts: qcom: sm8150: fix UFS PHY registers Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 021/731] arm64: dts: qcom: sm8250: " Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 022/731] arm64: dts: qcom: sm8350: " Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 023/731] arm64: dts: qcom: sm8250: drop bogus DP PHY clock Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 024/731] soc: qcom: apr: make code more reuseable Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 025/731] soc: qcom: apr: Add check for idr_alloc and of_property_read_string_index Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 026/731] arm64: dts: qcom: sm6125: fix SDHCI CQE reg names Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 027/731] arm: dts: spear600: Fix clcd interrupt Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 028/731] soc: ti: knav_qmss_queue: Use pm_runtime_resume_and_get instead of pm_runtime_get_sync Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 029/731] soc: ti: knav_qmss_queue: Fix PM disable depth imbalance in knav_queue_probe Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 030/731] soc: ti: smartreflex: Fix PM disable depth imbalance in omap_sr_probe Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 031/731] arm64: Treat ESR_ELx as a 64-bit register Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 032/731] arm64: mm: kfence: only handle translation faults Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 033/731] perf: arm_dsu: Fix hotplug callback leak in dsu_pmu_init() Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 034/731] perf/arm_dmc620: Fix hotplug callback leak in dmc620_pmu_init() Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 035/731] perf/smmuv3: Fix hotplug callback leak in arm_smmu_pmu_init() Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 036/731] arm64: dts: ti: k3-am65-main: Drop dma-coherent in crypto node Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 037/731] arm64: dts: ti: k3-j721e-main: " Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 038/731] ARM: dts: nuvoton: Remove bogus unit addresses from fixed-partition nodes Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 039/731] arm64: dts: mt6779: Fix devicetree build warnings Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 040/731] arm64: dts: mt2712e: Fix unit_address_vs_reg warning for oscillators Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 041/731] arm64: dts: mt2712e: Fix unit address for pinctrl node Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 042/731] arm64: dts: mt2712-evb: Fix vproc fixed regulators unit names Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 043/731] arm64: dts: mt2712-evb: Fix usb vbus " Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 044/731] arm64: dts: mediatek: pumpkin-common: Fix devicetree warnings Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 045/731] arm64: dts: mediatek: mt6797: Fix 26M oscillator unit name Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 046/731] ARM: dts: dove: Fix assigned-addresses for every PCIe Root Port Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 047/731] ARM: dts: armada-370: " Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 048/731] ARM: dts: armada-xp: " Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 049/731] ARM: dts: armada-375: " Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 050/731] ARM: dts: armada-38x: " Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 051/731] ARM: dts: armada-39x: " Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 052/731] ARM: dts: turris-omnia: Add ethernet aliases Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 053/731] ARM: dts: turris-omnia: Add switch port 6 node Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 054/731] ARM: dts: armada-38x: Fix compatible string for gpios Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 055/731] ARM: dts: armada-39x: " Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 056/731] arm64: dts: armada-3720-turris-mox: Add missing interrupt for RTC Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 057/731] seccomp: Move copy_seccomp() to no failure path Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 058/731] pstore/ram: Fix error return code in ramoops_probe() Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 059/731] ARM: mmp: fix timer_read delay Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 060/731] pstore: Avoid kcore oops by vmap()ing with VM_IOREMAP Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 061/731] tpm/tpm_ftpm_tee: Fix error handling in ftpm_mod_init() Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 062/731] tpm/tpm_crb: Fix error message in __crb_relinquish_locality() Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 063/731] ovl: store lower path in ovl_inode Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 064/731] ovl: use ovl_copy_{real,upper}attr() wrappers Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 065/731] ovl: remove privs in ovl_copyfile() Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 066/731] ovl: remove privs in ovl_fallocate() Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 067/731] sched/fair: Cleanup task_util and capacity type Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 068/731] sched/uclamp: Fix relationship between uclamp and migration margin Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 069/731] sched/uclamp: Make task_fits_capacity() use util_fits_cpu() Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 070/731] sched/uclamp: Make select_idle_capacity() " Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 071/731] sched/fair: Removed useless update of p->recent_used_cpu Greg Kroah-Hartman
2022-12-28 14:32 ` [PATCH 5.15 072/731] sched/core: Introduce sched_asym_cpucap_active() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 073/731] sched/uclamp: Make asym_fits_capacity() use util_fits_cpu() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 074/731] cpuidle: dt: Return the correct numbers of parsed idle states Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 075/731] alpha: fix TIF_NOTIFY_SIGNAL handling Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 076/731] alpha: fix syscall entry in !AUDUT_SYSCALL case Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 077/731] x86/sgx: Reduce delay and interference of enclave release Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 078/731] PM: hibernate: Fix mistake in kerneldoc comment Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 079/731] fs: dont audit the capability check in simple_xattr_list() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 080/731] cpufreq: qcom-hw: Fix memory leak in qcom_cpufreq_hw_read_lut() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 081/731] selftests/ftrace: event_triggers: wait longer for test_event_enable Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 082/731] perf: Fix possible memleak in pmu_dev_alloc() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 083/731] lib/debugobjects: fix stat count and optimize debug_objects_mem_init Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 084/731] platform/x86: huawei-wmi: fix return value calculation Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 085/731] timerqueue: Use rb_entry_safe() in timerqueue_getnext() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 086/731] proc: fixup uptime selftest Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 087/731] lib/fonts: fix undefined behavior in bit shift for get_default_font Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 088/731] ocfs2: fix memory leak in ocfs2_stack_glue_init() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 089/731] MIPS: vpe-mt: fix possible memory leak while module exiting Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 090/731] MIPS: vpe-cmp: " Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 091/731] selftests/efivarfs: Add checking of the test return value Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 092/731] PNP: fix name memory leak in pnp_alloc_dev() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 093/731] perf/x86/intel/uncore: Fix reference count leak in sad_cfg_iio_topology() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 094/731] perf/x86/intel/uncore: Fix reference count leak in hswep_has_limit_sbox() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 095/731] perf/x86/intel/uncore: Fix reference count leak in snr_uncore_mmio_map() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 096/731] perf/x86/intel/uncore: Fix reference count leak in __uncore_imc_init_box() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 097/731] platform/chrome: cros_usbpd_notify: Fix error handling in cros_usbpd_notify_init() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 098/731] thermal: core: fix some possible name leaks in error paths Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 099/731] irqchip: gic-pm: Use pm_runtime_resume_and_get() in gic_probe() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 100/731] irqchip/wpcm450: Fix memory leak in wpcm450_aic_of_init() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 101/731] EDAC/i10nm: fix refcount leak in pci_get_dev_wrapper() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 102/731] SUNRPC: Return true/false (not 1/0) from bool functions Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 103/731] NFSD: Finish converting the NFSv2 GETACL result encoder Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 104/731] nfsd: dont call nfsd_file_put from client states seqfile display Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 105/731] genirq/irqdesc: Dont try to remove non-existing sysfs files Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 106/731] cpufreq: amd_freq_sensitivity: Add missing pci_dev_put() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 107/731] libfs: add DEFINE_SIMPLE_ATTRIBUTE_SIGNED for signed value Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 108/731] lib/notifier-error-inject: fix error when writing -errno to debugfs file Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 109/731] debugfs: fix error when writing negative value to atomic_t " Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 110/731] rapidio: fix possible name leaks when rio_add_device() fails Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 111/731] rapidio: rio: fix possible name leak in rio_register_mport() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 112/731] clocksource/drivers/sh_cmt: Access registers according to spec Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 113/731] mips: ralink: mt7621: define MT7621_SYSC_BASE with __iomem Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 114/731] mips: ralink: mt7621: soc queries and tests as functions Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 115/731] mips: ralink: mt7621: do not use kzalloc too early Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 116/731] futex: Move to kernel/futex/ Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 117/731] futex: Resend potentially swallowed owner death notification Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 118/731] cpu/hotplug: Make target_store() a nop when target == state Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 119/731] cpu/hotplug: Do not bail-out in DYING/STARTING sections Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 120/731] clocksource/drivers/timer-ti-dm: Fix missing clk_disable_unprepare in dmtimer_systimer_init_clock() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 121/731] ACPICA: Fix use-after-free in acpi_ut_copy_ipackage_to_ipackage() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 122/731] uprobes/x86: Allow to probe a NOP instruction with 0x66 prefix Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 123/731] x86/xen: Fix memory leak in xen_smp_intr_init{_pv}() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 124/731] x86/xen: Fix memory leak in xen_init_lock_cpu() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 125/731] xen/privcmd: Fix a possible warning in privcmd_ioctl_mmap_resource() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 126/731] PM: runtime: Do not call __rpm_callback() from rpm_idle() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 127/731] platform/chrome: cros_ec_typec: Cleanup switch handle return paths Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 128/731] platform/chrome: cros_ec_typec: zero out stale pointers Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 129/731] platform/x86: mxm-wmi: fix memleak in mxm_wmi_call_mx[ds|mx]() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 130/731] platform/x86: intel_scu_ipc: fix possible name leak in __intel_scu_ipc_register() Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 131/731] MIPS: BCM63xx: Add check for NULL for clk in clk_enable Greg Kroah-Hartman
2022-12-28 14:33 ` [PATCH 5.15 132/731] MIPS: OCTEON: warn only once if deprecated link status is being used Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 133/731] lockd: set other missing fields when unlocking files Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 134/731] fs: sysv: Fix sysv_nblocks() returns wrong value Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 135/731] rapidio: fix possible UAF when kfifo_alloc() fails Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 136/731] eventfd: change int to __u64 in eventfd_signal() ifndef CONFIG_EVENTFD Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 137/731] relay: fix type mismatch when allocating memory in relay_create_buf() Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 138/731] hfs: Fix OOB Write in hfs_asc2mac Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 139/731] rapidio: devices: fix missing put_device in mport_cdev_open Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 140/731] platform/mellanox: mlxbf-pmc: Fix event typo Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 141/731] wifi: ath9k: hif_usb: fix memory leak of urbs in ath9k_hif_usb_dealloc_tx_urbs() Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 142/731] wifi: ath9k: hif_usb: Fix use-after-free in ath9k_hif_usb_reg_in_cb() Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 143/731] wifi: rtl8xxxu: Fix reading the vendor of combo chips Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 144/731] drm/bridge: adv7533: remove dynamic lane switching from adv7533 bridge Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 145/731] libbpf: Fix use-after-free in btf_dump_name_dups Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 146/731] libbpf: Fix null-pointer dereference in find_prog_by_sec_insn() Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 147/731] ata: libata: move ata_{port,link,dev}_dbg to standard pr_XXX() macros Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 148/731] ata: add/use ata_taskfile::{error|status} fields Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 149/731] ata: libata: fix NCQ autosense logic Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 150/731] ipmi: kcs: Poll OBF briefly to reduce OBE latency Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 151/731] drm/amdgpu/powerplay/psm: Fix memory leak in power state init Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 152/731] powerpc: dts: t208x: Mark MAC1 and MAC2 as 10G Greg Kroah-Hartman
2022-12-29 16:00 ` Sean Anderson
2022-12-30 9:16 ` Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 153/731] media: v4l2-ctrls: Fix off-by-one error in integer menu control check Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 154/731] media: coda: jpeg: Add check for kmalloc Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 155/731] media: adv748x: afe: Select input port when initializing AFE Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 156/731] media: i2c: ad5820: Fix error path Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 157/731] venus: pm_helpers: Fix error check in vcodec_domains_get() Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 158/731] soreuseport: Fix socket selection for SO_INCOMING_CPU Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 159/731] media: exynos4-is: dont rely on the v4l2_async_subdev internals Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 160/731] libbpf: Btf dedup identical struct test needs check for nested structs/arrays Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 161/731] can: kvaser_usb: do not increase tx statistics when sending error message frames Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 162/731] can: kvaser_usb: kvaser_usb_leaf: Get capabilities from device Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 163/731] can: kvaser_usb: kvaser_usb_leaf: Rename {leaf,usbcan}_cmd_error_event to {leaf,usbcan}_cmd_can_error_event Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 164/731] can: kvaser_usb: kvaser_usb_leaf: Handle CMD_ERROR_EVENT Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 165/731] can: kvaser_usb_leaf: Set Warning state even without bus errors Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 166/731] can: kvaser_usb: make use of units.h in assignment of frequency Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 167/731] can: kvaser_usb_leaf: Fix improved state not being reported Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 168/731] can: kvaser_usb_leaf: Fix wrong CAN state after stopping Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 169/731] can: kvaser_usb_leaf: Fix bogus restart events Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 170/731] can: kvaser_usb: Add struct kvaser_usb_busparams Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 171/731] can: kvaser_usb: Compare requested bittiming parameters with actual parameters in do_set_{,data}_bittiming Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 172/731] drm/rockchip: lvds: fix PM usage counter unbalance in poweron Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 173/731] clk: renesas: r9a06g032: Repair grave increment error Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 174/731] spi: Update reference to struct spi_controller Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 175/731] drm/panel/panel-sitronix-st7701: Remove panel on DSI attach failure Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 176/731] ima: Handle -ESTALE returned by ima_filter_rule_match() Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 177/731] drm/msm/hdmi: drop unused GPIO support Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 178/731] drm/msm/hdmi: use devres helper for runtime PM management Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 179/731] bpf: Fix slot type check in check_stack_write_var_off Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 180/731] media: vivid: fix compose size exceed boundary Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 181/731] media: platform: exynos4-is: fix return value check in fimc_md_probe() Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 182/731] bpf: propagate precision in ALU/ALU64 operations Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 183/731] bpf: Check the other end of slot_type for STACK_SPILL Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 184/731] bpf: propagate precision across all frames, not just the last one Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 185/731] clk: qcom: gcc-sm8250: Use retention mode for USB GDSCs Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 186/731] mtd: Fix device name leak when register device failed in add_mtd_device() Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 187/731] Input: joystick - fix Kconfig warning for JOYSTICK_ADC Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 188/731] wifi: rsi: Fix handling of 802.3 EAPOL frames sent via control port Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 189/731] media: camss: Clean up received buffers on failed start of streaming Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 190/731] net, proc: Provide PROC_FS=n fallback for proc_create_net_single_write() Greg Kroah-Hartman
2022-12-28 19:44 ` patchwork-bot+netdevbpf
2022-12-28 14:34 ` [PATCH 5.15 191/731] rxrpc: Fix ack.bufferSize to be 0 when generating an ack Greg Kroah-Hartman
2022-12-28 14:34 ` [PATCH 5.15 192/731] bfq: fix waker_bfqq inconsistency crash Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 193/731] drm/radeon: Add the missed acpi_put_table() to fix memory leak Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 194/731] drm/mediatek: Modify dpi power on/off sequence Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 195/731] ASoC: pxa: fix null-pointer dereference in filter() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 196/731] libbpf: Fix uninitialized warning in btf_dump_dump_type_data Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 197/731] nvmet: only allocate a single slab for bvecs Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 198/731] regulator: core: fix unbalanced of node refcount in regulator_dev_lookup() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 199/731] amdgpu/pm: prevent array underflow in vega20_odn_edit_dpm_table() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 200/731] nvme: return err on nvme_init_non_mdts_limits fail Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 201/731] regulator: qcom-rpmh: Fix PMR735a S3 regulator spec Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 202/731] drm/fourcc: Add packed 10bit YUV 4:2:0 format Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 203/731] drm/fourcc: Fix vsub/hsub for Q410 and Q401 Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 204/731] integrity: Fix memory leakage in keyring allocation error path Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 205/731] ima: Fix misuse of dereference of pointer in template_desc_init_fields() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 206/731] block: clear ->slave_dir when dropping the main slave_dir reference Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 207/731] wifi: ath10k: Fix return value in ath10k_pci_init() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 208/731] drm/msm/a6xx: Fix speed-bin detection vs probe-defer Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 209/731] mtd: lpddr2_nvm: Fix possible null-ptr-deref Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 210/731] Input: elants_i2c - properly handle the reset GPIO when power is off Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 211/731] media: vidtv: Fix use-after-free in vidtv_bridge_dvb_init() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 212/731] media: solo6x10: fix possible memory leak in solo_sysfs_init() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 213/731] media: platform: exynos4-is: Fix error handling in fimc_md_init() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 214/731] media: videobuf-dma-contig: use dma_mmap_coherent Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 215/731] inet: add READ_ONCE(sk->sk_bound_dev_if) in inet_csk_bind_conflict() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 216/731] mtd: spi-nor: hide jedec_id sysfs attribute if not present Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 217/731] mtd: spi-nor: Fix the number of bytes for the dummy cycles Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 218/731] bpf: Move skb->len == 0 checks into __bpf_redirect Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 219/731] HID: hid-sensor-custom: set fixed size for custom attributes Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 220/731] pinctrl: k210: call of_node_put() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 221/731] ALSA: pcm: fix undefined behavior in bit shift for SNDRV_PCM_RATE_KNOT Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 222/731] ALSA: seq: fix undefined behavior in bit shift for SNDRV_SEQ_FILTER_USE_EVENT Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 223/731] regulator: core: use kfree_const() to free space conditionally Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 224/731] clk: rockchip: Fix memory leak in rockchip_clk_register_pll() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 225/731] drm/amdgpu: fix pci device refcount leak Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 226/731] bonding: fix link recovery in mode 2 when updelay is nonzero Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 227/731] mtd: maps: pxa2xx-flash: fix memory leak in probe Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 228/731] drbd: remove call to memset before free device/resource/connection Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 229/731] drbd: destroy workqueue when drbd device was freed Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 230/731] ASoC: qcom: Add checks for devm_kcalloc Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 231/731] media: vimc: Fix wrong function called when vimc_init() fails Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 232/731] media: imon: fix a race condition in send_packet() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 233/731] clk: imx8mn: rename vpu_pll to m7_alt_pll Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 234/731] clk: imx: replace osc_hdmi with dummy Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 235/731] clk: imx8mn: fix imx8mn_sai2_sels clocks list Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 236/731] clk: imx8mn: fix imx8mn_enet_phy_sels " Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 237/731] pinctrl: pinconf-generic: add missing of_node_put() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 238/731] media: dvb-core: Fix ignored return value in dvb_register_frontend() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 239/731] media: dvb-usb: az6027: fix null-ptr-deref in az6027_i2c_xfer() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 240/731] media: s5p-mfc: Add variant data for MFC v7 hardware for Exynos 3250 SoC Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 241/731] drm/tegra: Add missing clk_disable_unprepare() in tegra_dc_probe() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 242/731] ASoC: dt-bindings: wcd9335: fix reset line polarity in example Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 243/731] ASoC: mediatek: mtk-btcvsd: Add checks for write and read of mtk_btcvsd_snd Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 244/731] NFSv4.2: Clear FATTR4_WORD2_SECURITY_LABEL when done decoding Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 245/731] NFSv4.2: Fix a memory stomp in decode_attr_security_label Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 246/731] NFSv4.2: Fix initialisation of struct nfs4_label Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 247/731] NFSv4: Fix a credential leak in _nfs4_discover_trunking() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 248/731] NFSv4: Fix a deadlock between nfs4_open_recover_helper() and delegreturn Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 249/731] NFS: Fix an Oops in nfs_d_automount() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 250/731] ALSA: asihpi: fix missing pci_disable_device() Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 251/731] wifi: iwlwifi: mvm: fix double free on tx path Greg Kroah-Hartman
2022-12-28 14:35 ` [PATCH 5.15 252/731] ASoC: mediatek: mt8173: Fix debugfs registration for components Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 253/731] ASoC: mediatek: mt8173: Enable IRQ when pdata is ready Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 254/731] drm/amd/pm/smu11: BACO is supported when its in BACO state Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 255/731] drm/radeon: Fix PCI device refcount leak in radeon_atrm_get_bios() Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 256/731] drm/amdgpu: Fix PCI device refcount leak in amdgpu_atrm_get_bios() Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 257/731] drm/amdkfd: Fix memory leakage Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 258/731] ASoC: pcm512x: Fix PM disable depth imbalance in pcm512x_probe Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 259/731] netfilter: conntrack: set icmpv6 redirects as RELATED Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 260/731] Input: wistron_btns - disable on UML Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 261/731] bpf, sockmap: Fix repeated calls to sock_put() when msg has more_data Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 262/731] bpf, sockmap: Fix missing BPF_F_INGRESS flag when using apply_bytes Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 263/731] bpf, sockmap: Fix data loss caused by using apply_bytes on ingress redirect Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 264/731] bonding: uninitialized variable in bond_miimon_inspect() Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 265/731] spi: spidev: mask SPI_CS_HIGH in SPI_IOC_RD_MODE Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 266/731] wifi: mac80211: fix memory leak in ieee80211_if_add() Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 267/731] wifi: cfg80211: Fix not unregister reg_pdev when load_builtin_regdb_keys() fails Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 268/731] mt76: stop the radar detector after leaving dfs channel Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 269/731] wifi: mt76: mt7921: fix reporting of TX AGGR histogram Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 270/731] wifi: mt76: fix coverity overrun-call in mt76_get_txpower() Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 271/731] regulator: core: fix module refcount leak in set_supply() Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 272/731] clk: qcom: lpass-sc7180: Fix pm_runtime usage Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 273/731] clk: qcom: clk-krait: fix wrong div2 functions Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 274/731] hsr: Add a rcu-read lock to hsr_forward_skb() Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 275/731] hsr: Avoid double remove of a node Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 276/731] hsr: Disable netpoll Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 277/731] hsr: Synchronize sending frames to have always incremented outgoing seq nr Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 278/731] hsr: Synchronize sequence number updates Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 279/731] configfs: fix possible memory leak in configfs_create_dir() Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 280/731] regulator: core: fix resource leak in regulator_register() Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 281/731] hwmon: (jc42) Convert register access and caching to regmap/regcache Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 282/731] hwmon: (jc42) Restore the min/max/critical temperatures on resume Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 283/731] bpf, sockmap: fix race in sock_map_free() Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 284/731] ALSA: pcm: Set missing stop_operating flag at undoing trigger start Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 285/731] media: saa7164: fix missing pci_disable_device() Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 286/731] ALSA: mts64: fix possible null-ptr-defer in snd_mts64_interrupt Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 287/731] xprtrdma: Fix regbuf data not freed in rpcrdma_req_create() Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 288/731] SUNRPC: Fix missing release socket in rpc_sockname() Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 289/731] NFSv4.x: Fail client initialisation if state manager thread cant run Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 290/731] riscv, bpf: Emit fixed-length instructions for BPF_PSEUDO_FUNC Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 291/731] mmc: alcor: fix return value check of mmc_add_host() Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 292/731] mmc: moxart: " Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 293/731] mmc: mxcmmc: " Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 294/731] mmc: pxamci: " Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 295/731] mmc: rtsx_pci: " Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 296/731] mmc: rtsx_usb_sdmmc: " Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 297/731] mmc: toshsd: " Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 298/731] mmc: vub300: " Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 299/731] mmc: wmt-sdmmc: " Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 300/731] mmc: atmel-mci: " Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 301/731] mmc: omap_hsmmc: " Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 302/731] mmc: meson-gx: " Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 303/731] mmc: via-sdmmc: " Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 304/731] mmc: wbsd: " Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 305/731] mmc: mmci: " Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 306/731] mmc: renesas_sdhi: alway populate SCC pointer Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 307/731] memstick: ms_block: Add error handling support for add_disk() Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 308/731] memstick/ms_block: Add check for alloc_ordered_workqueue Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 309/731] mmc: core: Normalize the error handling branch in sd_read_ext_regs() Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 310/731] regulator: qcom-labibb: Fix missing of_node_put() in qcom_labibb_regulator_probe() Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 311/731] media: c8sectpfe: Add of_node_put() when breaking out of loop Greg Kroah-Hartman
2022-12-28 14:36 ` [PATCH 5.15 312/731] media: coda: Add check for dcoda_iram_alloc Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 313/731] media: coda: Add check for kmalloc Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 314/731] clk: samsung: Fix memory leak in _samsung_clk_register_pll() Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 315/731] spi: spi-gpio: Dont set MOSI as an input if not 3WIRE mode Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 316/731] wifi: rtl8xxxu: Add __packed to struct rtl8723bu_c2h Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 317/731] wifi: rtl8xxxu: Fix the channel width reporting Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 318/731] wifi: brcmfmac: Fix error return code in brcmf_sdio_download_firmware() Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 319/731] blktrace: Fix output non-blktrace event when blk_classic option enabled Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 320/731] bpf: Do not zero-extend kfunc return values Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 321/731] clk: socfpga: Fix memory leak in socfpga_gate_init() Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 322/731] net: vmw_vsock: vmci: Check memcpy_from_msg() Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 323/731] net: defxx: Fix missing err handling in dfx_init() Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 324/731] net: stmmac: selftests: fix potential memleak in stmmac_test_arpoffload() Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 325/731] net: stmmac: fix possible memory leak in stmmac_dvr_probe() Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 326/731] drivers: net: qlcnic: Fix potential memory leak in qlcnic_sriov_init() Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 327/731] of: overlay: fix null pointer dereferencing in find_dup_cset_node_entry() and find_dup_cset_prop() Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 328/731] ethernet: s2io: dont call dev_kfree_skb() under spin_lock_irqsave() Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 329/731] net: farsync: Fix kmemleak when rmmods farsync Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 330/731] net/tunnel: wait until all sk_user_data reader finish before releasing the sock Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 331/731] net: apple: mace: dont call dev_kfree_skb() under spin_lock_irqsave() Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 332/731] net: apple: bmac: " Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 333/731] net: emaclite: " Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 334/731] net: ethernet: dnet: " Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 335/731] hamradio: " Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 336/731] net: amd: lance: " Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 337/731] af_unix: call proto_unregister() in the error path in af_unix_init() Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 338/731] net: amd-xgbe: Fix logic around active and passive cables Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 339/731] net: amd-xgbe: Check only the minimum speed for active/passive cables Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 340/731] can: tcan4x5x: Remove invalid write in clear_interrupts Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 341/731] can: m_can: Call the RAM init directly from m_can_chip_config Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 342/731] can: tcan4x5x: Fix use of register error status mask Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 343/731] net: lan9303: Fix read error execution path Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 344/731] ntb_netdev: Use dev_kfree_skb_any() in interrupt context Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 345/731] sctp: sysctl: make extra pointers netns aware Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 346/731] Bluetooth: MGMT: Fix error report for ADD_EXT_ADV_PARAMS Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 347/731] Bluetooth: btintel: Fix missing free skb in btintel_setup_combined() Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 348/731] Bluetooth: btusb: dont call kfree_skb() under spin_lock_irqsave() Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 349/731] Bluetooth: hci_qca: " Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 350/731] Bluetooth: hci_ll: " Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 351/731] Bluetooth: hci_h5: " Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 352/731] Bluetooth: hci_bcsp: " Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 353/731] Bluetooth: hci_core: " Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 354/731] Bluetooth: RFCOMM: " Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 355/731] stmmac: fix potential division by 0 Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 356/731] i40e: Fix the inability to attach XDP program on downed interface Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 357/731] net: dsa: tag_8021q: avoid leaking ctx on dsa_tag_8021q_register() error path Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 358/731] apparmor: fix a memleak in multi_transaction_new() Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 359/731] apparmor: fix lockdep warning when removing a namespace Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 360/731] apparmor: Fix abi check to include v8 abi Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 361/731] crypto: hisilicon/qm - fix missing destroy qp_idr Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 362/731] crypto: sun8i-ss - use dma_addr instead u32 Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 363/731] crypto: nitrox - avoid double free on error path in nitrox_sriov_init() Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 364/731] scsi: core: Fix a race between scsi_done() and scsi_timeout() Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 365/731] apparmor: Use pointer to struct aa_label for lbs_cred Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 366/731] PCI: dwc: Fix n_fts[] array overrun Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 367/731] RDMA/core: Fix order of nldev_exit call Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 368/731] PCI: pci-epf-test: Register notifier if only core_init_notifier is enabled Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 369/731] f2fs: Fix the race condition of resize flag between resizefs Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 370/731] crypto: rockchip - do not do custom power management Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 371/731] crypto: rockchip - do not store mode globally Greg Kroah-Hartman
2022-12-28 14:37 ` [PATCH 5.15 372/731] crypto: rockchip - add fallback for cipher Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 373/731] crypto: rockchip - add fallback for ahash Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 374/731] crypto: rockchip - better handle cipher key Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 375/731] crypto: rockchip - remove non-aligned handling Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 376/731] crypto: rockchip - rework by using crypto_engine Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 377/731] apparmor: Fix memleak in alloc_ns() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 378/731] f2fs: fix to invalidate dcc->f2fs_issue_discard in error path Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 379/731] f2fs: fix normal discard process Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 380/731] f2fs: fix to destroy sbi->post_read_wq in error path of f2fs_fill_super() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 381/731] RDMA/irdma: Report the correct link speed Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 382/731] scsi: qla2xxx: Fix set-but-not-used variable warnings Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 383/731] RDMA/siw: Fix immediate work request flush to completion queue Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 384/731] IB/mad: Dont call to function that might sleep while in atomic context Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 385/731] PCI: vmd: Disable MSI remapping after suspend Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 386/731] RDMA/restrack: Release MR restrack when delete Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 387/731] RDMA/core: Make sure "ib_port" is valid when access sysfs node Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 388/731] RDMA/nldev: Return "-EAGAIN" if the cm_id isnt from expected port Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 389/731] RDMA/siw: Set defined status for work completion with undefined status Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 390/731] scsi: scsi_debug: Fix a warning in resp_write_scat() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 391/731] crypto: ccree - Remove debugfs when platform_driver_register failed Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 392/731] crypto: cryptd - Use request context instead of stack for sub-request Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 393/731] crypto: hisilicon/qm - add missing pci_dev_put() in q_num_set() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 394/731] RDMA/hns: Repacing dseg_len by macros in fill_ext_sge_inl_data() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 395/731] RDMA/hns: Fix ext_sge num error when post send Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 396/731] PCI: Check for alloc failure in pci_request_irq() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 397/731] RDMA/hfi: Decrease PCI device reference count in error path Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 398/731] crypto: ccree - Make cc_debugfs_global_fini() available for module init function Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 399/731] RDMA/hns: fix memory leak in hns_roce_alloc_mr() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 400/731] RDMA/rxe: Fix NULL-ptr-deref in rxe_qp_do_cleanup() when socket create failed Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 401/731] dt-bindings: imx6q-pcie: Fix clock names for imx6sx and imx8mq Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 402/731] dt-bindings: visconti-pcie: Fix interrupts array max constraints Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 403/731] scsi: hpsa: Fix possible memory leak in hpsa_init_one() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 404/731] crypto: tcrypt - Fix multibuffer skcipher speed test mem leak Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 405/731] padata: Always leave BHs disabled when running ->parallel() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 406/731] padata: Fix list iterator in padata_do_serial() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 407/731] scsi: mpt3sas: Fix possible resource leaks in mpt3sas_transport_port_add() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 408/731] scsi: hpsa: Fix error handling in hpsa_add_sas_host() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 409/731] scsi: hpsa: Fix possible memory leak in hpsa_add_sas_device() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 410/731] scsi: efct: Fix possible memleak in efct_device_init() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 411/731] scsi: scsi_debug: Fix a warning in resp_verify() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 412/731] scsi: scsi_debug: Fix a warning in resp_report_zones() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 413/731] scsi: fcoe: Fix possible name leak when device_register() fails Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 414/731] scsi: scsi_debug: Fix possible name leak in sdebug_add_host_helper() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 415/731] scsi: ipr: Fix WARNING in ipr_init() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 416/731] scsi: fcoe: Fix transport not deattached when fcoe_if_init() fails Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 417/731] scsi: snic: Fix possible UAF in snic_tgt_create() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 418/731] RDMA/nldev: Add checks for nla_nest_start() in fill_stat_counter_qps() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 419/731] f2fs: avoid victim selection from previous victim section Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 420/731] RDMA/nldev: Fix failure to send large messages Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 421/731] crypto: amlogic - Remove kcalloc without check Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 422/731] crypto: omap-sham - Use pm_runtime_resume_and_get() in omap_sham_probe() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 423/731] riscv/mm: add arch hook arch_clear_hugepage_flags Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 424/731] RDMA/hfi1: Fix error return code in parse_platform_config() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 425/731] RDMA/srp: Fix error return code in srp_parse_options() Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 426/731] PCI: mt7621: Rename mt7621_pci_ to mt7621_pcie_ Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 427/731] PCI: mt7621: Add sentinel to quirks table Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 428/731] orangefs: Fix sysfs not cleanup when dev init failed Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 429/731] RDMA/hns: Fix AH attr queried by query_qp Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 430/731] RDMA/hns: Fix PBL page MTR find Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 431/731] RDMA/hns: Fix page size cap from firmware Greg Kroah-Hartman
2022-12-28 14:38 ` [PATCH 5.15 432/731] RDMA/hns: Fix error code of CMD Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 433/731] crypto: img-hash - Fix variable dereferenced before check hdev->req Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 434/731] hwrng: amd - Fix PCI device refcount leak Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 435/731] hwrng: geode " Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 436/731] IB/IPoIB: Fix queue count inconsistency for PKEY child interfaces Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 437/731] RISC-V: Align the shadow stack Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 438/731] drivers: dio: fix possible memory leak in dio_init() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 439/731] serial: tegra: Read DMA status before terminating Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 440/731] serial: 8250_bcm7271: Fix error handling in brcmuart_init() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 441/731] class: fix possible memory leak in __class_register() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 442/731] vfio: platform: Do not pass return buffer to ACPI _RST method Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 443/731] uio: uio_dmem_genirq: Fix missing unlock in irq configuration Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 444/731] uio: uio_dmem_genirq: Fix deadlock between irq config and handling Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 445/731] usb: fotg210-udc: Fix ages old endianness issues Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 446/731] staging: vme_user: Fix possible UAF in tsi148_dma_list_add Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 447/731] usb: typec: Check for ops->exit instead of ops->enter in altmode_exit Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 448/731] usb: typec: tcpci: fix of node refcount leak in tcpci_register_port() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 449/731] usb: typec: tipd: Cleanup resources if devm_tps6598_psy_register fails Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 450/731] usb: typec: tipd: Fix spurious fwnode_handle_put in error path Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 451/731] extcon: usbc-tusb320: Add support for mode setting and reset Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 452/731] extcon: usbc-tusb320: Add support for TUSB320L Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 453/731] usb: typec: Factor out non-PD fwnode properties Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 454/731] extcon: usbc-tusb320: Factor out extcon into dedicated functions Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 455/731] extcon: usbc-tusb320: Add USB TYPE-C support Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 456/731] extcon: usbc-tusb320: Update state on probe even if no IRQ pending Greg Kroah-Hartman
2022-12-28 15:45 ` Alvin Šipraga
2022-12-28 21:04 ` Peter Rosin
2022-12-29 0:09 ` Peter Rosin
2022-12-30 9:15 ` Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 457/731] serial: amba-pl011: avoid SBSA UART accessing DMACR register Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 458/731] serial: pl011: Do not clear RX FIFO & RX interrupt in unthrottle Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 459/731] serial: stm32: move dma_request_chan() before clk_prepare_enable() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 460/731] serial: pch: Fix PCI device refcount leak in pch_request_dma() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 461/731] tty: serial: clean up stop-tx part in altera_uart_tx_chars() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 462/731] tty: serial: altera_uart_{r,t}x_chars() need only uart_port Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 463/731] serial: altera_uart: fix locking in polling mode Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 464/731] serial: sunsab: Fix error handling in sunsab_init() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 465/731] test_firmware: fix memory leak in test_firmware_init() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 466/731] misc: ocxl: fix possible name leak in ocxl_file_register_afu() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 467/731] ocxl: fix pci device refcount leak when calling get_function_0() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 468/731] misc: tifm: fix possible memory leak in tifm_7xx1_switch_media() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 469/731] misc: sgi-gru: fix use-after-free error in gru_set_context_option, gru_fault and gru_handle_user_call_os Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 470/731] firmware: raspberrypi: fix possible memory leak in rpi_firmware_probe() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 471/731] cxl: fix possible null-ptr-deref in cxl_guest_init_afu|adapter() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 472/731] cxl: fix possible null-ptr-deref in cxl_pci_init_afu|adapter() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 473/731] iio: temperature: ltc2983: make bulk write buffer DMA-safe Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 474/731] iio: adis: handle devices that cannot unmask the drdy pin Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 475/731] iio: adis: stylistic changes Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 476/731] iio:imu:adis: Move exports into IIO_ADISLIB namespace Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 477/731] iio: adis: add __adis_enable_irq() implementation Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 478/731] counter: stm32-lptimer-cnt: fix the check on arr and cmp registers update Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 479/731] coresight: trbe: remove cpuhp instance node before remove cpuhp state Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 480/731] usb: roles: fix of node refcount leak in usb_role_switch_is_parent() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 481/731] usb: gadget: f_hid: fix f_hidg lifetime vs cdev Greg Kroah-Hartman
2023-01-05 12:18 ` Lee Jones
2023-01-05 12:28 ` Greg Kroah-Hartman
2023-01-05 14:08 ` Lee Jones
2022-12-28 14:39 ` [PATCH 5.15 482/731] usb: gadget: f_hid: fix refcount leak on error path Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 483/731] drivers: mcb: fix resource leak in mcb_probe() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 484/731] mcb: mcb-parse: fix error handing in chameleon_parse_gdd() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 485/731] chardev: fix error handling in cdev_device_add() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 486/731] i2c: pxa-pci: fix missing pci_disable_device() on error in ce4100_i2c_probe Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 487/731] staging: rtl8192u: Fix use after free in ieee80211_rx() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 488/731] staging: rtl8192e: Fix potential use-after-free in rtllib_rx_Monitor() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 489/731] vme: Fix error not catched in fake_init() Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 490/731] gpiolib: Get rid of redundant else Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 491/731] gpiolib: cdev: fix NULL-pointer dereferences Greg Kroah-Hartman
2022-12-28 14:39 ` [PATCH 5.15 492/731] gpiolib: make struct comments into real kernel docs Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 493/731] gpiolib: protect the GPIO device against being dropped while in use by user-space Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 494/731] i2c: mux: reg: check return value after calling platform_get_resource() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 495/731] i2c: ismt: Fix an out-of-bounds bug in ismt_access() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 496/731] usb: storage: Add check for kcalloc Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 497/731] tracing/hist: Fix issue of losting command info in error_log Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 498/731] ksmbd: Fix resource leak in ksmbd_session_rpc_open() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 499/731] samples: vfio-mdev: Fix missing pci_disable_device() in mdpy_fb_probe() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 500/731] thermal/drivers/imx8mm_thermal: Validate temperature range Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 501/731] thermal/drivers/qcom/temp-alarm: Fix inaccurate warning for gen2 Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 502/731] thermal/drivers/qcom/lmh: Fix irq handler return value Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 503/731] fbdev: ssd1307fb: Drop optional dependency Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 504/731] fbdev: pm2fb: fix missing pci_disable_device() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 505/731] fbdev: via: Fix error in via_core_init() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 506/731] fbdev: vermilion: decrease reference count in error path Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 507/731] fbdev: ep93xx-fb: Add missing clk_disable_unprepare in ep93xxfb_probe() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 508/731] fbdev: geode: dont build on UML Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 509/731] fbdev: uvesafb: " Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 510/731] fbdev: uvesafb: Fixes an error handling path in uvesafb_probe() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 511/731] HSI: omap_ssi_core: fix unbalanced pm_runtime_disable() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 512/731] HSI: omap_ssi_core: fix possible memory leak in ssi_probe() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 513/731] power: supply: fix residue sysfs file in error handle route of __power_supply_register() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 514/731] perf trace: Return error if a system call doesnt exist Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 515/731] perf trace: Use macro RAW_SYSCALL_ARGS_NUM to replace number Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 516/731] perf trace: Handle failure when trace point folder is missed Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 517/731] perf symbol: correction while adjusting symbol Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 518/731] power: supply: z2_battery: Fix possible memleak in z2_batt_probe() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 519/731] HSI: omap_ssi_core: Fix error handling in ssi_init() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 520/731] power: supply: ab8500: Fix error handling in ab8500_charger_init() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 521/731] power: supply: fix null pointer dereferencing in power_supply_get_battery_info Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 522/731] perf stat: Refactor __run_perf_stat() common code Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 523/731] perf stat: Do not delay the workload with --delay Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 524/731] RDMA/siw: Fix pointer cast warning Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 525/731] fs/ntfs3: Avoid UBSAN error on true_sectors_per_clst() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 526/731] overflow: Implement size_t saturating arithmetic helpers Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 527/731] fs/ntfs3: Harden against integer overflows Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 528/731] iommu/sun50i: Fix reset release Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 529/731] iommu/sun50i: Consider all fault sources for reset Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 530/731] iommu/sun50i: Fix R/W permission check Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 531/731] iommu/sun50i: Fix flush size Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 532/731] iommu/rockchip: fix permission bits in page table entries v2 Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 533/731] phy: usb: s2 WoL wakeup_count not incremented for USB->Eth devices Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 534/731] include/uapi/linux/swab: Fix potentially missing __always_inline Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 535/731] pwm: tegra: Improve required rate calculation Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 536/731] fs/ntfs3: Fix slab-out-of-bounds read in ntfs_trim_fs Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 537/731] dmaengine: idxd: Fix crc_val field for completion record Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 538/731] rtc: rtc-cmos: Do not check ACPI_FADT_LOW_POWER_S0 Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 539/731] rtc: cmos: Fix event handler registration ordering issue Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 540/731] rtc: cmos: Fix wake alarm breakage Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 541/731] rtc: cmos: fix build on non-ACPI platforms Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 542/731] rtc: cmos: Call cmos_wake_setup() from cmos_do_probe() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 543/731] rtc: cmos: Call rtc_wake_setup() " Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 544/731] rtc: cmos: Eliminate forward declarations of some functions Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 545/731] rtc: cmos: Rename ACPI-related functions Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 546/731] rtc: cmos: Disable ACPI RTC event on removal Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 547/731] rtc: snvs: Allow a time difference on clock register read Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 548/731] rtc: pcf85063: Fix reading alarm Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 549/731] iommu/amd: Fix pci device refcount leak in ppr_notifier() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 550/731] iommu/fsl_pamu: Fix resource leak in fsl_pamu_probe() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 551/731] macintosh: fix possible memory leak in macio_add_one_device() Greg Kroah-Hartman
2022-12-28 14:40 ` [PATCH 5.15 552/731] macintosh/macio-adb: check the return value of ioremap() Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 553/731] powerpc/52xx: Fix a resource leak in an error handling path Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 554/731] cxl: Fix refcount leak in cxl_calc_capp_routing Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 555/731] powerpc/xmon: Fix -Wswitch-unreachable warning in bpt_cmds Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 556/731] powerpc/xive: add missing iounmap() in error path in xive_spapr_populate_irq_data() Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 557/731] phy: qcom-qmp: create copies of QMP PHY driver Greg Kroah-Hartman
2022-12-28 16:49 ` Vinod Koul [this message]
2022-12-31 11:56 ` Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 558/731] powerpc/perf: callchain validate kernel stack pointer bounds Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 559/731] powerpc/83xx/mpc832x_rdb: call platform_device_put() in error case in of_fsl_spi_probe() Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 560/731] powerpc/hv-gpci: Fix hv_gpci event list Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 561/731] selftests/powerpc: Fix resource leaks Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 562/731] iommu/sun50i: Remove IOMMU_DOMAIN_IDENTITY Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 563/731] pwm: sifive: Call pwm_sifive_update_clock() while mutex is held Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 564/731] pwm: mtk-disp: Fix the parameters calculated by the enabled flag of disp_pwm Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 565/731] pwm: mediatek: always use bus clock for PWM on MT7622 Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 566/731] remoteproc: sysmon: fix memory leak in qcom_add_sysmon_subdev() Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 567/731] remoteproc: qcom: q6v5: Fix potential null-ptr-deref in q6v5_wcss_init_mmio() Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 568/731] remoteproc: qcom_q6v5_pas: disable wakeup on probe fail or remove Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 569/731] remoteproc: qcom_q6v5_pas: detach power domains on remove Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 570/731] remoteproc: qcom_q6v5_pas: Fix missing of_node_put() in adsp_alloc_memory_region() Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 571/731] remoteproc: qcom: q6v5: Fix missing clk_disable_unprepare() in q6v5_wcss_qcs404_power_on() Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 572/731] powerpc/eeh: Drop redundant spinlock initialization Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 573/731] powerpc/pseries/eeh: use correct API for error log size Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 574/731] mfd: bd957x: Fix Kconfig dependency on REGMAP_IRQ Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 575/731] mfd: qcom_rpm: Fix an error handling path in qcom_rpm_probe() Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 576/731] mfd: pm8008: Remove driver data structure pm8008_data Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 577/731] mfd: pm8008: Fix return value check in pm8008_probe() Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 578/731] netfilter: flowtable: really fix NAT IPv6 offload Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 579/731] rtc: st-lpc: Add missing clk_disable_unprepare in st_rtc_probe() Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 580/731] rtc: pic32: Move devm_rtc_allocate_device earlier in pic32_rtc_probe() Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 581/731] rtc: pcf85063: fix pcf85063_clkout_control Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 582/731] nfsd: under NFSv4.1, fix double svc_xprt_put on rpc_create failure Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 583/731] net: macsec: fix net device access prior to holding a lock Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 584/731] mISDN: hfcsusb: dont call dev_kfree_skb/kfree_skb() under spin_lock_irqsave() Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 585/731] mISDN: hfcpci: " Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 586/731] mISDN: hfcmulti: " Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 587/731] block, bfq: fix possible uaf for bfqq->bic Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 588/731] selftests/bpf: Add test for unstable CT lookup API Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 589/731] net: enetc: avoid buffer leaks on xdp_do_redirect() failure Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 590/731] nfc: pn533: Clear nfc_target before being used Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 591/731] unix: Fix race in SOCK_SEQPACKETs unix_dgram_sendmsg() Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 592/731] r6040: Fix kmemleak in probe and remove Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 593/731] blk-iocost: simplify ioc_name Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 594/731] igc: Enhance Qbv scheduling by using first flag bit Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 595/731] igc: Use strict cycles for Qbv scheduling Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 596/731] igc: Add checking for basetime less than zero Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 597/731] igc: allow BaseTime 0 enrollment for Qbv Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 598/731] igc: recalculate Qbv end_time by considering cycle time Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 599/731] igc: Lift TAPRIO schedule restriction Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 600/731] igc: Set Qbv start_time and end_time to end_time if not being configured in GCL Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 601/731] rtc: mxc_v2: Add missing clk_disable_unprepare() Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 602/731] selftests: devlink: fix the fd redirect in dummy_reporter_test Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 603/731] openvswitch: Fix flow lookup to use unmasked key Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 604/731] soc: mediatek: pm-domains: Fix the power glitch issue Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 605/731] arm64: dts: mt8183: Fix Mali GPU clock Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 606/731] skbuff: Account for tail adjustment during pull operations Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 607/731] mailbox: mpfs: read the system controllers status Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 608/731] mailbox: arm_mhuv2: Fix return value check in mhuv2_probe() Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 609/731] mailbox: zynq-ipi: fix error handling while device_register() fails Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 610/731] net_sched: reject TCF_EM_SIMPLE case for complex ematch module Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 611/731] rxrpc: Fix missing unlock in rxrpc_do_sendmsg() Greg Kroah-Hartman
2022-12-28 14:41 ` [PATCH 5.15 612/731] myri10ge: Fix an error handling path in myri10ge_probe() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 613/731] net: stream: purge sk_error_queue in sk_stream_kill_queues() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 614/731] HID: amd_sfh: Add missing check for dma_alloc_coherent Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 615/731] rcu: Fix __this_cpu_read() lockdep warning in rcu_force_quiescent_state() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 616/731] arm64: make is_ttbrX_addr() noinstr-safe Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 617/731] video: hyperv_fb: Avoid taking busy spinlock on panic path Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 618/731] x86/hyperv: Remove unregister syscore call from Hyper-V cleanup Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 619/731] binfmt_misc: fix shift-out-of-bounds in check_special_flags Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 620/731] fs: jfs: fix shift-out-of-bounds in dbAllocAG Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 621/731] udf: Avoid double brelse() in udf_rename() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 622/731] jfs: Fix fortify moan in symlink Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 623/731] fs: jfs: fix shift-out-of-bounds in dbDiscardAG Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 624/731] ACPICA: Fix error code path in acpi_ds_call_control_method() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 625/731] nilfs2: fix shift-out-of-bounds/overflow in nilfs_sb2_bad_offset() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 626/731] nilfs2: fix shift-out-of-bounds due to too large exponent of block size Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 627/731] acct: fix potential integer overflow in encode_comp_t() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 628/731] hfs: fix OOB Read in __hfs_brec_find Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 629/731] drm/etnaviv: add missing quirks for GC300 Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 630/731] media: imx-jpeg: Disable useless interrupt to avoid kernel panic Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 631/731] brcmfmac: return error when getting invalid max_flowrings from dongle Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 632/731] wifi: ath9k: verify the expected usb_endpoints are present Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 633/731] wifi: ar5523: Fix use-after-free on ar5523_cmd() timed out Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 634/731] ASoC: codecs: rt298: Add quirk for KBL-R RVP platform Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 635/731] ipmi: fix memleak when unload ipmi driver Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 636/731] drm/amd/display: prevent memory leak Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 637/731] Revert "drm/amd/display: Limit max DSC target bpp for specific monitors" Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 638/731] qed (gcc13): use u16 for fid to be big enough Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 639/731] bpf: make sure skb->len != 0 when redirecting to a tunneling device Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 640/731] net: ethernet: ti: Fix return type of netcp_ndo_start_xmit() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 641/731] hamradio: baycom_epp: Fix return type of baycom_send_packet() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 642/731] wifi: brcmfmac: Fix potential shift-out-of-bounds in brcmf_fw_alloc_request() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 643/731] igb: Do not free q_vector unless new one was allocated Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 644/731] drm/amdgpu: Fix type of second parameter in trans_msg() callback Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 645/731] drm/amdgpu: Fix type of second parameter in odn_edit_dpm_table() callback Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 646/731] s390/ctcm: Fix return type of ctc{mp,}m_tx() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 647/731] s390/netiucv: Fix return type of netiucv_tx() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 648/731] s390/lcs: Fix return type of lcs_start_xmit() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 649/731] drm/msm: Use drm_mode_copy() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 650/731] drm/rockchip: " Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 651/731] drm/sti: " Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 652/731] drm/mediatek: Fix return type of mtk_hdmi_bridge_mode_valid() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 653/731] drivers/md/md-bitmap: check the return value of md_bitmap_get_counter() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 654/731] md/raid1: stop mdx_raid1 thread when raid1 array run failed Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 655/731] drm/amd/display: fix array index out of bound error in bios parser Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 656/731] net: add atomic_long_t to net_device_stats fields Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 657/731] ipv6/sit: use DEV_STATS_INC() to avoid data-races Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 658/731] mrp: introduce active flags to prevent UAF when applicant uninit Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 659/731] ppp: associate skb with a device at tx Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 660/731] bpf: Prevent decl_tag from being referenced in func_proto arg Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 661/731] ethtool: avoiding integer overflow in ethtool_phys_id() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 662/731] media: dvb-frontends: fix leak of memory fw Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 663/731] media: dvbdev: adopts refcnt to avoid UAF Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 664/731] media: dvb-usb: fix memory leak in dvb_usb_adapter_init() Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 665/731] blk-mq: fix possible memleak when register hctx failed Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 666/731] drm/amd/display: Use the largest vready_offset in pipe group Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 667/731] libbpf: Avoid enum forward-declarations in public API in C++ mode Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 668/731] regulator: core: fix use_count leakage when handling boot-on Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 669/731] wifi: mt76: do not run mt76u_status_worker if the device is not running Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 670/731] mmc: f-sdh30: Add quirks for broken timeout clock capability Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 671/731] mmc: renesas_sdhi: better reset from HS400 mode Greg Kroah-Hartman
2022-12-28 14:42 ` [PATCH 5.15 672/731] media: si470x: Fix use-after-free in si470x_int_in_callback() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 673/731] clk: st: Fix memory leak in st_of_quadfs_setup() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 674/731] crypto: hisilicon/hpre - fix resource leak in remove process Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 675/731] scsi: lpfc: Fix hard lockup when reading the rx_monitor from debugfs Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 676/731] scsi: ufs: Reduce the START STOP UNIT timeout Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 677/731] scsi: elx: libefc: Fix second parameter type in state callbacks Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 678/731] hugetlbfs: fix null-ptr-deref in hugetlbfs_parse_param() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 679/731] drm/fsl-dcu: Fix return type of fsl_dcu_drm_connector_mode_valid() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 680/731] drm/sti: Fix return type of sti_{dvo,hda,hdmi}_connector_mode_valid() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 681/731] orangefs: Fix kmemleak in orangefs_prepare_debugfs_help_string() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 682/731] orangefs: Fix kmemleak in orangefs_{kernel,client}_debug_init() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 683/731] tools/include: Add _RET_IP_ and math definitions to kernel.h Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 684/731] KVM: selftests: Fix build regression by using accessor function Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 685/731] hwmon: (jc42) Fix missing unlock on error in jc42_write() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 686/731] ALSA/ASoC: hda: move/rename snd_hdac_ext_stop_streams to hdac_stream.c Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 687/731] ALSA: hda: add snd_hdac_stop_streams() helper Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 688/731] ASoC: Intel: Skylake: Fix driver hang during shutdown Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 689/731] ASoC: mediatek: mt8173-rt5650-rt5514: fix refcount leak in mt8173_rt5650_rt5514_dev_probe() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 690/731] ASoC: audio-graph-card: fix refcount leak of cpu_ep in __graph_for_each_link() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 691/731] ASoC: rockchip: pdm: Add missing clk_disable_unprepare() in rockchip_pdm_runtime_resume() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 692/731] ASoC: mediatek: mt8183: fix refcount leak in mt8183_mt6358_ts3a227_max98357_dev_probe() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 693/731] ASoC: wm8994: Fix potential deadlock Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 694/731] ASoC: rockchip: spdif: Add missing clk_disable_unprepare() in rk_spdif_runtime_resume() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 695/731] ASoC: rt5670: Remove unbalanced pm_runtime_put() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 696/731] drm/i915/display: Dont disable DDI/Transcoder when setting phy test pattern Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 697/731] LoadPin: Ignore the "contents" argument of the LSM hooks Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 698/731] pstore: Switch pmsg_lock to an rt_mutex to avoid priority inversion Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 699/731] perf debug: Set debug_peo_args and redirect_to_stderr variable to correct values in perf_quiet_option() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 700/731] afs: Fix lost servers_outstanding count Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 701/731] pstore: Make sure CONFIG_PSTORE_PMSG selects CONFIG_RT_MUTEXES Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 702/731] ima: Simplify ima_lsm_copy_rule Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 703/731] ALSA: usb-audio: add the quirk for KT0206 device Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 704/731] ALSA: hda/realtek: Add quirk for Lenovo TianYi510Pro-14IOB Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 705/731] ALSA: hda/hdmi: Add HP Device 0x8711 to force connect list Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 706/731] usb: cdnsp: fix lack of ZLP for ep0 Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 707/731] usb: xhci-mtk: fix leakage of shared hcd when fail to set wakeup irq Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 708/731] arm64: dts: qcom: sm8250: fix USB-DP PHY registers Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 709/731] usb: dwc3: Fix race between dwc3_set_mode and __dwc3_set_mode Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 710/731] usb: dwc3: core: defer probe on ulpi_read_id timeout Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 711/731] xhci: Prevent infinite loop in transaction errors recovery for streams Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 712/731] HID: wacom: Ensure bootloader PID is usable in hidraw mode Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 713/731] HID: mcp2221: dont connect hidraw Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 714/731] loop: Fix the max_loop commandline argument treatment when it is set to 0 Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 715/731] 9p: set req refcount to zero to avoid uninitialized usage Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 716/731] security: Restrict CONFIG_ZERO_CALL_USED_REGS to gcc or clang > 15.0.6 Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 717/731] reiserfs: Add missing calls to reiserfs_security_free() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 718/731] iio: fix memory leak in iio_device_register_eventset() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 719/731] iio: adc: ad_sigma_delta: do not use internal iio_dev lock Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 720/731] iio: adc128s052: add proper .data members in adc128_of_match table Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 721/731] regulator: core: fix deadlock on regulator enable Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 722/731] floppy: Fix memory leak in do_floppy_init() Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 723/731] gcov: add support for checksum field Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 724/731] fbdev: fbcon: release buffer when fbcon_do_set_font() failed Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 725/731] ovl: fix use inode directly in rcu-walk mode Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 726/731] btrfs: do not BUG_ON() on ENOMEM when dropping extent items for a range Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 727/731] scsi: qla2xxx: Fix crash when I/O abort times out Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 728/731] net: stmmac: fix errno when create_singlethread_workqueue() fails Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 729/731] media: dvbdev: fix build warning due to comments Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 730/731] media: dvbdev: fix refcnt bug Greg Kroah-Hartman
2022-12-28 14:43 ` [PATCH 5.15 731/731] extcon: usbc-tusb320: Call the Type-C IRQ handler only if a port is registered Greg Kroah-Hartman
2022-12-28 19:08 ` [PATCH 5.15 000/731] 5.15.86-rc1 review Florian Fainelli
2022-12-28 20:42 ` Slade Watkins
2022-12-29 3:42 ` Bagas Sanjaya
2022-12-29 3:50 ` Ron Economos
2022-12-29 7:54 ` Thierry Reding
2022-12-29 13:42 ` Guenter Roeck
2022-12-29 14:40 ` Pavel Machek
2022-12-29 16:56 ` Nathan Chancellor
2022-12-29 23:26 ` Shuah Khan
2022-12-30 7:28 ` Naresh Kamboju
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