[PATCH 5.10 / 5.15] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs

[PATCH 5.10 / 5.15] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs

[Guilherme G. Piccoli]

From: Deepak Sharma <deepak.sharma@amd.com>

commit a8fb40966f19ff81520d9ccf8f7e2b95201368b8 upstream.

All Zen or newer CPU which support C3 shares cache. Its not necessary to
flush the caches in software before entering C3. This will cause drop in
performance for the cores which share some caches. ARB_DIS is not used
with current AMD C state implementation. So set related flags correctly.

Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Guilherme G. Piccoli <gpiccoli@igalia.com>
---


Hi folks, this is a very simple optimization that might be read
as a fix IMO, since it's setting the flags correctly for the Zen CPUs.
It was built/boot tested in the Steam Deck.

The backport for stable was a suggestion from Greg [0], so lemme
know if any of you see an issue with that, or if we should target
other stable versions (or less versions, maybe only 5.15).
Cheers,


Guilherme


[0] https://github.com/ValveSoftware/SteamOS/issues/954#issuecomment-1368182597

 arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index 49ae4e1ac9cd..d28d43d774a2 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
 		 */
 		flags->bm_control = 0;
 	}
+	if (c->x86_vendor == X86_VENDOR_AMD && c->x86 >= 0x17) {
+		/*
+		 * For all AMD Zen or newer CPUs that support C3, caches
+		 * should not be flushed by software while entering C3
+		 * type state. Set bm->check to 1 so that kernel doesn't
+		 * need to execute cache flush operation.
+		 */
+		flags->bm_check = 1;
+		/*
+		 * In current AMD C state implementation ARB_DIS is no longer
+		 * used. So set bm_control to zero to indicate ARB_DIS is not
+		 * required while entering C3 type state.
+		 */
+		flags->bm_control = 0;
+	}
 }
 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
 
-- 
2.39.0

Re: [PATCH 5.10 / 5.15] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs

[Greg KH]

On Wed, Jan 25, 2023 at 06:51:45PM -0300, Guilherme G. Piccoli wrote:
> From: Deepak Sharma <deepak.sharma@amd.com>
> 
> commit a8fb40966f19ff81520d9ccf8f7e2b95201368b8 upstream.
> 
> All Zen or newer CPU which support C3 shares cache. Its not necessary to
> flush the caches in software before entering C3. This will cause drop in
> performance for the cores which share some caches. ARB_DIS is not used
> with current AMD C state implementation. So set related flags correctly.
> 
> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
> Acked-by: Thomas Gleixner <tglx@linutronix.de>
> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> Signed-off-by: Guilherme G. Piccoli <gpiccoli@igalia.com>
> ---
> 
> 
> Hi folks, this is a very simple optimization that might be read
> as a fix IMO, since it's setting the flags correctly for the Zen CPUs.
> It was built/boot tested in the Steam Deck.
> 
> The backport for stable was a suggestion from Greg [0], so lemme
> know if any of you see an issue with that, or if we should target
> other stable versions (or less versions, maybe only 5.15).
> Cheers,

Looks good, thanks for the backport, now queued up!

greg k-h