From: Matt Atwood <matthew.s.atwood@intel.com>
To: Lionel Landwerlin <lionel.g.landwerlin@intel.com>,
<intel-gfx@lists.freedesktop.org>
Cc: <intel-gfx@lists.freedesktop.org>, <stable@vger.kernel.org>
Subject: Re: [Intel-gfx] [v2] drm/i915: disable sampler indirect state in bindless heap
Date: Thu, 30 Mar 2023 12:27:33 -0700 [thread overview]
Message-ID: <ZCXipYU8ULR6eEPc@msatwood-mobl> (raw)
In-Reply-To: <20230330174740.2775776-1-lionel.g.landwerlin@intel.com>
On Thu, Mar 30, 2023 at 08:47:40PM +0300, Lionel Landwerlin wrote:
> By default the indirect state sampler data (border colors) are stored
> in the same heap as the SAMPLER_STATE structure. For userspace drivers
> that can be 2 different heaps (dynamic state heap & bindless sampler
> state heap). This means that border colors have to copied in 2
> different places so that the same SAMPLER_STATE structure find the
> right data.
>
> This change is forcing the indirect state sampler data to only be in
> the dynamic state pool (more convinient for userspace drivers, they
convenient
> only have to have one copy of the border colors). This is reproducing
> the behavior of the Windows drivers.
>
> BSpec: 46052
>
Assuming still good CI results..
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Cc: stable@vger.kernel.org
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++++++++++++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 4aecb5a7b6318..f298dc461a72f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1144,6 +1144,7 @@
> #define ENABLE_SMALLPL REG_BIT(15)
> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
> +#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
>
> #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
> #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e7ee24bcad893..0ce1c8c23c631 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2535,6 +2535,25 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> ENABLE_SMALLPL);
> }
>
> + if (GRAPHICS_VER(i915) >= 11) {
> + /* This is not a Wa (although referred to as
> + * WaSetInidrectStateOverride in places), this allows
> + * applications that reference sampler states through
> + * the BindlessSamplerStateBaseAddress to have their
> + * border color relative to DynamicStateBaseAddress
> + * rather than BindlessSamplerStateBaseAddress.
> + *
> + * Otherwise SAMPLER_STATE border colors have to be
> + * copied in multiple heaps (DynamicStateBaseAddress &
> + * BindlessSamplerStateBaseAddress)
> + *
> + * BSpec: 46052
> + */
> + wa_mcr_masked_en(wal,
> + GEN10_SAMPLER_MODE,
> + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> + }
> +
> if (GRAPHICS_VER(i915) == 11) {
> /* This is not an Wa. Enable for better image quality */
> wa_masked_en(wal,
> --
> 2.34.1
>
next prev parent reply other threads:[~2023-03-30 19:28 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-09 15:26 [PATCH] drm/i915: disable sampler indirect state in bindless heap Lionel Landwerlin
2023-03-28 10:44 ` [Intel-gfx] " Kalvala, Haridhar
2023-03-28 22:49 ` Matt Atwood
2023-03-30 17:19 ` Lionel Landwerlin
2023-03-31 7:05 ` Kalvala, Haridhar
2023-04-03 18:22 ` Kalvala, Haridhar
2023-04-03 21:59 ` Lionel Landwerlin
2023-03-30 17:47 ` [v2] " Lionel Landwerlin
2023-03-30 19:27 ` Matt Atwood [this message]
2023-03-30 19:38 ` [Intel-gfx] " Matt Atwood
2023-03-30 20:43 ` Lionel Landwerlin
2023-03-30 20:42 ` [v3] " Lionel Landwerlin
2023-04-06 21:22 ` [Intel-gfx] " Matt Atwood
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