From: David Laight <David.Laight@ACULAB.COM>
To: "'H. Peter Anvin'" <hpa@zytor.com>,
Nick Desaulniers <ndesaulniers@google.com>,
Brian Gerst <brgerst@gmail.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Sedat Dilek <sedat.dilek@gmail.com>,
stable <stable@vger.kernel.org>,
Jesse Brandeburg <jesse.brandeburg@intel.com>,
"kernelci . org bot" <bot@kernelci.org>,
Andy Shevchenko <andriy.shevchenko@intel.com>,
Ilie Halip <ilie.halip@gmail.com>,
"the arch/x86 maintainers" <x86@kernel.org>,
Marco Elver <elver@google.com>,
"Paul E. McKenney" <paulmck@kernel.org>,
Daniel Axtens <dja@axtens.net>,
"Masahiro Yamada" <yamada.masahiro@socionext.com>,
Luc Van Oostenryck <luc.vanoostenryck@gmail.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
clang-built-linux <clang-built-linux@googlegroups.com>
Subject: RE: [PATCH] x86: bitops: fix build regression
Date: Sun, 10 May 2020 11:59:17 +0000 [thread overview]
Message-ID: <b1072e7116774e0c9e6e7e6f55bae4a3@AcuMS.aculab.com> (raw)
In-Reply-To: <8f53b69e-86cc-7ff9-671e-5e0a67ff75a2@zytor.com>
From: Peter Anvin
> Sent: 08 May 2020 18:32
> On 2020-05-08 10:21, Nick Desaulniers wrote:
> >>
> >> One last suggestion. Add the "b" modifier to the mask operand: "orb
> >> %b1, %0". That forces the compiler to use the 8-bit register name
> >> instead of trying to deduce the width from the input.
> >
> > Ah right: https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html#x86Operandmodifiers
> >
> > Looks like that works for both compilers. In that case, we can likely
> > drop the `& 0xff`, too. Let me play with that, then I'll hopefully
> > send a v3 today.
> >
>
> Good idea. I requested a while ago that they document these modifiers; they
> chose not to document them all which in some ways is good; it shows what they
> are willing to commit to indefinitely.
I thought the intention here was to explicitly do a byte access.
If the constant bit number has had a div/mod by 8 done on it then
the address can be misaligned - so you mustn't do a non-byte sized
locked access.
OTOH the original base address must be aligned.
Looking at some instruction timing, BTS/BTR aren't too bad if the
bit number is a constant. But are 6 or 7 clocks slower if it is in %cl.
Given these are locked RMW bus cycles they'll always be slow!
How about an asm multi-part alternative that uses a byte offset
and byte constant if the compiler thinks the mask is constant
or a 4-byte offset and 32bit mask if it doesn't.
The other alternative is to just use BTS/BTS and (maybe) rely on the
assembler to add in the word offset to the base address.
David
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Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)
next prev parent reply other threads:[~2020-05-10 11:59 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-05 17:44 [PATCH] x86: bitops: fix build regression Nick Desaulniers
2020-05-05 18:07 ` hpa
2020-05-05 18:22 ` Nick Desaulniers
2020-05-07 11:34 ` Peter Zijlstra
2020-05-07 14:00 ` Brian Gerst
2020-05-07 19:19 ` Nick Desaulniers
2020-05-07 22:29 ` Nick Desaulniers
2020-05-08 1:57 ` Brian Gerst
2020-05-08 17:21 ` Nick Desaulniers
2020-05-08 17:31 ` H. Peter Anvin
2020-05-10 11:59 ` David Laight [this message]
2020-05-10 12:33 ` hpa
2020-05-07 19:29 ` hpa
2020-05-06 4:30 ` Nathan Chancellor
2020-05-06 9:22 ` Sedat Dilek
2020-05-06 15:41 ` Nathan Chancellor
2020-05-06 16:37 ` Nick Desaulniers
2020-05-06 16:55 ` Ilie Halip
2020-05-07 6:18 ` Brian Gerst
2020-05-07 7:02 ` hpa
2020-05-07 13:32 ` Brian Gerst
2020-05-07 15:09 ` David Laight
2020-05-07 19:31 ` hpa
2020-05-07 19:29 ` hpa
2020-05-07 7:44 ` David Laight
2020-05-07 7:59 ` hpa
2020-05-07 8:35 ` David Laight
2020-05-07 8:38 ` hpa
2020-05-07 9:17 ` Andy Shevchenko
2020-05-07 19:22 ` Nick Desaulniers
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