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From: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
To: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Sebastian Andrzej Siewior <sebastian.siewior@linutronix.de>,
	Ken Goldman <kgold@linux.vnet.ibm.com>,
	Haris Okanovic <haris.okanovic@ni.com>,
	linux-rt-users@vger.kernel.org, linux-kernel@vger.kernel.org,
	tpmdd-devel@lists.sourceforge.net, harisokn@gmail.com,
	julia.cartwright@ni.com, gratian.crisan@ni.com,
	scott.hartman@ni.com, chris.graf@ni.com, brad.mouring@ni.com,
	jonathan.david@ni.com, peterhuewe@gmx.de, tpmdd@selhorst.net,
	eric.gardiner@ni.com
Subject: Re: [tpmdd-devel] [PATCH v2] tpm_tis: fix stall after iowrite*()s
Date: Sat, 19 Aug 2017 20:03:46 +0300	[thread overview]
Message-ID: <20170819170346.6mytggeq3rgu6b2q@linux.intel.com> (raw)
In-Reply-To: <20170817171732.GA22792@obsidianresearch.com>

On Thu, Aug 17, 2017 at 11:17:32AM -0600, Jason Gunthorpe wrote:
> On Thu, Aug 17, 2017 at 12:38:07PM +0200, Sebastian Andrzej Siewior wrote:
> 
> > > I worry a bit about "appears to fix".  It seems odd that the TPM device
> > > driver would be the first code to uncover this.  Can anyone confirm that the
> > > chipset does indeed have this bug?
> > 
> > What Haris says makes sense. It is just not all architectures
> > accumulate/ batch writes to HW.
> 
> It doesn't seem that odd to me.. In modern Intel chipsets the physical
> LPC bus is used for very little. Maybe some flash and possibly a
> winbond super IO at worst?  Plus the TPM.
> 
> I can't confirm what Intel has done, but if writes are posted, then it
> is not a 'bug', but expected operation for a PCI/LPC bridge device to
> have an ordered queue of posted writes, and thus higher latency when
> processing reads due to ordering requirments.
> 
> Other drivers may not see it because most LPC usages would not be
> write heavy, or might use IO instructions which are not posted..
> 
> I can confirm that my ARM systems with a custom PCI-LPC bridge will
> have exactly the same problem, and that the readl is the only
> solution.
> 
> This is becuase writes to LPC are posted over PCI and will be buffered
> in the root complex, device end port and internally in the LPC
> bridge. Since they are posted there is no way for the CPU to know when
> the complete and when it would be 'low latency' to issue a read.

What you say makes sense to me but wasn't the patch tried with SPI-TPM,
not LPC? Anyway, what you're saying probably still applies.

/Jarkko

      parent reply	other threads:[~2017-08-19 17:03 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20170804215651.29247-1-haris.okanovic@ni.com>
2017-08-14 22:53 ` [PATCH] " Haris Okanovic
2017-08-15  6:11   ` Alexander Stein
2017-08-15 20:10     ` Haris Okanovic
     [not found] ` <20170804215651.29247-1-haris.okanovic-acOepvfBmUk@public.gmane.org>
2017-08-15 20:13   ` [PATCH v2] " Haris Okanovic
2017-08-16 21:15     ` [tpmdd-devel] " Ken Goldman
2017-08-17  5:57       ` Alexander Stein
2017-08-17 10:38       ` Sebastian Andrzej Siewior
     [not found]         ` <20170817103807.ubrbylnud6wxod3s-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
2017-08-17 17:17           ` Jason Gunthorpe
     [not found]             ` <20170817171732.GA22792-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-08-17 20:12               ` Haris Okanovic
2017-08-19 17:03             ` Jarkko Sakkinen [this message]

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