From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07AADC433F5 for ; Tue, 21 Dec 2021 08:23:02 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E39F681C08; Tue, 21 Dec 2021 09:23:00 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1640074981; bh=syt+SWn5iLCidkHzxLR1xavHEPzyDR6JJV1Lpi9yl+8=; h=Date:Subject:To:Cc:References:From:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=bdB0raO6+HQkx24aJTPVS5DcIV4vThk7easLk1C5RwCU1RTx5UDmbvLyThCM28yu2 SjRvjLDyR90yRUcQVQti+Q7bZW4cvtw7aU1+tjlxd4CZHjvwpeeM8u0SSbiFlFkF/Q xN5d8YrdgenrqAdl8r1qbSeJxxrIsrMc+HnIib/iNP6F9jfqIPNgz4cSFOsMsNS+Yz 3tEx0qGRaZJCt/y0dwTLrZY/Q7b3G4JcSBsEKS97kQyhGgNMOWw1OF//lqR5/TkBkS vjh8CnTNCmP+nrn4LXv6gU5Vmt2aR5Kqvng/PizOwrr18RaHG70K+iZ+T3rZjlyCEH nVBtrhZQDX43A== Received: by phobos.denx.de (Postfix, from userid 109) id 480B682F03; Tue, 21 Dec 2021 09:22:59 +0100 (CET) Received: from mout-u-204.mailbox.org (mout-u-204.mailbox.org [91.198.250.253]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8269D8192E for ; Tue, 21 Dec 2021 09:22:56 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp102.mailbox.org (smtp102.mailbox.org [IPv6:2001:67c:2050:105:465:1:3:0]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-204.mailbox.org (Postfix) with ESMTPS id 4JJ8bM70YTzQk98; Tue, 21 Dec 2021 09:22:55 +0100 (CET) Message-ID: <0b0d4f31-db5c-cef9-df00-1c5b71682fcd@denx.de> Date: Tue, 21 Dec 2021 09:22:51 +0100 MIME-Version: 1.0 Subject: Re: [PATCH u-boot-marvell 03/10] pci: pci_mvebu: Move setup for BAR[0] where other BARs are setup Content-Language: en-US To: =?UTF-8?Q?Marek_Beh=c3=ban?= Cc: u-boot@lists.denx.de, =?UTF-8?Q?Pali_Roh=c3=a1r?= , =?UTF-8?Q?Marek_Beh=c3=ban?= References: <20211111153549.29111-1-kabel@kernel.org> <20211111153549.29111-4-kabel@kernel.org> From: Stefan Roese In-Reply-To: <20211111153549.29111-4-kabel@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On 11/11/21 16:35, Marek Behún wrote: > From: Pali Rohár > > Function mvebu_pcie_setup_wins() sets up all other BARs, so move setup of > BAR[0] to this function to have common code at one place. > > In the past, commit 193a1e9f196b ("pci: pci_mvebu: set BAR0 after memory > space is set") moved setup of BAR[0] to another location, due to ath10k > not working in kernel, but the reason why was unknown, but it seems to > work now, and we think the issue then was cause by the PCIe Root Port > presenting itself as a Memory Controller and therefore U-Boot's code > have overwritten the BAR. Since the driver now ignores any write > operations to PCIe Root Port BARs, this should not be an issue anymore. > > Signed-off-by: Pali Rohár > Signed-off-by: Marek Behún Applied to u-boot-marvell/next Thanks, Stefan > --- > drivers/pci/pci_mvebu.c | 12 +++++++----- > 1 file changed, 7 insertions(+), 5 deletions(-) > > diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c > index 278dc2756f..97c7b5604f 100644 > --- a/drivers/pci/pci_mvebu.c > +++ b/drivers/pci/pci_mvebu.c > @@ -335,7 +335,9 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf, > > /* > * Setup PCIE BARs and Address Decode Wins: > - * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks > + * BAR[0] -> internal registers > + * BAR[1] -> covers all DRAM banks > + * BAR[2] -> disabled > * WIN[0-3] -> DRAM bank[0-3] > */ > static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie) > @@ -386,6 +388,10 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie) > writel(0, pcie->base + PCIE_BAR_HI_OFF(1)); > writel(((size - 1) & 0xffff0000) | 0x1, > pcie->base + PCIE_BAR_CTRL_OFF(1)); > + > + /* Setup BAR[0] to internal registers. */ > + writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0)); > + writel(0, pcie->base + PCIE_BAR_HI_OFF(0)); > } > > static int mvebu_pcie_probe(struct udevice *dev) > @@ -501,10 +507,6 @@ static int mvebu_pcie_probe(struct udevice *dev) > pcie->io.start, MBUS_PCI_IO_SIZE, PCI_REGION_IO); > hose->region_count = 3; > > - /* Set BAR0 to internal registers */ > - writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0)); > - writel(0, pcie->base + PCIE_BAR_HI_OFF(0)); > - > /* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */ > pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] = > PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8); > Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de