[U-Boot] [PATCH 5/7] Enable POST memory test for corenet_ds

[Wolfgang Denk <wd@denx.de>]

Dear York Sun,

In message <1282944356-4020-5-git-send-email-yorksun@freescale.com> you wrote:
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
>  include/configs/corenet_ds.h |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
> index cf316e0..627f851 100644
> --- a/include/configs/corenet_ds.h
> +++ b/include/configs/corenet_ds.h
> @@ -87,6 +87,7 @@
>  #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
>  #endif
>  
> +#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
>  #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
>  #define CONFIG_SYS_MEMTEST_END		0x00400000
>  #define CONFIG_SYS_ALT_MEMTEST
> @@ -272,6 +273,7 @@
>  
>  #define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
>  #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
> +#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_MPC85xx_PIC_ADDR + offsetof(ccsr_pic_t, tfrr))

The previous patch suggested that you were "Using PIC TFRR register
for post word load/store for generic" - then no such define should be
needed for any 85xx board.

Best regards,

Wolfgang Denk

-- 
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